Low Power Emulation for Power Intensive Designs

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1 Low Power Emulation for Power Intensive Designs Harpreet Kaur Mohit Jain Piyush Kumar Gupta Jitendra Aggarwal Accellera Systems Initiative 1

2 Agenda Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 2

3 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 3

4 Introduction Smaller technology nodes, higher leakage current. Accellera Systems Initiative 4

Introduction Low Power Verification, Needs and Future SoC Need : More performance, more features, more complex, but Low power budgets Eg mobile phones Consequence: More and more power domains,

5 Introduction Low Power Verification, Needs and Future SoC Need : More performance, more features, more complex, but Low power budgets Eg mobile phones Consequence: More and more power domains, complex power optimization features. Typical Application Processor for a Smartphone Power verification - equally important as Functional verification. Faster verification of the design with all Power features. Accellera Systems Initiative 5

6 Introduction Power Aware Verification SoC / Sub-system Design Functional Verification Simulation in practice Emulation SoC / Sub-system Design Power Verification Simulation Emulation not in practice Accellera Systems Initiative 6

7 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 7

8 Power Aware Design Power Verification - Simulation Different power management schemes Isolation Retention Level shifter Clock gating And many more These schemes defined through UPF (IEEE 1801) Accellera Systems Initiative 8

Power Aware Simulation Power Verification -

Hard Macros supply behavior is provided by the

to X When supply is on Normal simulation Iso cell

9 Power Aware Simulation Power Verification - Simulation RTL Hard Macro Power Aware Simulator UPF Hard Macros supply behavior is provided by the simulation model. Behavior Actual circuit power behavior. When supply is off Internals and outputs corrupted to X When supply is on Normal simulation Iso cell VDD1 OFF VDD3 ON X at internals and outputs Retention cell VDD2 ON VDD Normal simulation Accellera Systems Initiative 9

10 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 10

complete regression suite with complex power scenarios can be exercised in a faster way.

11 Need for Low Power Emulation Power Verification - Emulation Complete power verification very expensive on simulation Large no. of power domains, large runtime to simulate. Emulation runs on hardware many magnitudes faster than simulation. complete regression suite with complex power scenarios can be exercised in a faster way. Flow No RTL or UPF special changes compared to simulation. Hard Macro RTL Hard Macro Power Aware Emulator UPF Synthesizable model with power functionality required. Accellera Systems Initiative 11

Features VDD1 Power Verification - Emulation Today Emulators support various

supply is off Internals and outputs corrupt to X on waveform When supply is on

12 Features VDD1 Power Verification - Emulation Today Emulators support various Power Simulation features: Multiple power domains Hierarchical power domain connections Special power cells viz. isolation, retention, switches X corruption of power domains Behavior When supply is off Internals and outputs corrupt to X on waveform When supply is on Normal simulation Iso cell OFF VDD3 ON X at internals and outputs Retention cell VDD2 ON VDD Normal simulation Accellera Systems Initiative 12

13 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 13

14 Test PD Architecture Low Power Emulation Example TEST AXI DRIVER PROXY AXI DRIVER BFM TOP DOMAIN DPREG AXI SPHD SPREG DOMAIN 1 erom SPHDLV ECC DOMAIN 2 APIP AAPD RFF DOMAIN 3 PLL Accellera Systems Initiative 14

15 Low Power Emulation Example Low Power Emulation flow on TestPD RTL UPF Simulation model for Hard Macros SIMULATION SETUP TESTBENCH RTL UPF Emulation model for Hard Macros HW BFM part SW proxy part EMULATION SETUP Hardware compile / elab Software compile / elab Running test cases Accellera Systems Initiative 15 Monitor results through log files and waveforms

16 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 16

Hard Macros Power port connections Problem: Tool didn

u_rds_testpd_ioring/io_power_vdd_gnd_0/vdd Solution:

reg/wire and connect it with UPF -upf_options

Synthesis tool will simply optimize power port defined

VDD1 VDD2 vdd vddtop PLL Issues faced/ Solutions

17 Hard Macros Power port connections Problem: Tool didn t understand the port connection, defined in RTL, through UPF file. connect_supply_net vddtop -ports u_rds_testpd_ioring/io_power_vdd_gnd_0/vdd Solution: Guide the tool to preserve power port defined as reg/wire and connect it with UPF -upf_options "-extend_upf_connect_net_to_rtl_net_flow NOTE: Synthesis tool will simply optimize power port defined as reg in verilog emulation model. VDD1 VDD2 vdd vddtop PLL Issues faced/ Solutions module PLL_TOP (clk, div, en, out_clk); input clk, en, div; output outclk; reg vdd = 1; reg gnd= 0; (clk)begin if (!vdd ).. Accellera Systems Initiative 17

X value support in Emulation Problem: X value doesn t exist in Emulation, then how to highlight an OFF power domain? Solution: X visibility provided in waveforms by the tool.

18 X value support in Emulation Problem: X value doesn t exist in Emulation, then how to highlight an OFF power domain? Solution: X visibility provided in waveforms by the tool. Power Sequence Failure in Hard Macros Problem: How to implement the behavior for hard macros like memories? Solution: Power sequence failing can be highlighted by Assertion in Emulation Models to mimic the power behavior. Example: Issues faced/ Solutions (negedge vddmp) begin FOURTH_ASSERTION: assert (SLEEP === 1'b0) else $display ("FOURTH_ASSERTION failed"); end Assertion failure when vddmp goes low Accellera Systems Initiative 18

19 Hard Macros Interface corruption Problem: Tool didn t support Liberty features (used for hard macro interface corruption) Solution: Liberty file support by the tool. -pg_type, primary_power, -primary_ground -related_power_pin, -related_ground_pin For input pin corruption of hard macro -power_down_function For output pin corruption of hard macro Functionality Issues faced/ Solutions Corrupt ports when related_ground/power supply is in OFF state. Corrupt output ports when specified power_down function is true. Support run-time corruption control schemes ( 0, 1, invert) Accellera Systems Initiative 19

20 Memory Array Corruption Issues faced/ Solutions Problem: How to corrupt an array which lies into multi voltage domain? Solution: Whole Memory Array can be Corrupted with predefined corrupt values through Verilog readmemh construct under assertion. Wire vddma; if(sleep!== 1'b1 && (vddma!== 1'b1 ) ) begin end Simulation Model for (i=0; i<words; i++) Mem[i] = Wordx; Emulation Model reg vddma; property CK)!SLEEP -> vddma ; endproperty ARRAY_ASSERTION: assert property (sleep_vddma) else begin $readmemh("error_file",mem); $display( Array corruption "); end Accellera Systems Initiative 20

21 Introduction Power Verification - Simulation Power Verification - Emulation Low Power Emulation Example Issues faced/ Solutions Results Accellera Systems Initiative 21

22 Assertion failure on memories Memory array supply OFF in SLEEP mode Results Assertion failure Accellera Systems Initiative 22

X corruption domain switch OFF 1 2 3 4 5 Results 1.

Observe the domain corruption (x) of switch off

23 X corruption domain switch OFF Results 1. Save the count value at one instance. 2. Isolate the domains before switching off the driving domain. 3. Observe the domain corruption (x) of switch off domain. 4. Restore the stored count value. 5. Remove the isolation between domains. Accellera Systems Initiative 23

24 Future Work Assertion Generation: Use Standard EDA tool to generate assertions for enhancing debugging on Low Power Emulation. To handle Static Checking of various anomalies while setting Power Domains and debugging. Add Assertion Support for all the Hard Macros e.g. Memories, EPOD, IOs Follow up with EDA vendor to get support of all missing features which are present on Simulator. Accellera Systems Initiative 24

25 Questions Accellera Systems Initiative 25

Challenges with Power Aware Simulation and Verification Methodologies

Challenges with Power Aware Simulation and Verification Methodologies Divyeshkumar Vora Staff Design Engineer Accellera Systems Initiative 1 Agenda Introduction Power-aware (PA) simulation overview Integrated