ARTEMIS Technology Conference

Transcription

1 ARTEMIS Technology Conference Agenda & Abstracts Organized by:, INDEXYS, CESAR, SYSMODEL project partners Hosted by: AITIA & BME

2 June 29 th 08:45-09:00 Opening of the ARTEMIS Technology Conference 09:00-12:30 Session 1/a - Room IB026 Session 1/b - Room IB027 lectures I INDEXYS lectures 09:00-09:50 09:50-10:40 10:40-11:30 11:30-12:20 SPEAr: a customizable MPSoC solution for multi-processing applications Fabio Mario Scalise Experiences in a power efficient and high performance computation environment Mario Vigliar A Fast Modeling and Simulation Framework for the Design of Power/Thermal Control Strategies in Industrial Embedded Platforms Andrea Acquaviva Power reduction techniques for memory and I/O subsystems in application specific processors Jos Hulzink First Genesys Architectures Implemented in the INDEXYS Project - An Overview on The Technical Project Contents and Status Quo Andreas Eckel Developing Deterministic Networking Technology for Railway Applications Using TTEthernet Software Based End Systems Astrit Ademaj Adoption of The GENESYS Architectural Style in The Railway DomainSoftware Based End Systems Christoph Scherrer Flexray Multirouter 12:20-14:30 Informal lunch, Demonstrations, Poster presentations 14:30-17:50 Session 2/a - Room IB026 Session 2/b - Room IB027 + ARTEMIS Academy lectures INDEXYS + SYSMODEL lectures 14:30-15:20 15:20-16:10 Robust, High-throughput, Extended range Wireless Connectivity, for mobile application Saeid Azmoodeh Networking application design framework for High Speed reconfigurable networking hardware István Moldován Eric Schmidt Error-Propagation Analysis in Design Time V&V of Component Oriented Embedded Systems Gy. Csertán A Robust and Scalable CAN-based Communication Infrastructure based on the GENESYS Architecture Roman Obermaisser 16:10-17:00 17:00-17:50 Lightweight but powerful QoS solution for embedded systems Andreas Foglar Design Space Exploration and Rapid Prototyping of Low-Power Network Processors Christian Liss Semantics-Based Integration of Embedded Systems Models A. Balogh System Level Modeling Environment for Small and Medium Enterprises Sanna Määttä 18:30 - Social event at Buda Castle

3 June 30 th 09:00-12:20 Session 3/a - Room IB026 Session 3/b - Room IB027 lectures III CESAR lectures 09:00-09:50 09:50-10:40 SW simulation and performance analysis Eugenio Villar AMM technology for early performance measurements on system level Tim Kogel CESAR Approach for The Development of Safety Critical Embedded Systems Quentin Bourrouilh, Ingrid Kundner Improved Requirements Engineering for Safety Related Systems Markus Oertel 10:40-11:30 11:30-12:20 Composable, predictable processor tile for an embedded MPSoC Anca Molnos Design of programmable accelerators for multicore SoCs Gert Goossens A Multi-Views Approach for a Component- Based Architecture Design Eric Armengaud The CESAR Reference Technology Platform Tom Ritter 12:20-14:30 Informal lunch, Demonstrations, Poster presentations 14:30-16:10 Session 4/a - Room IB026 Session 4/b - Room IB027 lectures IV lectures IV 14:30-15:20 The SCMP architecture Nicolas Ventroux Adaptive Runtime Resource Management for Devices with Heterogeneous Processing Elements Zhe Ma Geert Nuyttens 15:20-16:10 Early evaluation and reliability assessment of Multiprocessor Systems on Chip platforms and applications: issues and novel approaches Francesco Bruschi Power saving in LCD panels Hans van Mourik 16:10-16:30 Summary session

4 Lecture Abstracts SW Simulation and Performance Analysis (Eugenio Villar, University of Cantabria, Spain) Current electronic systems are based on multi-processor, systems on chip, the last frontier of very-large scale integration technology. In these systems, most of the functionality is implemented as embedded SW running on the multiprocessing platform in close interaction with the rest of the platform resources (communication infrastructure, peripherals, application-specific HW, etc.). In this context, there is a need to develop virtual prototypes able to allow the designer to verify the correctness of the design and to analyze its performance (timing, power consumption, etc.) at the different design steps. Traditional techniques like functional modeling and simulation are fast but can hardly provide accurate performance metrics. On the other hand, ISS simulation is very accurate but too slow. Native simulation and virtualization are the new SW simulation techniques able to provide fast and accurate enough solutions. In this lecture an overview of current SW simulation and performance analysis techniques is provided. Improvements to the state of the art as a result of the Scalopes project are presented. Power Saving in LCD Panels (Hans Van Mourik, Philips Consumer Lifestyle, The Netherlands) In modern flat TV sets the major part of the power is consumed by the Liquid Crystal Display. Obviously, to save power we have to start here. There are several ways to make the LCD more efficient. Within the framework of the Scalopes project we looked at the backlight and the colour filter. For the backlight we can select fluorescent lamps or LEDs as light source and when using LEDs there are several architectures possible. Also the algorithms to control the backlight will be discussed. Then most of the light that is generated in the backlight is absorbed in the colour filter. By using "Multi Primary", using more than the traditional red, green and blue components, the colour filter can be made more efficient. Early Evaluation and Reliability Assessment of Multiprocessor System-on-Chip Platforms and Applications: Issues and Novel Approaches (Francesco Bruschi, Poliecnico di Milano, Italy) Being able to evalute functional (correctness, dependability) and non functional (performance, power consumption) features of embedded applications very early in the design cycle has always been one of the main aims of Electronic Design Automation efforts. Within the framework of this classical problem, some issues emerged recently, alongside with the diffusion of certain design and implementation technologies. Among these are the increasing number of processor cores available on a chip, the nearly ubiquitous presence of operating systems even in embedded devices and the adoption of reconfigurable hardware components. In this talk, the main challenges that a modern system level MPSoC simulator must address will be introduced and analysed. After that, some novel approaches to answer to the questions raised will be introduced, among which are operating system emulation and reflexivity in system modeling. Application of such techniques to the aims will then be described and exemplified. Adaptive, Runtime Resource Management for Devices with Heterogeneous Processing Elements (Zhe Ma, IMEC, Belgium and Geert Nuyttens, Barco, Belgium) Embedded software developers increasingly need to take advantage of heterogeneous processors, like GPUs and DSPs, to achieve required performance with a reasonable development cost. Conventional solutions rely on design-time profiling and exploration to determine the assignment of software tasks on processing elements. However, runtime dynamism encountered in practice can breach the design-time assumptions and hence result in suboptimal usage of the hardware resources. Moreover, when commodity processors are added into the underlying hardware platform of an embedded system, it is difficult to determine a cost-effective mapping of software tasks on multiple heterogeneous processors. To tackle the challenge of fast and cost-effective task mapping on a heterogeneous platform, we propose an intelligent resource management layer between the software applications and the hardware platforms. This resource manager automatically assigns software tasks to heterogeneous processors in order to maximize the overall performance at runtime. We have developed a specific adaptive runtime resource manager for a workstation consisting of CPU and GPU. In this paper we demonstrate its effectiveness through a case study of a real-life AVC encoder on the workstation. we will show that (1) an optimal task assignment depends on the runtime scenarios and hence is hard to define statically for a complex system; (2) by integrating this runtime resource manager with the encoder, we always provide task assignments close to the optimal ones.

5 The SCMP Architecture (Nicolas Ventroux, CEA-LIST, France) The emergence of new embedded applications for telecom, communication infrastructure, digital television or multimedia applications, has fueled the demand for architectures with higher performances, more chip area and power efficiency. These applications are usually computation-intensive, which prevents them from being executed by general-purpose processors. Another very important feature of future embedded computation-intensive applications is the dynamism. Algorithms become highly data-dependent and their execution time depends on their input data, since decision processes and the whole application are now implemented and must be accelerated. For these reasons, a new multiprocessor architecture, named SCMP, is proposed. This lecture will present this multiprocessor platform and will focus on the work that has been done in the project. We will mainly discuss about our specific resource manager, which supports the scheduling of tasks and the energy consumption management through DVFS and DPM techniques, about its programming model and automatic parallelization tools, as well as the SESAM simulation framework, which is a complete simulation tool for MPSoC exploration. Design Space Exploration and Rapid Prototyping of Low-Power Network Processors (Christian Liss, Heinz Nixdorf Institute, Germany) ARTEMIS Academy Chip development is a complex process that is getting more and more challenging. Starting with a high-level specification various decisions have to be made to achieve a working chip design. Some of the most important decisions in respect to the system's architecture, the production process etc. can be improved by design space exploration, i.e., the process of finding optimal designs in respect to resources like energy consumption, die area, and application-specific performance metrics. This lecture presents two important parts of the chip development process, which are design space exploration approaches and rapid prototyping. Rapid prototyping is the art of quickly building working prototypes that can be tested in a real environment to check the correct behavior of the design before producing it as a chip, to reduce risk, and to optimize the design. Networking Application Design Framework for High-Speed Reconfigurable Networking Hardware (István Moldován, BME, Hungary) There is more and more applications for the reconfigurable networking hardware, they are widely used from prototyping to commercial applications. The development of new applications however is challenging, and requires both networking and hardware related expertise. In this lecture we present a framework for easy networking application development. The framework builds around a generic high-speed packet forwarding architecture, which is modular and easily extensible. The toolchain uses a simulation and hardware model library providing the basic networking functions, and also provides a methodology for creating custom applications in an easy way. Basic applications can be built using the models provided, and more complex applications with new hardware modules and harware accelerators can be created and optimized in a iterative manner. Robust, High-Throughput, Extended-Range Wireless Connectivity for Mobile Applications (Saeid Azmoodeh, ST-Ericsson, UK) One of the key functionalities of the next generation portable multimedia, surveillance systems and many other applications such as Portable Multimedia Players, Digital Photography, Gaming,..etc is Wireless Connectivity. In fact, Wireless Connectivity is becoming a basic requirement for many of the applications we will rely on in our daily lives. To meet the challenges of such applications, with respect to high throughput, extended range, maximum level of integration and long autonomy, a solution beyond the state-of-the art is required. The objective is to develop a highly advanced platform, compliant with appropriate standards, but still flexible enough to allow a high degree of re-usability in different mobile or battery operated scenarios. The core of this development is a System-On-Chip Wi-Fi device, complying with IEEE a/b/g/n standard provided, and more complex applications with new hardware modules and harware accelerators can be created and optimized in a iterative manner.

6 Composable, Predictable Processor Tile for an Embedded MPSoC (Anca Molnos, TU Delft, The Netherlands) Composability - a property identified as crucial in the consortium - ensures that the behaviour of an application, including its timing, is not affected by the absence or presence of other applications. In this work we consider an Multi-Processor Systems on Chip (MPSoC) consisting of several processor tiles, an interconnect, and several memory tiles. Such an MPSoC executes multiple applications concurrently, each of which potentially having different timing constraints (i.e. real-time or non real-time). The tasks of each application may be mapped on several processors, store their data in distributed memories, and communicate via the interconnect. Composability cannot be achieved without proper arbitration of each shared resource (i.e. processor, interconnect, memory). We use a composable interconnect, and composable memory tiles, and we present a processor tile architecture, an inter-tile communication mechanism, and an operating system able to ensure composability for all applications and to preserve predictability for the real-time ones. The proposed mechanisms are prototyped on a MPSoC in FPGA and experiments indicate that composability is achieved. Experiences in a Power-Efficient and High-Performance Computation Environment (Mario Vigliar, DPControl, Italy) Power constrained and "green" computing are often considered to be self-restricted to a low performance domain of applications by default. MPSoC architectures, richer and richer of complex peripherals and IPs, and smarter resource management policies are by the way lowering the energy demand of modern designs by acting on common cause of energy wastes and thermal implications. Nevertheless high density computing meshes offer to algorithms' designers new chances to reduce class of complexity of their target problems by adopting SIMD schemes. The lecture will focus on how to use best-in-class optimization techniques to face off hard numerical problems in an embedded device, with low power consumption. As use case the proceedings on DPC H.264 video compressor (based on non-trivial motion estimation) will be shown, w.r.t. to the constrained power model of the experience. As compendium some notes on realtime OS support (Linux in realtime) on ARM will be provided. A Fast Modeling and Simulation Framework for the Design of Power/Thermal Control Strategies in Industrial Embedded Platforms (Andrea Acquaviva, Politecnico di Torino, Italy) Next generation industrial embedded platforms require the development of complex power and thermal management solutions. Indeed, from one side an increasingly fine and intrusive thermal control is required because of temperature impact on circuit reliability. On the other side, thermal management policies must be as much as possible transparent from a performance and power viewpoint. To be effective, the implementation of these policies involves decisions that must be taken during various phases along the design process, to enable the development of architectural level countermeasures and the required hardware knobs, such as power modes, power supply regulation granularity and the number of on-chip temperature sensors. As a consequence, a framework allowing rapid power and thermal policy exploration during the design process is desirable. In presentation we propose a solution on this direction, by showing a fast modeling and simulation environment for the evaluation of power and temperature management policies. It exploits power information available at a post-synthesis phase of the design process. Power information is used to drive a thermal simulation engine capable of temperature feedback for the emulation of on-chip sensors. Design of Programmable Accelerators for Multicore SoCs (Geert Goossens, Target Compiler Technologies, Belgium) For new wireless standards like 3GPP-LTE, general-purpose processors are getting out of steam. Wisdom is that accelerators must be added in the form of hardwired datapaths, to deliver the required performance. However, a hardwired datapath stands for zero flexibility, reducing the capability of supporting evolutionary or multiple standards. In this lecture we discuss how C-programmable applicationspecific processors (ASIPs) can replace fixed-function accelerators without sacrificing performance (i.e. throughput, power and gate count). Multiple ASIPs can be combined in a heterogeneous multicore SoC. We review different approaches for ASIP design. We introduce IP Designer, a retargetable tool-suite for ASIP design developed by Target Compiler Technologies. We illustrate our performance claims with examples from the data-plane of wireless communication systems, such as channel encoding for WLAN and fast FFT calculation.

7 SPEAr: a Customizable MPSoC Solution for Muliprocessing Applications (Fabio Mario Scalise, STMicroelectronics, Italy) SPEAr is an MPSoC (Multi-Processors System-on-Chip) single-silicon solution that can be used to efficently implement various complex systems spanning from industrial to communication and consumer fields, where intensive computing abilities, flexible power consumption and agile reconfigurability are key success factors. SPEAr family of devices is based on dual ARM9 or Cortex A9 processors, a smart interconnect on-chip network and a comprehensive set of connectivity solutions (including GigaEthernet, USB and others) combined with other powerful blocks, like HD LCD controller, crypto accelerator and others more. On top of that, SPEAr devices comprise a very large part of generic logic, that can be customized according to customer's indications, to support either customer-developed IP blocks or additional customer-related blocks (e.g. a specific connectivity block) to fit into the end application requirements. The lecture will describe in details the technical features and architecture of the SPEAr platform, including the SW suite (Linux based). Information about the market relevance and key pros of SPEAr will be give as well. Power Reduction Techniques for Memory and I/O Subsystems in Application-Specific Processors (Jos Hulzink, Holst Centre / IMEC, The Netherlands) For many applications, especially in the area of sensor nodes and sensor networks, the computational power requirements in an ASIP are limited. Therefore, power in such system is usually not dominated by the processor, but by the memories, I/O subsystems, running clocks and with modern design technologies even leakage. In this lecture we present a variety of techniques used to reduce the power consumption of these components and the ASIP as a whole. The used technologies for this purpose include, but are not limited to, strict clock gating, clock speed reduction, on-chip clock generation, power gating, voltage reduction and memory retention modes. Apart from the hardware design aspects, also the impact on the applications will be discussed. AMM Technology for Early Performance Measurements on System Level (Tim Kogel, Synopsys and NXP-NL) In the early design phase of multi-processor embedded systems, most of the decisions taken are based on static performance analysis techniques, such as bandwidth calculations in spreadsheets. A limitation of static approaches is in the analysis of dynamic aspects, e.g. scheduling, arbitration and synchronization. The goal of the Application Modeling and Mapping (AMM) project is to complement existing static performance analysis techniques with dynamic performance analysis techniques based on simulations. The simulation models are based on virtual prototyping techniques supported by commercial ESL tooling from CoWare. The models focus on traffic generation and include control mechanisms to make dynamic aspects like mode switching and synchronization effects explicit. The (software) application models are separated from the hardware platform models, to ease exploration of use-cases. In this session the AMM technology will be explained. Lightweight but Powerfull QoS Solution for Embedded Systems (Andreas Foglar, LANTIQ, Germany) ARTEMIS Academy While ATM technology provided very sophisticated QoS methods Internet still offers best effort quality. A compromise is needed for low power embedded systems, on the one hand sufficiently elaborated to offer guaranteed QoS and bounded delay for real-time sensor applications, on the other hand simple enough to be implementable with limited resources. A lightweight solution has been elaborated, with 4 QoS classes differentiated by the delay, a parameter which is sensitive for the human being. Starting with queuing theory the solution is derived down to a practical solution, ready for implementation. It includes simple formulas for bandwidth control, link load and and end-to-end delay prediction The solution allows segregation of the network in two independent planes, best effort plane with connectionless net-neutrality as requested by public authorities as well as value-added services with guaranteed QoS.

8 System Level Modeling Environment for Small and Medium Enterprises (Sanna Määttä, Tampere University of Technology) Sysmodel Small and Medium Enterprises (SME) participating the SYSMODEL project work on different application areas or as subcontractors. Therefore, they have different targets, such as analog and digital hardware, software, and RFID technology. SMEs have no or very little experience on system level modelling tools, languages, methods, or design space exploration. Their methods are mainly ad hoc approaches that cannot completely handle the complexity and heterogeneity of today's embedded systems. The aim of the SYSMODEL project is to provide the SMEs with system level modelling tools for the design and implementation of time and power critical heterogeneous systems. Proper system level modelling tools may increase the SMEs' design productivity even by 30%. Within the SYSMODEL project, open source system and platform modelling frameworks will be created as well as point tools for design verification and design space exploration. First GENESYS Architectures Implemented in The INDEXYS Project An Overview on The Technical Project Contents and Status Quo (Andreas Eckel, TTTech Computertechnik AG) The objective of INDEXYS (INDustrial EXploitation of the genesys cross-domain architecture; funded by the Artemis Joint Undertaking) is to tangibly realize industrial implementations of cross-domain architectural concepts developed in GENESYS (GENeric Embedded SYStem Platform; funded by the seventh framework-programme of the European commission). INDEXYS aims at three domains: automotive, aerospace and railway and relates to ARTEMIS-JU Industrial Priority: Reference designs and architectures. The automotive, aerospace and railway industries require safety-critical systems. Consequently, INDEXYS targets dependability services at the architectural level by architectural service instantiations in order to guarantee reliable and timely system services despite accidental failure of system components. Core concepts behind these dependability services are the availability of a synchronized global time, message-based sub-system interaction across a state-message based interface (i.e., temporal firewall), error containment on node level and on network level by strict definition of error containment regions, as well as diversity concepts in order to increase robustness at an architectural level. The presentation will introduce recent developments of INDEXYS architectural style verifications which have been carried out in the three industrial domains (automotive, aerospace and railway). Those developments are examples to demonstrate the cross-domain applicability of the GENESYS architectural style and its related services. Developing Deterministic Networking Technology for Railway Applications Using TTEthernet Software- Based End Systems (Astrit Ademaj, TTTech Computertechnik AG) Safety-critical applications in the railway domain require deterministic communication networks where robustness and composability are key issues. TTEthernet is a deterministic, composable and scalable real-time communication network fully compatible with IEEE Standard Ethernet traffic sent over the same network does not affect determinism and synchronization of TTEthernet real-time traffic. TTEthernet takes advantage of design experiences with time-triggered systems in the transportation industry and provides a unique approach to real-time Ethernet networking. The software-based TTEthernet implementation uses COTS Ethernet controllers showcasing that TTEthernet can be implemented on any Ethernet compliant hardware, thus providing a cost-efficient and flexible technology implementation. Software based TTEthernet will be ported in the HW target used in the railway industry and it will be used for investigation of robustness services in the course of the INDEXUS project by using a railway application. Adoption of The GENESYS Architectural Style in The Railway Domain (Christoph Scherrer, Thales) In today s computer-based railway control one major challenge is to reconcile the inhomogeneous field of different systems into a composable and dependable platform. Such systems range from electronic interlocking systems, axle counters, signal controllers to automatic onboard train control systems, all equipped with different COTS based hardware components. These applications share similar requirements with respect to dependability and safety certification procedures, but depend on different assumptions concerning performance, operating environmental conditions and cost.given this background the challenges for future architectures for embedded systems in the railway domain are being discussed in the context of the GENESYS architecture.

9 FlexRay Multirouter (Eric Schmidt, TTTech Computertechnik AG) The introduction of the FlexRay communications system into today's cars has enabled new possibilities for integrating novel distributed functions requiring high communication bandwidth and fulfilling tight timing constraints. By loading a single channel FlexRay bus with multiple messages needed for a variety of functions, it now becomes obvious that enhancements of the FlexRay communications system are needed for future expansions without losing the compatibility with todays FlexRay standard 2.1A. The FlexRay Multirouter is designed to operate as a drop-in replacement for an active star device with a set of additional new features that significantly enhance the performance of the FlexRay communications system with respect to bandwith utilization and also fault containment. By intelligently subdividing the FlexRay cluster into synchronously operating sub-domains, additional bandwith can be utilized on the same physical layer. Safety-relevant messages can be protected from potential faults which would cause the according safety-relevant functions to fail. The FlexRay Multirouter operates as an intelligent cut-through (zero-dalay) switching device which allows both, selective and parallel routing on a slot-by-slot basis. This central device is configurable to the specific needs of the designed FlexRay network. The issue of configuration of the FlexRay Multirouter as such is a rather complex task that requires careful and suitable tooling and design support. Resulting from both, the FlexRay Multirouter device capabilities and the configuration tools, enhanced bandwith utilization and fault containment is supported, additionally fulfilling the goals of extensibility and flexibility thereby preserving the compatibility to the available COTS components of the FlexRay standard 2.1A. A Robust and Scalable CAN-based Communication Infrastructure based on the GENESYS Architecture (Roman Obermaisser, TU Vienna) Controller Area Network (CAN) provides an inexpensive and robust network technology in many application domains. However, the use of CAN is constrained by limitations with respect to fault isolation, bandwidth, wire length, namespaces and diagnosis. For example, a faulty CAN node can disrupt the communication abilities of all other nodes by continuously transmitting high-priority messages. Hence, a single CAN bus does not support the construction of embedded systems where the correct operation of the communication services is required to ensure safety. This presentation introduces a CAN-based communication infrastructure to overcome these limitations based on the embedded system architecture implemented within the INDEXYS (INDustrial EXploitation of the genesys cross-domain architecture)project. The CAN-based communication infrastructure supports rigid fault containment and tackles scalability by improving the use of the bandwidth, extending the possible overall wire length and supporting multiple namespaces. Semantics-Based Integration of Embedded Systems Models (A. Balogh, OptXware Ltd) Model-driven development has become an important trend in embedded systems design. Several standardized domain-specific languages have been defined in various application domains mainly covering the functional aspects of development. The ARTEMIS platform targets the interaction between these domains by defining a common architectural and modeling style (like GENESYS) for the systems. Although, GENESYS has been successful in the uniformization of system design approaches and styles, from the modeling point of view, it focused only on the syntactical specification of components and interfaces and did not define a common semantical base for modeling approaches. In INDEXYS we define an ontology-based modeling approach that is able to capture the semantical aspects of different modeling concepts, like non-functional properties, hardware component types, and so on. This will result in an ontology of these concepts that can be used as a common nomenclature and classification of terms and will support the semantics preserving transformation between different modeling languages and will help the integration of embedded system development tools with different metamodeling background into a coherent development tool-chain. Error-Propagation Analysis in Design Time V&V of Component Oriented Embedded Systems (Gy. Csertán, OptXware Ltd) In the field of embedded system design, modern development tool-chains are based on the model driven design (MDD) technology. The key problem to solve here is the seamless integration of different development tools around an efficient central model repository. This solution gives place for design time verification and validation in early phases of the design of safety critical systems and as such can help to significantly reduce design costs. Error-propagation analysis is combined into our customizable workbench in order to automatically discover the undesired combinations of faulty input and an erroneous internal component state, which may result in the delivery of incorrect computation results.

10 CESAR Approach for The Development of Safety Critical Embedded Systems (Quentin Bourrouilh, Ingrid Kundner, AVL List GmbH) CESAR The embedded safety-critical systems design and development industry is facing increasing complexity and variety of systems and devices, coupled with increasing regulatory constraints while costs, performances and time to market are constantly challenged. To take this challenge and find some answers the CESAR-Project was launched in "CESAR" stands for Cost-efficient methods and processes for safety relevant embedded systems and is the biggest ARTEMIS project of the 1st Call. CESAR will try to reduce the costs of the development of safety critical systems by bringing significant and conclusive innovations in the System Design Engineering disciplines. A combination of the improved Requirements Engineering discipline and the improved Component Based Development discipline is a precondition to satisfy the ambitious CESAR goals. Only an integration of these disciplines accompanied with an adequate tool support into a seamless tool chain (CESAR RTP) can unleash the full potential of the CESAR approach. The presentation starts with a quick overview of the CESAR-Project were the motivation, the objectives, the approach and structure will be illustrated. The focus of this speech is concentrated on the first intermediate management results which depict the way how we want to measure the success of the CESAR project. The evidence of the success is highly recommended by the independent reviewers as well as the JU ARTEMIS project officer. Improved Requirements Engineering for Safety Related Systems (Markus Oertel, OFFIS) CESAR The embedded safety-critical systems design and development industry is facing increasing complexity and variety of systems and devices, coupled with increasing regulatory constraints while costs, performances and time to market are constantly challenged. From a safety point of view requirements engineering in particular with respect to traceability issues and analysis techniques to deal with consistency, completeness as well as correctness is an important discipline. CESAR will provide a formalized multi criteria requirement specification language together with analysis methods, for example supporting validation of formal multi-criteria requirements w.r.t. consistency and completeness. The presentation will provide some intermediate results of the CESAR project dealing with this subject. A Multi-Views Approach for a Component-Based Architecture Design (Eric Armengaud, Virtual Vehicle) CESAR When developing a system, a set of skills are required (mechanics, electronics, hydraulics, safety,...) and a set of criteria (safety, cost, performance,...) has to be met in order to fulfil the system requirements. So, in this talk the different facets of the system design to handle will be described as different system views that must be consistent. The foundations for ensuring these views consistency will be discussed. In addition to this viewpoint concept, the component based modelling approach chosen for the CESAR project will be presented. A specific focus will be made on the contract and connectors techniques that allow reusability and cost reduction. The CESAR Reference Technology Platform (Tom Ritter, Fraunhofer FOKUS) CESAR Developing embedded safety-critical systems is a challenging mission. Usually, there are multiple tasks to accomplish comprising activities like requirements management, system architecture design, component design, coding, simulation and tests. Each of these activities is complex in its own and is often supported by highly specialized software tools. But using these specialized tools together in a coordinated way within a development team, which is probably spread across multiple locations, is far from being simple. There is a lack of interoperability among these tools and only some vendor-specific solutions and point-to-point integrations can be used. In particular it is difficult to share data between these tools and to establish an end-to-end traceability from requirements to test results without substantial manual work. The CESAR project addresses these issues and creates the CESAR Reference Technology Platform - RTP. The CESAR RTP is a means helping to establish seamlessly integrated tool chains. This talk presents the general concepts of the CESAR RTP including the RTP ModelBus and exemplary scenarios based on the first results of the CESAR project.

11 About the Projects The goal of is to enable an industrially sustainable path for the evolution of low power multi-core computing platforms for application domains with strategic value for European competitiveness. The technical innovations are driven by and proven for 4 different application domains: /communication infrastructure, surveillance systems, smart mobile// terminals and stationary video systems/. More information about can be found at: INDEXYS The objective of INDEXYS (INDustrial EXploitation of the genesys cross-domain architecture) is to tangibly realize industrial implementations of cross-domain architectural concepts developed in the GENESYS project in three domains: automotive, aerospace and railway, thereby relating to ARTEMIS-JU Industrial Priority: Reference designs and architectures. More information about INDEXYS can be found at: CESAR CESAR intends to reduce the costs for the development of embedded systems while ensuring the quality and safety properties. To achieve this goal, CESAR will bring significant innovations in the two most improvable systems engineering disciplines: Requirements engineering in particular through formalization of multi viewpoint, multi criteria and multi level requirements Component based engineering applied to design space exploration comprising multi-view, multi-criteria and multi level architecture trade-offs Only an integration of these disciplines accompanied with an adequate tool support into a seamless tool chain can unleash the full potential of the CESAR approach. Therefore, CESAR is developing the RTP Reference Technology Platform. More information about CESAR can be found at: SYSMODEL The SYSMODEL project aims at providing SMEs with system level modelling tools for the design and implementation of time and power critical, heterogeneous systems. The vision is to allow SMEs to build cost-efficient ambient intelligence systems with optimal performance, high confidence, reduced time to market and faster deployment. The focus is on the development of modelling concepts, methods and tools that master system s complexity by allowing cost-efficient mapping of applications and product variants onto an embedded platform; while respecting constraints in terms of resources (time, energy, memory, etc.), safety, security and quality of service. More information about SYSMODEL can be found at: