Software Driven Verification at SoC Level. Perspec System Verifier Overview
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1 Software Driven Verification at SoC Level Perspec System Verifier Overview June 2015
2 IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC Sub-System IP Spec Silicon
3 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC Sub-System IP Spec Silicon
4 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC Sub-System Subsystem UVM e/sv Metric-Driven Verification IP IP UVM e/sv Metric-Driven Verification Spec Silicon
5 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis Sub-System Subsystem UVM e/sv Metric-Driven Verification IP IP UVM e/sv Metric-Driven Verification Spec Silicon
6 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Bare-Metal SW SoC Gate-Level Verification SoC Hardware/SW Use Case Verification SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis Sub-System Subsystem UVM e/sv Metric-Driven Verification IP IP UVM e/sv Metric-Driven Verification Spec Silicon
7 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) SoC Hardware/Software Integration Verification and Architecture Analysis Bare-Metal SW Gate-Level Verification SoC Hardware/SW Use Case Verification SoC SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis Sub-System Subsystem UVM e/sv Metric-Driven Verification IP Spec IP UVM e/sv Metric-Driven Verification Silicon
8 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Gate-Level Verification Software- SoC Hardware/SW Use Case VerificationDriven Verification SoC IP Integration Verification Sub-System IP Spec SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis UVM e/sv Coverage- Subsystem UVM e/sv Metric-Driven Verification Driven Verification IP UVM e/sv Metric-Driven Verification Silicon
9 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Gate-Level Verification Software- SoC Hardware/SW Use Case VerificationDriven Verification SoC IP Integration Verification Sub-System IP Spec SoC Interconnect UVM e/sv Metric-Driven Verification & Performance Analysis TLM Design UVM e/sv and Verification Coverage- Subsystem UVM e/sv Metric-Driven Verification Driven Verification IP UVM e/sv Metric-Driven Verification Silicon
10 Metric-Driven Verification Planning and Management IP to SoC hardware/software integration and verification flows Cadence methodology and focus Applications (Basic to Angry Birds) Middleware (Graphics, Audio) OS and Drivers (Linux, Android) Hybrid Hardware/Software SoC Hardware/Software Integration Verification and Architecture Analysis Integration Bare-Metal SW SoC Sub-System IP Spec Gate-Level Verification Formal-Assisted Software- SoC Hardware/SW Debug Use Case VerificationDriven Formal Coverage Closure Verification Applications SoC IP Integration Connectivity Verification SoC Interconnect UVM e/sv Metric-Driven Security Path Verification & Performance Analysis TLM Design Register Verification UVM e/sv and Verification Coverage- Subsystem Power-Aware UVM e/sv Verification Metric-Driven Verification Driven Functional Verification Verification IP UVM e/sv Metric-Driven Verification Design Bring-Up Sequential Equiv. Silicon
11 IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Spec Silicon
12 IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Simulation and Formal Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Spec Silicon
13 IP to SoC pre-silicon verification platforms SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon
14 IP to SoC pre-silicon verification platforms Hardware Emulation or FPGA Prototype SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon
15 IP to SoC pre-silicon verification platforms Virtual Platform and Hybrid Hardware Emulation or FPGA Prototype SoC Hardware/Software Integration Verification and Architecture Analysis Gate-Level Verification SoC Hardware/Software Use-Case Verification Hardware Acceleration and Emulation Simulation and Formal Spec SoC IP Integration Verification SoC Interconnect UVM e/sv Metric-Driven Verification and Performance Analysis Subsystem UVM e/sv Metric-Driven Verification IP UVM e/sv Metric-Driven Verification Silicon
16 P H Y P H Y A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem ARM V8 CPUSubsystem Application Specific Components Cortex Cortex -A53 -A53 L2 cache Cortex Cortex -A57 A57 L2 cache 3D GFX DSP A/V Boot processor ARM M0 Modem Cache coherent fabric SoC interconnect fabric DDR 3 USB3.0 PCIe Gen 2,3 Eth er net HDMI SATA GPIO Display UART INTC MIPI PMU I2C PHY PHY PHY WLAN LTE MIPI SPI JTAG Low-speed peripheral Timer subsystem High speed, wired interface peripherals Other peripherals Low speed peripherals SoC
17 P H Y P H Y A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem Many cores Both symmetric and asymmetric Both homogeneous and heterogeneous ARM V8 CPUSubsystem Cortex Cortex Cortex Cortex -A53 -A53 -A57 A57 L2 cache L2 cache Cache coherent fabric DDR 3 USB3.0 PCIe Gen 2,3 Application Specific Components Boot 3D DSP processor GFX A/V ARM M0 SoC interconnect fabric HDMI Eth er SATA net GPIO Display Modem UART INTC MIPI PMU I2C PHY PHY PHY WLAN LTE MIPI SPI JTAG Low-speed peripheral Timer subsystem High speed, wired interface peripherals Other peripherals Low speed peripherals SoC
18 P H Y P H Y Bare metal software DSP software Init Software for boot, power, security A system-centric look at a modern SoC Many IPs Standard I/O Wifi, USB, PCI Express (PCIe ), etc. System infrastructure Interconnect, interrupt control, uart, timers Differentiators custom accelerators, modem Many cores Both symmetric and asymmetric Both homogeneous and heterogeneous Lots of software Part of core functionality Communication stack, DSP software, GPU microcode User application software infrastructure Android, Linux Operating Systems (OS) Application software stack Applications Middleware Drivers Firmware / HAL ARM V8 CPUSubsystem Cortex Cortex Cortex Cortex -A53 -A53 -A57 A57 Compute L2 Sub cachesystem L2 DDR 3 PHY Cache coherent fabric USB3.0 PCIe Gen 2,3 High Speed, Wired Interface PHY Peripherals High speed, wired interface peripherals Application Specific Components Boot Modem 3D DSP processor Application-Specific GFX A/V Components ARM M0 Eth er net PHY Software SoC interconnect fabric HDMI SATA General- MIPI WLAN Peripherals LTE SoC Customer s Purpose Other peripherals Bare-metal software GPIO Display PMU I2C Low-Speed MIPI SPI JTAG Low-speed peripheral subsystem Low speed peripherals UART INTC Peripherals Timer Communications L3 Communications L2 Communications L1 RTOS Drivers Firmware / HAL Mobile communications software stack
19 SoC-level verification and validation requirements
20 SoC-level verification and validation requirements Use-Case Reuse Architect Hardware Developer Software Developer User Verification Engineer Software Test Engineer Post-Silicon Validation Engineer How to communicate/share use cases between users
21 Vertical Reuse SoC-level verification and validation requirements Use-Case Reuse Scope (Integration) Middleware (Graphics, Audio, etc..) OS and Drivers Bare Metal Software SoC (Hardware + Software) Architect Hardware Developer Software Developer User Verification Engineer How to communicate/share use cases between users How to create and reuse use cases from IP to SoC Software Test Engineer Post-Silicon Validation Engineer Sub-System IP
22 Vertical Reuse SoC-level verification and validation requirements Use-Case Reuse Scope (Integration) Middleware (Graphics, Audio, etc..) OS and Drivers Bare Metal Software SoC (Hardware + Software) Sub-System IP Architect Hardware Developer Software Developer User Verification Engineer How to communicate/share use cases between users How to create and reuse use cases from IP to SoC Software Test Engineer Post-Silicon Validation Engineer How to use C code to execute natively on many cores and communicate between cores How to run use cases across platforms and run more constrained random variants on faster platforms Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Platform Horizontal Reuse
23 Vertical Reuse The solution: Perspec System Verifier Use-Case Reuse Scope (Integration) Middleware (Graphics, Audio, etc..) Architect Hardware Developer Software Developer User Verification Engineer Software Test Engineer Post-Silicon Validation Engineer OS and Drivers Bare-Metal Software Abstract Model with Reusable Use Cases Powerful Solvers SoC (Hardware + Software) Software Sub-System IP Perspec System Verifier c test c test c test c test Multi-Core Verification OS Firmware/HAL Scheduling, inter-processor communication, runtime randomization Many cores Multi-Cluster Apps Processors 3D GFX DSP A/V Boot Proc Comm Procs Virtual Platform Simulation Emulation FPGA Prototype Silicon Board Platform Horizontal Reuse
24 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone
25 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec solver checks the feasibility of the goals statically
26 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
27 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
28 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display Correct-by-construction generation for multiple targets SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
29 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display Re-generate the code for derivatives, spec changes, etc SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
30 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Coverage model is autocreated and pruned for reachable scenarios Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
31 Automated use case verification SLN Models Desired Scenario: Decode video from the DDR and show on the display SoC SRAM CPU CPU CPU CPU DDR Controller DMA MODEM C test C test C test Abstract Tests C test C test C test Target C test Interconnect USB controller GPX Audio Camera controller Display controller TB USB VIP Speaker Microphone Perspec System Verifier automatically and exhaustively completes the goals in to full legal scenarios
32 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words)
33 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver: Constrained random data and control flow UML Activity Diagram
34 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver randomly selects legal video source and video stream source Solver: Constrained random data and control flow UML Activity Diagram
35 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver randomly selects legal attributes of video stream and memory buffer Solver: Constrained random data and control flow UML Activity Diagram
36 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver schedules show and transmit in parallel as required by use case and adds decode to display Solver: Constrained random data and control flow UML Activity Diagram
37 Example use case Translating end-user use case to system-level bare-metal actions End-user use case: Mobile phone requirement: view a video while uploading it (6 words) Solver: Constrained random data and control flow UML Activity Diagram System-level bare-metal actions: Capture a video with camera using graphics processor and save it to a memory buffer in DDR0 in AVI format with medium resolution and MPEG3 audio with 4x3 aspect ratio then transmit the video using the modem and processor 3 while processor 2 shows the video on the built in display being streamed by the graphics processor of the video already saved in DDR0 memory buffer (66 words)
38 June 2015 Flow
39 Use-case verification flow with Perspec engine._ _...._. SLN Model Resources, actions, C code templates Perspec Library C Test Abstract Debug Environment C Test Use Case Composer Debuggers (C/Design debuggers, etc.) Perspec Engine C Test C Test
40 Step #1: Capture topology and system SLN Model Resources, actions, C code templates Perspec Library actions Use Case Composer Perspec Engine
41 Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Composer Perspec Engine
42 Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Desired Composer Scenario: Decode video from the DDR and show on the display Perspec Engine Abstract Use Case
43 Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Desired Composer Scenario: Decode video from the DDR and show on the display Perspec Engine Abstract Use Case Concrete Use Case
44 Step #2: Capture abstract use case >> solve for concrete use case(s) >> analyze gentime coverage SLN Model Resources, actions, C code templates Perspec Library Use Case Desired Composer Scenario: Decode video from the DDR and show on the display Perspec Engine Abstract Use Case Concrete Use Case Gentime coverage of use case
45 Step #3: Generate tests for specific platform(s) SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test
46 Step #3: Generate tests for specific platform(s) SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code
47 Step #3: Generate tests for specific platform(s) SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code
48 Step #4: Run tests and debug SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code
49 Step #4: Run tests and debug SLN Model Resources, actions, C code templates Perspec Library C Test C Test Use Case Composer C Test Perspec Engine Concrete Use Case C Test C Test Generated C Code Debug from UML activity diagram synchronized with source, waveform and log messages
50 Perspec Modeling Accellera Systems Initiative 15
51 Modeling elements Component: Functional unit groups actions and resources Action: Abstract operation of function Token: Include information for preconditions and outcomes Place: Defines interaction of tokens and actions (memory, channel, lock) Extend: Extending functionality of actions, components, and tokens
52 Modeling with Perspec System Verifier System language notation (SLN)
53 Constraints
54 C-code generation
55 Code generation
56 Public Success Stories Accellera Systems Initiative 21
57 ST TRD: Verify GPU modified for SoC power management
58 ST TRD: Verify GPU modified for SoC power management
59 ST TRD: Verify GPU modified for SoC power management
60 ST TRD: Verify GPU modified for SoC power management
61 ST TRD: Verify GPU modified for SoC power management
62 ST TRD: Verify GPU modified for SoC power management
63 ST TRD: Verify GPU modified for SoC power management
64 Texas Instruments: SoC verification flow
65 Texas Instruments: SoC verification flow
66 Texas Instruments: SoC verification flow
67 Texas Instruments: SoC verification flow
68 Texas Instruments: SoC verification flow
69 Texas Instruments: SoC verification flow
70 ST CPD: Complex SoC scenarios
71 ST CPD: Complex SoC scenarios
72 ST CPD: Complex SoC scenarios
73 ST CPD: Complex SoC scenarios
74 ST CPD: Complex SoC scenarios
75 ST CPD: Complex SoC scenarios
76 ST CPD: Complex SoC scenarios
77 PSWG Breaking News On September 8, Cadence, Mentor, and Breker issued a joint press release Three companies providing joint contribution to PSWG Contributing proven technology and leveraging expertise Why this combined effort? Avoids a long effort to evaluate multiple contributions Accelerates development of an Accellera standard Accelerates adoption of portable stimulus in the industry What s next? Joint contribution to PSWG by September 16 deadline BoF breakfast tomorrow share your thoughts! Accellera Systems Initiative 25
78 June 2015 Demo
79 June 2015 Summary
80 Connecting it together Coherency use case User1
81 Connecting it together Coherency use case User1 User2 Power shutdown use case
82 Connecting it together Coherency use case User1 Coherency User3 User2 Power shutdown Power shutdown use case
83 Connecting it together Coherency use case User1 Coherency Mixed Scenario User3 User2 Power shutdown Power shutdown use case
84 Connecting it together Coherency use case 1. Cache transactions User1 Coherency Mixed Scenario User3 User2 Power shutdown Power shutdown use case
85 Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown Power shutdown use case
86 Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User3 Mixed Scenario 3. Cache transactions User2 Power shutdown Power shutdown use case
87 Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown 3. Cache transactions 4. Power up Power shutdown use case
88 Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down User2 User3 Mixed Scenario Power shutdown 3. Cache transactions 4. Power up Power shutdown use case 5. Cache transactions
89 Connecting it together Coherency use case 1. Cache transactions User1 Coherency 2. Power down C Test C Test Mixed Scenario 3. Cache transactions User2 User3 Power shutdown 4. Power up C Test C Test Power shutdown use case 5. Cache transactions
90 Perspec System Verifier Productivity 10X improvement for complex SoC test creation Abstraction UML-style use-case diagrams Automation System use-case test generation Portability Reuse across all execution platforms Measurement SoC-level hardware/software coverage metrics
91 June 2015 Thank You
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