Cell Broadband Engine Processor: Motivation, Architecture,Programming

Transcription

1 Cell Broadband Engine Processor: Motivation, Architecture,Programming H. Peter Hofstee, Ph. D. Cell Chief Scientist and Chief Architect, Cell Synergistic Processor IBM Systems and Technology Group SCEI/Sony Toshiba IBM Design Center Austin, Texas

2 Acknowledgements Cell Broadband Engine ( Cell ) is the result of a deep partnership between SCEI/Sony, Toshiba, and IBM Cell represents the work of more than 400 people starting in 2001and a design investment of about $400M 2

3 Agenda Motivation Architecture Implementation Programming Applications 3

4 Motivation 4

5 Motivation: Cell Goals Outstanding performance, especially on game/multimedia applications. Challenges: Power Wall, Frequency Wall, Memory Wall Real time responsiveness to the user and the network. Challenges: Real-time in an SMP environment, Security Applicable to a wide range of platforms. Challenge: Maintain programmability while increasing performance Support an introduction in 2005/6. Challenge: Structure innovation such that 5yr. schedule can be met 5

6 Power Wall: Module Heat Flux Trend 14 IBM ES9000 CMOS Prescott 12 Bipolar Jayhawk(dual) Module Heat Flux(watts/cm 2 ) Start of Water Cooling Vacuum IBM 360 Fujitsu VP2000 IBM 3090S CDC Cyber 205 IBM 4381 IBM 3081 Fujitsu M380 IBM 370 IBM NTT Fujitsu M-780 IBM 3090 Year of Announcement IBM RY5 IBM RY6 IBM RY4 IBM RY7 Apache Pulsar T-Rex Mckinley IBM GP Merced Pentium 4 Squadrons Pentium II(DSIP) R. Schmidt, IBM 6

7 CMOS Devices hitting a scaling wall Power components: 1000 Net: Active power Passive power Gate leakage Sub-threshold leakage (sourcedrain leakage) Power Density (W/cm 2 ) Further improvements require structure/materials changes (next slide) Active Power Air Cooling limit 0.1 Gate Length (microns) Passive Power

8 Better Performance Without Scaling New materials & structures are critical for continuing CMOS technology density and performance path, while mitigating power dissipation 8

9 Computing Paradigm Shift Today: Single thread performance hitting limits Architecture and process technology saturated Small percentage gains expected to remain But: Signs of paradigm shift to application specific system customization Large multiple gains for specific applications Cell 50x on TRE, 120x on FFT Datapower XML acceleration Many examples in embedded markets Future: Greater performance demands Immersive Interaction 3D, real-time, gaming inspired applications Rich media, data-intensive content Sensory Computing New network tier Autonomous agents performing intelligent analysis on streaming data >A&D: battlefield coordination Single Thread Performance SPECint Single thread performance growth rate slows dramatically Historical Trend 45% CGR 9

10 Solutions Memory wall: More slower threads Asynchronous loads Efficiency wall: More slower threads Specialized function Power wall: Reduce transistor power operating voltage limit oxide thickness scaling limit channel length Reduce switching per function INCREASE CONCURRENCY INCREASE SPECIALIZATION 10

11 Architecture & Implementation 11

12 Cell Concept Compatibility with 64b Power Architecture Builds on and leverages IBM investment and community Increased efficiency and performance Non Homogenous Coherent Chip Multiprocessor Allows an attack on the Frequency Wall Streaming DMA architecture attacks Memory Wall High design frequency, low operating voltage attacks Power Wall Highly optimized implementation Interface between user and networked world Flexibility and security Multi-OS support, including RTOS/non-RTOS Architectural extensions for real-time management 12

13 Cell Architecture is 64b Power Architecture Power ISA Power ISA MMU/BIU MMU/BIU Memory COHERENT BUS Incl. coherence/memory IO transl. compatible with 32/64b Power Arch. Applications and OS s 13

14 Cell Architecture is 64b Power Architecture Plus Power Power Memory Flow Control (MFC) ISA +RMT ISA +RMT MMU/BIU MMU/BIU +RMT +RMT Memory COHERENT BUS (+RAG) IO transl. MMU/DMA MMU/DMA LS Alias LS Alias +RMT Local Store Memory +RMT Local Store Memory 14

15 Cell Architecture is 64b Power Architecture + MFC Plus Power Power Synergistic Processors ISA +RMT ISA +RMT MMU/BIU MMU/BIU +RMT +RMT Memory COHERENT BUS (+RAG) IO transl. LS Alias LS Alias Syn. Proc. ISA MMU/DMA +RMT Local Store Memory Syn. Proc. ISA MMU/DMA +RMT Local Store Memory 15

16 Coherent Offload Model DMA into and out of Local Store equivalent to Power core loads & stores Governed by Power Architecture page and segment tables for translation and protection Shared memory model Power architecture compatible addressing MMIO capabilities for SPEs Local Store is mapped (alias) allowing LS to LS DMA transfers DMA equivalents of locking loads & stores OS management/virtualization of SPEs Pre-emptive context switch is supported (but not efficient) 16

17 SPE Highlights SFP FXU EVN FWD FXU ODD GPR DMA SBI CONTROL DP CHANNEL SMM LS LS LS LS ATO RTB 14.5mm 2 (90nm SOI) BEB RISC like organization 32 bit fixed instructions Clean design unified Register file User-mode architecture No translation/protection within SPU DMA is full Power Arch protect/x-late VMX-like SIMD dataflow Broad set of operations (8 / 16 / 32 Byte) Graphics SP-Float IEEE DP-Float Unified register file 128 entry x 128 bit 256KB Local Store Combined I & D 17

18 SPE BLOCK DIAGRAM Floating-Point Unit Fixed-Point Unit Permute Unit Load-Store Unit Branch Unit Channel Unit Local Store (256kB) Single Port SRAM Result Forwarding and Staging Register File Instruction Issue Unit / Instruction Line Buffer 128B Read 128B Write On-Chip Coherent Bus DMA Unit 8 Byte/Cycle 16 Byte/Cycle 64 Byte/Cycle 128 Byte/Cycle 18

19 SPE PIPELINE FRONT END IF1 IF2 IF3 IF4 IF5 IB1 IB2 ID1 ID2 ID3 IS1 IS2 SPE PIPELINE BACK END Branch Instruction RF1 RF2 Permute Instruction EX1 EX2 EX3 EX4 Load/Store Instruction EX1 EX2 EX3 EX4 Fixed Point Instruction EX5 EX6 WB WB IF Instruction Fetch IB Instruction Buffer ID Instruction Decode IS Instruction Issue RF Register File Access EX Execution WB Write Back EX1 EX2 WB Floating Point Instruction EX1 EX2 EX3 EX4 EX5 EX6 WB 19

20 Systems and Technology Group 20

21 CELL PROCESSOR STATISTICS 250M transistors 235mm2 Top frequency >4GHz Lab conditions Most efficient at ~1V > 200 GFlops > 20 GFlops Up to 25.6 GB/s memory B/W Up to 70+ GB/s I/O B/W Practical ~ 50GB/s Frequency [GHz] Hardware Performance Measurement (85 C) 4.5 Fmax Supply Voltage 100+ simultaneous bus transactions First pass hardware measurement in the Lab - Nominal Voltage = 1V 16+8 entry DMA queue per SPE 21

22 Programming 22

23 Cell Prototype Software Environment Programmer Experience Code Dev Tools Samples Workloads Demos End-User Experience Development Environment Debug Tools SPE Management Lib Application Libs Execution Environment Development Tools Stack Performance Tools Linux PPC64 with Cell Extensions Verification Hypervisor Miscellaneous Tools Hardware or System Level Simulator Standards: Language extensions ABI 23

24 Operating System Runtime Strategy Heterogeneous Multi-Threading Model PPE Threads, SPE Threads SPE DMA EA = PPE Process EA Space Or SPE Private EA space OS supports Create/Destroy SPE tasks Atomic Update Primitives used for Mutex SPE Context Fully Managed Context Save/Restore for Debug Virtualization Mode (indirect access) Direct Access Mode (realtime) OS assignment of SPE threads to SPEs Programmer directed using affinity mask SPE Compilers use OS runtime services PPE object files Application Source & Libraries SPE object files Cell AwareOS ( Linux) SPE Virtualization / Scheduling Layer (m->n SPE threads) Existing PPE tasks/threads PPE MT1 MT2 Physical PPE New SPE tasks/threads SPE SPE SPE SPE SPE SPE SPE SPE Physical SPEs 24

25 MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N MFC Local Stor e SPU AUC N Systems and Technology Group Programming Models 1) Application Specific Accelerators Acceleration provided by O/S services Application independent of accelerators platform fixed PPE PowerPC Application BE Aware OS (Linux) mpeg_encode() O/S Service System Memory Parameter Area OpenGL Encrypt Decrypt Encoding Decoding Graphics Offload Data Encryption Data Decryption Realtime MPEG Encoding Compression/ Decompression Application Specific Acceleration Model SPC Accelerated Subsystems 25

26 Programming Models 2) Function Offload Power Processor (PPE) System Memory SPE function provided by libraries Predetermined functions Application calls standard Libraries Single source compilation SPE working set fits in Local Store O/S handles SPE allocation SPU Local Store MFC Multi-stage Pipeline N SPU Local Store MFC Power Processor (PPE) System Memory N SPU Local Store MFC N Parallel-stages SPU N Local Store MFC SPU N Local Store MFC 26

27 Programming Models 3) Computational Acceleration User created RPC libraries User acceleration routines User compiles SPE code Local Data Data and Parameters passed in call Global Data Data and Parameters passed in call SPE Code manages global data PPE Puts Text Static Data Parameters PPE Puts Initial Text Static Data Parameters Power Processor (PPE) SPU Local Store MFC Power Processor (PPE) System Memory N SPE executes PPE Gets Results SPE Puts Results SPU N Local Store 27 MFC SPE Independently Stages Text & Intermediate Data Transfers while executing

28 Single source approach to programming Cell Single Source Compiler Auto parallelization ( treat target Cell as an SMP ) Auto SIMD-ization ( SIMD-vectorization ) Compiler management of Local Store as 2 nd level register file / SW managed cache (I&D) Most Cell unique piece Optimization OpenMP pragmas Vector.org SIMD intrinsics Data/Code partitioning Streaming / pre-specifying code/data use Prototype Single Source Compiler Developed in IBM Research 28

29 Applications 29

30 Cell BE Performance Characteristics VERY GOOD Computationally intensive code ( loops can be unrolled ) Order of magnitude more flops Scatter-gather type problems ( e.g.fft, Raycasting, sparse matrices(?) ) Almost two orders of magnitude more performance than a typical PC processor NOT OPTIMIZED FOR Rapid context switch LS is context, switch is about 30uSec Run to completion is preferred Cooperative switching works well Pre-emptive switch is possible Load-compare-add-branch (TPCC, gcc type codes) 6 cycle load hurts Still 8 (10) threads on a single chip 30

31 Terrain Rendering Engine 31

32 Planned Usage of Cell Sony Playstation million units / year Current Sony installed base 190 million units (PS1 & PS2) Cell Development Center reporting directly to CEO Toshiba Cell on PC-type form factor card (October 2005) IBM White box form factor Reference system for Cell Engineering and Technology Services Custom designs and application utilizing cell Mercury Computer Cell based systems 32

33 User Interaction Drives Innovation in Computing Immersive Interaction Online Gaming Level of Interaction Main Frame Batch Punch Cards Main Frame Multitasking Green Screen/ Teletype Mini-Computer WYSIWYG Word Processing Time Stand Alone PC Windows Spreadsheet Client/Server Internet WWW Gaming Source: J.A. Kahle 33

34 Characteristics of the Latest Transition in User Interaction Windows Click and wait Client-centric User data accessible from client only Device-centric Connected Wired, sporadic /newsgroups 34 Immersive, 3D interactivity Real-time Distributed User data accessible everywhere Device-agnostic Collaborative Wireless, always-on Text messaging/blogs

35 Summary & Conclusions 35

36 Summary Cell ushers in a new era of leading edge processors optimized for digital media and entertainment Desire for realism is driving a convergence between supercomputing and entertainment New levels of performance and power efficiency beyond what is achieved by PC processors Responsiveness to the human user and the network are key drivers for Cell Cell will enable entirely new classes of applications, even beyond those we contemplate today TIME TO GET IN THE GAME! 36