MPC55xx Highlighted Features

Transcription

1 MPC55xx Highlighted Features

2 Why Do I Need an etpu? Number one constraint of microcontrollers is their limited ability to perform high speed time related tasks. Limited by CPU interrupt overhead in servicing timers and other peripherals. Some applications may use more than 70% of CPU time to perform these tasks. The flexibility of the microcontroller has been severely limited by the fixed functionality and number of timer pins. Freescale F l Solution Defined The Enhanced Time Processor Unit (etpu) is a programmable I/O controller with it s own core and memory system, allowing it to perform complex timing and I/O management independently of the CPU. Detects and precisely records timing of input events Generates complex output waveforms The etpu is an upgrade of the original TPU featured in Freescale s MPC500 and 68K families. The etpu is dedicated to handling complex control, I/O, and timing algorithms. Microcontroller is free to handle other tasks, allowing for more system throughput and increased system performance. Since the etpu was designed for the complex I/O management required in automotive engines, it can handle even the most demanding timing applications. etp 1

3 Solenoid control Stepper motor control Detecting when input events occur Measuring pulse widths and periods Schedule an output event (rising or falling edge) or pulse based on a timer Why Do I Need emios? emios provides functionality to generate or measure time events Uses timer channels that are a reduced version of the unified channel (UC) module used on MPC555x devices Each channel provides a subset of the functionality available in the unified channel, at a resolution of 16 bits, and provides a consistent user interface with previous emios implementations. Vary output pulse width and frequency to solenoids using output pulse width frequency modulation (OPWFM) mode Control motors using Output Pulse Width mode (OPWM) or Center Aligned Output Pulse Width Modulation with dead time insertion using a channel in Input Capture mode, capture the time when a transition occurs and optionally generate an interrupt or DMA transfer Using a channel in Input Pulse Width or Input Period Measurement mode, measure two input edges ( double action ) then optionally generate an interrupt or DMA transfer Schedule an event with Single Action Output Compare or a pulse with Double Action Output compare where edges are synchronized with a counter 2

4 Why Do I Need a Programmable Interrupt Timer (PIT)? Simple, cost-effective timers for RTOS ticks, periodic DMA transfers, periodic A/D conversions Low power timer for system wakeup PIT is an array of timers that can be used to initiate interrupts and trigger DMA channels Provides a dedicated real-time interrupt (RTI) timer, which runs on a separate clock and can be used for system wakeup Simpler, lower cost timers than emios Timers can be configured to trigger A/D conversions or DMA transfers. Timers generate simple interrupts for RTOS. Real-time clock uses separate low power clock source and can be used for wake up from low power mode. 3

5 Why Do I Need Deserial Serial Peripheral Interface (DSPI)? Communicate with on-board peripherals, such as Smart MOS drivers for configuration and status Get more signals in and out of a package, which is pad limited DSPI provides a synchronous serial bus for communication between the MCU and an external peripheral p device. Serialization of parallel outputs and/or deserialization of serial inputs Physical protocol fully compatible with QSPI on MPC5xx family Master and Slave modes support Supports pin count reduction through serialization ation and deserialization ation of etpu channels, emios channels and memory-mapped registers Incoming serial data may be used to trigger external interrupt requests through DSPI deserialized output connections to the SIU 4

6 Why Do I Need a Memory Protection Unit (MPU)? Protect small memory areas from unauthorized access Meet RTOS requirements Using gpre-programmed p region descriptors that define memory spaces and their associated access rights, MPU concurrently monitors all system bus transactions and evaluates the appropriateness of each transfer. Memory references with sufficient access control rights are allowed to complete, but references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. Implements a set of program-visible region descriptors that monitor all system bus addresses Provides hardware access control for all memory references generated in a device 5

7 Reducing Flash memory costs Why Do I Need Variable Length Encoding (VLE)? VLE instruction enhancements allow the Power Architecture technology instruction set to be represented by a modified instruction set made up from a mixture of 16-bit and 32-bit instructions. VLE cores will run both Power Architecture technology and VLE instruction encodings on a page by page basis (page defined using MMU) VLE is a re-encoding of the Power Architecture technology to improve code density up to 30% over classic Power Architecture with no noticeable impact to performance. 6

8 Devices with Highlighted Features 7