MICROPROCESSOR TECHNOLOGY

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1 MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 14 Ch.6 The 80186, 80188, and Microprocessors 21-Apr-15 1

2 Timers The 80186/80188 contain three fully programmable 16-bit timers and each is totally independent of the others. Timer 0 and timer 1 have input and output pins that allow them to count external events or generate waveforms. Timer 2 connects to the 80186/80188 clock. It is used as a DMA request source, as a pre-scaler for other timers, or as a watchdog timer. 21-Apr-15 2

3 M / IO The Timer Unit The timer unit contains one counting element which is responsible for updating all three counters. The counter element is responsible for generating the outputs on the pins T0OUT and T1OUT, reading the T0IN and T1IN pins, and causing a DMA request from the terminal count (TC) of timer Apr-15 3

4 Timer Register Operation Timers are controlled by a block of registers in the PCB. Each timer has a count register, maximum count register, and a control register. The count register contains a 16-bit number that is incremented whenever an input to the timer occurs. Timers 0, 1 are incremented at the +ve edge on an external input pin every fourth clock or by timer 2 o/p. 21-Apr-15 4

5 Timer Register Operation Timer 2 is clocked on every fourth clock pulse and has no other timing source. In the 8 MHz version, timer 2 operates at 2 MHz, and the maximum counting frequency of timers 0,1 is 2 MHz. Each timer has at least one maximum-count register, called a compare register that is loaded with the maximum count of the count register to generate an output. 21-Apr-15 5

6 Timer Register Operation Timers 0, 1 each have a second maximum count compare register. Using both maximum count registers allows the timer to count up to 131,072 instead of 65,536. The control register of each timer is 16-bit wide and specifies the operation of the timer. EN: Enable bit allows the timer to start counting INH: Inhibit bit allows a write to the timer control register to affect the enable bit. 21-Apr-15 6

7 Timer Register Operation INT: The interrupt bit allows an interrupt to be generated by the timer. RIU: Register in use bit indicates which maximumcount compare register is currently used by the timer. (Read-only bit) MC: Maximum count bit indicates that the timer has reached its maximum count. RTG: Re-trigger bit is active only for external clocking. It is used by timers 0,1 to select the operation of the timer input pins. 21-Apr-15 7

8 Timer Register Operation P: Prescaler bit selects the clocking source of timers 0,1. If P=1, the source is timer 2. If P=0, the source is one fourth the clock frequency. EXT: External bit selects internal timing when EXT=0 ALT: Alternate bit selects single maximum- count mode if ALT=0 or alternate if ALT=1. CONT: Continuous bit selects continuous operation if CONT=1 (i.e The counter automatically continues counting after it reaches its maximum) 21-Apr-15 8

9 Timer Output Pin Timers 0, 1 have an output pin used to generate either square waves or pulses. To produce pulses, the timer is operated in single maximum-count mode. To produce square waves the alternating mode ALT=1 is selected. Any duty cycle can be generated in the alternate mode. Example: 10% duty cycle 21-Apr-15 9

10 Timer Output Pin Solution: Maximum count register A is loaded with 10 Maximum count register B is loaded with 90 The o/p is logic 1 for 10 clocks and logic 0 for 90 clocks See the real-time clock example pages 146, Apr-15 10

11 DMA Controller The DMA controller has two fully-independent DMA channels. Each channel has its own set of 20-bit address registers. These registers are located in the PCB at offset address C0H-DFH Each channel contains a control word, a source and destination pointer, and a transfer count. The transfer count is 16-bit wide. The source and destination pointers are 20-bit wide 21-Apr-15 11

12 Channel Control Register M/IO: Indicates memory or I/O location DEC: Causes the pointer to be decremented. INC: Causes the pointer to be incremented. TC: Stop transfers when the channel count register is decremented to 0000H. INT: Enables interrupts to the interrupt controller SYN: Selects the type of synchronization for the channel P: Selects the channel priority (P=1 high priority) 21-Apr-15 12

13 Chip Selection Unit The chip selection unit simplifies the interface of memory and I/O to the 80186/ It contains programmable chip selection logic. Memory Chip Selects: Six pins are used to select different external memory components. The UCS pin enables the memory device located in upper portion of memory map (ROM). 21-Apr-15 13

14 Chip Selection Unit The LCS pin selects the memory device (RAM) that begins at memory location 00000H. The remaining 4 pins select middle memory devices. Peripheral Chip Selects: Seven external peripheral devices can be addressed with pins PCS0 PCS6. 21-Apr-15 14

15 Real-Time Operating System (RTOS) The RTOS is an operating system used in embedded applications that performs tasks in a predictable amount of time. Operating systems, like WINDOWS, defer many tasks and do not guarantee their execution in a predictable time. There are three components to all operating systems: (1) Initialization (2) Kernel (3) Data & Procedures 21-Apr-15 15

16 Real-Time Operating System (RTOS) The initialization section is used to program all hardware components in the system, load drivers specific to a system, and program the contents of the µp s registers. The kernel performs the basic system task, provides system calls or functions, and comprises the embedded system. The data & procedure section holds all procedures and any static data used by the OS. 21-Apr-15 16

17 Introduction to The is an advanced version of the 8086 that was designed for multi-user and multitasking environments. The addresses 16MB of physical memory and 1 GB of virtual memory. The is an optimized 8086 that executes instructions in fewer clocking periods than the The contains a memory manager 21-Apr-15 17

18 The Hardware Features The contains a memory management unit (MMU) which is called the address unit in P The address bus is now 24-bit wide to accommodate the 16 MB of physical memory (A0 A23). The does not have a multiplexed address/data bus. New additional pins: BUSY, CAP, ERROR, PEREQ, and PEACK 21-Apr-15 18

19 The Hardware Features The 286 operates in both the real and protected modes. In real mode, the addresses 1MB memory address space and is virtually identical to In protected mode, the addresses 16 MB of memory space. The clock is provided by the clock generator. The system control signals are provided by the system bus controller. No latch circuits (No de-multiplexing) 21-Apr-15 19

20 Additional Instructions The extra instructions control the virtual memory system through the MMU. CLTS: Clear task-switched flag clears the TS flag bit to logic 0. LAR: The Load Access Rights instruction reads the segment descriptor and places a copy of the access rights byte into a 16-bit register. LSL: Load Segment Limit loads a userspecified register with the segment limit. 21-Apr-15 20

21 Additional Instructions ARPL: Adjust Requested Privilege level is used to test a selector so that the privilege level of the requested selector is not violated. VERR: Verify for Read access verifies that a segment can be read. VERW: Verify for Write access verifies that a segment can be written. 21-Apr-15 21

22 Thank You With all best wishes!! 21-Apr-15 22

MICROPROCESSOR TECHNOLOGY

MICROPROCESSOR TECHNOLOGY Assis. Prof. Hossam El-Din Moustafa Lecture 13 Ch.6 The 80186, 80188, and 80286 Microprocessors 21-Apr-15 1 Chapter Objectives Describe the hardware and software enhancements