Design of emmc Controller with Virtual Channels for Multiple Processors

Transcription

1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, 2018 ISSN(Print) https//doi.org/ /jsts ISSN(Online) Design of emmc Controller with Virtual Channels for Multiple s Chanho Lee and Chulhoon Kim Abstract Portable embedded systems includes several non-volatile memory devices for the external storage. Multiple processors and multiple processing are popular and reading and writing data in the storage limit the performance of the system. The conventional architectures combine the devices to a single channel or assign the devices to multiple channels one by one to increase the performance. However, performance improvement depends on the applications due to the various requirements of data transfer. In this paper, we propose architecture for non-volatile memory controller with virtual channels for systems with multiple processors. The proposed architecture has an AMBA AXI master interface for data transfer and an AMBA APB slave interface for writing instructors and reading status and responses to be connected to a host system. adapters are connected to the devices and form physical channels. It can respond to the requests of the multiple processors by configuring virtual channels which have a single or multiple physical channels and can be activated independently. The waiting times and the transfer times of memory requests can be traded-off dynamically for the better system performance. An emmc controller is designed using Verilog-HDL according to the proposed architecture, and is implemented using an FPGA. The operation of the controller is verified by simulation and measurement. Index Terms emmc, memory controller, virtual channel, multiple channels, dynamic configuration Manuscript received Apr. 23, 2017; accepted Oct. 9, 2017 School of Electronic Engineering, Soongsil University, Seoul, Korea chlee@ssu.ac.kr I. INTRODUCTION Digital systems consists of processors, maim memory, non-volatile storage, and peripherals. The performance improvement of processors exceeds that of memories due to the development of design and process technology. The memory access operations are the bottleneck of system performance nowadays. The portable embedded systems with multiple processors are becoming popular, and they also encounter the same problem. The popular approach for the main memory which usually consists of a DRAM device is the scheduling or arbitration of requests to increase the efficiency of the DRAM utilization and to prioritize the requests [1-4]. The portable embedded systems require external nonvolatile memories to store application codes and data. They usually utilize semiconductor non-volatile memory devices for the storage and they demand external nonvolatile memory with high performance and high capacity. Embedded multimedia card or emmc [5] is a next generation external non-volatile memory and includes both NAND flash memory and enhanced multimedia card (MMC) controller. It is expected to be used widely in embedded systems by replacing the secure digital (SD) card due to the improved performance and the modified package. The data width of the SD card which is widely used as an external nonvolatile memory is 4 bits and the package requires specific types of readers. The SD cards do not satisfy the requests of the multiple processors since they respond to the requests sequentially with low performance and the limitation of the package. On the other hand, the data width of the emmc device is 8 bits with enhanced operation modes and the performance is higher by up to

2 228 CHANHO LEE et al DESIGN OF EMMC CONTROLLER WITH VIRTUAL CHANNELS FOR MULTIPLE PROCESSORS 8 times than that of the SD card. The modified package type enables the emmc devices to install on a PCB directly and an additional reader is not necessary. Flash memory-based memory controllers need to provide multiple channels to satisfy the demands of increased data bandwidth and multiple requests of multiple processors. The data bandwidth can be increased by connecting multiple devices to a single channel to increase the data bit widths although multiple requests cannot be processed simultaneously. The idea came from the RAID solution for HDD, which considers multiple disks as a single disk to increase performance or reliability [6]. A single access to a flash memory requires much larger number of cycles compared with the DRAM [1]. As a result, the order of transactions affects the waiting times of processors a lot, and a different approach is desirable for the external memory. By the way, multiple numbers of devices are often installed for high capacity. Many architectures have been reported to increase the performance of reading and writing data in the nonvolatile memory by increasing physical channels for one logical channel [7-9]. They cannot process the multiple requests simultaneously although they increase the bandwidth of data transfer. Another architecture includes multiple logical channels to process multiple requests, and each channel controls multiple devices to increase the data bandwidth [10]. They assume a lot of numbers of devices are available since they are developed for the solid state drives (SSD). However, the portable embedded systems without the SSD can contain only several devices due to the small size. In addition, the channel configurations of the architectures mentioned above are fixed and cannot be changed while operation. It cannot satisfy the requirements of various types of requests generated in general-purpose systems. Multiple requests can be processed simultaneously if the controller has as many numbers of channels as the devices so that each device is controlled independently although the data bandwidth for each request may not be increased. A system with multiple processors may handle multiple processes and some of them may require short waiting times for storage accesses while others may require fast transfer times. The memory controller need to provide both demands to increase the overall performance the system. In this paper, we propose an architecture of emmc controllers with enhanced data bandwidth and multiple request processing. It consists of an application adaptor (AA), device adaptors (DA) and a virtual channel controller (VCC). The application adaptor is used for communication with host systems and consists of AMBA AXI master interfaces and an AMBA APB slave interface [11, 12]. A host system configures the controller, sends commands, and reads the status of the controller and the responses of devices using the APB slave interface. The controller transfers data using the high performance AXI master interface with direct memory access controllers (DMAC). adaptors manipulate the devices directly according to the control signals of the virtual channel controller. They generate and send commands to emmc devices, and receive the responses from them along with the data. The virtual channel controller configures virtual channels (VC) according to the directions of host systems or built-in algorithms. It assigns device adaptors to the virtual channels and sends control signals for each device adaptor according to the requests of host systems. It can create and assign virtual channels dynamically depending on the request of the host system. An emmc controller is designed using Verilog-HDL according to the proposed architecture, and implemented using an FPGA for verification. II. ARCHITECTURE The previous emmc controllers has a single channel with a single device or multiple devices tied together [13-15]. The proposed emmc controller with multiple channels processes multiple requests from multiple processors simultaneously and increases the data bandwidth. The improvement can be achieved by two schemes. First, increasing the number of interfaces between processors and a controller improves the performance of communication. An AXI master interface can perform read and write transactions simultaneously, and an additional interface will increase the performance. The number of interfaces is importance when processors require a large amount of data and a short response time or latency. Improving the performance of network architecture will satisfy the requirement of data bandwidth without increasing the number of interfaces

3 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, Application APB Virtual Channel Controller Virtual Channel Controller (VCC) control signals s CLK CMD DATA emmc devices emmc device AXI wdata Fig. 2. Block diagram of APB slave interface logic. rdata when the latency is not important. Secondly, improving the performance between a controller and devices increases the data bandwidth. The controller can control multiple devices independently or together. The independent control will increase the parallelism to improve the latency and the simultaneous control by combining devices will increase the data bandwidth. The performance of communication between the controller and devices should be balanced with that between processors and the controller for the effective improvement of the system performance. Fig. 1 shows the block diagram of the proposed architecture. The proposed architecture includes an application adaptor, a virtual channel controller, and device adaptors. The application adaptor communicates with the host, and device adaptors control emmc devices by sending commands and data as well as receiving responses and data. The virtual channel controller configures virtual channels and controls emmc adaptors according to the virtual channel configurations. 1. Application control signals CLK CMD DATA emmc device Fig. 1. Block diagram of the proposed emmc controller architecture. The application adaptor communicates with the host system and has interfaces with the same interface protocols as those of the host system. The proposed architecture includes an AMBA APB slave interface for commands, status and responses, and an AMBA AXI master interface for data transfer. A. APB Slave Interface Host processors configure the controller, send commands, and read the status of the controller and responses of devices through the APB slave interface. A host processor writes parameters to configuration registers to configure the controller and the virtual channels. It also reads status and responses in registers for the following operations. The register bank shown in Fig. 2 holds configuration parameters, status values of the controller, and responses of devices. The configuration parameters specify a block size, a number of blocks, addresses for the DMAC in the AXI master interface, an operation mode, time-out conditions, and so on. The APB interface includes a command queue as shown in Fig. 2 to store commands and arguments that the virtual channel controller reads for the next operation without waiting. s write multiple commands and arguments to the command queue for the continuous operations unless a command is dependent on the response of the previous command. The amount of data through the slave interface of the application adaptor and we employ the APB interface since it is simple. However, the salve interface can be the AHB or the AXI slave interface if necessary. B. AXI Master Interface The AXI master interface of the application adaptor transfers data between a host system and the memory controller. Fig. 3 shows the block diagram of the AXI interface. It has both write and read channel units since the AXI protocol allows the simultaneous read and write operations. Each channel unit has its own DMAC for high performance. The data bandwidth can be doubled if the AXI interface performs read and write operations simultaneously and continuously. The DMACs in the AXI interface increase the performance of the data transfer. It takes at least twice the number of cycles to transfer data if the DMAC is outside the memory controller. The proposed architecture

4 230 CHANHO LEE et al DESIGN OF EMMC CONTROLLER WITH VIRTUAL CHANNELS FOR MULTIPLE PROCESSORS Fig. 3. Block diagram of AXI master interface with DMAC. includes DMACs in the controller which read or write data directly. The host system can control the DMACs using the APB slave interface. A simulation result of data transfer of 512 Byte which is the minimum size of a block shows that the number of operation cycles using an internal DMAC is reduced by 90% compared with that using an external DMAC. An AXI master interface can handle the data transfer of several devices since it has much higher data bandwidth than the emmc devices. For example, an AXI master interface with 64 bit data width and 200MHz operating frequency can accommodate at least 4 emmc devices in the HS400 mode. The number of devices increases when read and write operations are interleaved. The increase in the number of AXI master interfaces can improve the system performance if more than 4 devices are connected in the above example or the response times of requests are important. 2. A device adaptor controls a memory device physically and consists of a command controller and a data controller. The command controller sends commands for a device at proper timing and receives responses according to the commands of the virtual channel controller. The data controller transfers data between the AXI interface and emmc devices. Fig. 4 shows the block diagram of the device controller. A. Command Controller The command controller generates commands according to the direction of the virtual channel controller, and checks the validity of command issuing and responses from a device. It sends command bits and collects the responses through the CMD line. It encodes Command Queue Register Bank w_async FIFO r_async FIFO VCC Command and control Response Status wdata control signal rdata Fig. 4. Block diagram of device controller. commands and decodes responses using the cyclic redundancy codes 7 (CRC7) to detect transmission errors. It also configures status registers so that a host processor can reads the status of the memory controller and the results of requests. B. Data Controller The data controller transfers data between devices and the buffers of the DMACs via the virtual channel controller. The buffers are asynchronous FIFO memories for read and write operations, and have double buffering structure so that multiple blocks of data are transferred without interruption. The data controller also generates appropriate control signals for the FIFOs in the operation modes of SDR, DDR, HS200 and HS400 [5]. It encodes and decodes data using the cyclic redundancy codes 16 (CRC16) to detect transmission errors, and configures a status register. 3. Virtual Channel Controller contoller Command controller crc7 Data contoller crc16 DAT The proposed emmc controller with multiple channels processes multiple requests of hosts simultaneously to increase the system performance when multiple devices are connected. The virtual channel controller controls the device controllers independently according to the requests of host processors so that the data bandwidth is increased and the response times are reduced. The virtual channel controller is the core block of the proposed emmc controller that enables the multiple processing of memory requests. It creates or assigns a virtual channel according to the request of the host. The DS

5 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, virtual channel includes at least one physical channel which consists of a device adaptor and a device. The virtual channel controller sends the same commands to each device adaptor if more than one physical channels are assigned to a virtual channel. The data from the buffers are divided for writing and the data from the devices are combined for reading according to the number of physical channels and the predefined scheme. For example, 2 byte data are read and the upper byte and the lower byte are given to the first and the second physical channel for writing, respectively if a virtual channel includes two physical channels while the same commands are given to the physical channels. The degree of freedom for parallel operations increases as the number of virtual channels increases. The data bandwidth or the performance of a memory request increases as the number of physical channels in a virtual channel increases. Fig. 5 shows the block diagram of a virtual channel controller. The VC configuration and control block configures the virtual channels according to schemes determined by users, and receives the requests from host processors to distribute them to virtual channels. The host delivers configuration information using the APB slave interface when it determines the virtual channel configuration scheme. The host can determine the VC configuration to optimize the system performance. Otherwise, VC configuration and control block can include a processor or a hard-wired logic for the VC configuration so that the VC configuration is determined based on the patterns of memory requests to optimize the memory access operations. The software for the processor in the VCC can be modified depending on the host systems. The VC configuration can be changed dynamically to improve the system performance. The VCC includes a table which configures VCs. A new VC is added when it is created and an existing VC can be deleted when it is not necessary. A VC is activated when a request is assigned to it. Once a virtual channel is configured and a request is assigned, the VC operates independently until it completes the request. The VC supervises its device controller(s) by sending commands and receiving responses of devices. The VCC monitors the operations of VCs and controls data flow using a routing logic which makes a physical channel between the AXI master Configuration Requests (APB Slave) wdata (AXI Master) rdata (AXI Master) VC Config. & Control Write Data Control Read Data Control Virtual Channel Controller VC_0 VC_N Routing logic Fig. 5. Block diagram of virtual channel controller. _0 _1 _2 VCC interface and the device controller(s). The data in the host has a word format which is usually 8 bytes in the AXI network while the data format for an emmc device is 1/2/4/8 bits. The write/read control block translates the data format between the application adaptor and the device adaptors. The conventional memory controllers usually combine the physical channels into one logical channel to increase the data bandwidth when multiple memory devices are connected [7-9, 14]. It will show the maximum performance for a single request. Otherwise, they have multiple logical channels which have the same number of devices [10]. However, it is not the best solution when a system performs multiple processes with multiple processors. Fig. 6 shows an example of virtual channel configuration and assignment for a host system with three processors. The memory system includes four devices and three virtual channels are configured. VC_0 includes two physical channels while VC_1 and VC_2 VC_0 VC_1 VC_2 Commands Responses emmc0 emmc1 emmc2 emmc3 Fig. 6. Example of virtual-channel configuration and assignment for a host system with 3 processors.

6 232 CHANHO LEE et al DESIGN OF EMMC CONTROLLER WITH VIRTUAL CHANNELS FOR MULTIPLE PROCESSORS include one physical channel so that VC_0 has twice the read and write performance. _0, _1 and _2 are assigned to VC_0, VC_1, and VC_2, respectively, for the current operation since _0 requires more data bandwidth. The assignment may be changed later when _1 requests higher data bandwidth or data in the devices of VC_0. The VCC may change the configuration to VC_3 with four devices when _2 requires the maximum performance while other processors are idle. VC_0, VC_1 and VC_2 are inactive when VC_3 becomes active. The processors make requests with the information of virtual channels when the host configures the virtual channels. The VCC assigns the requests to the corresponding virtual channels. The proposed architecture gives degree of freedom to design a system for the external memory management. APB Slave Host system emmc memory controller CMD AXI4 network DAT DS Main memory (AXI Slave) AXI4 Master CLK ROM (AXI Master) emmc model emmc model emmc model emmc model Fig. 7. Block diagram of host system for simulation of the proposed emmc controller. Four processors and other peripherals are included for simulation. III. DESIGN AND IMPLEMENTATION 1. Design and Performance Analysis An emmc memory controller is designed based on the proposed architecture using Verilog-HDL and the operations and the performance are measured and analyzed by simulation with an emmc simulation model. Fig. 7 shows the system for the simulation. It consists of four host processors, a main memory with the AXI slave interface, a ROM with an AXI master interface, an AXI network, the emmc memory controller with the proposed architecture and four emmc simulation models. The host processors configure the memory controller, make requests, and read status through the APB slave interface. The AXI network connects the APB slave interface using an AXI-to-APB converter. The memory controller writes or reads data in the main memory through the AXI master interface according to the requests of host processors. The ROM contains initial data and writes them to the main memory when the simulation starts. The emmc devices are configured to operate in the HS400 mode and 8 bit data width for the highest performance. We compare the performance of the proposed memory controller with that of a conventional memory controller with the emmc devices tied together. The conventional memory controller shows the maximum performance for a single request. Fig. 8 shows the simulation result of 2 kb data writing Fig. 8. Waveform of 2 kb write operation using a virtual channel of quadruple bandwidth. which consists of data collection by the DMAC in the application adaptor and data transfer to the memory devices. A single VC includes four physical channels and the DMAC in the memory controller reads 2 kb data in the main memory and writes them to emmc devices through the VC. The data should be transferred to fill up buffers in the controller first ( DMAC Read Data Cycle ) since the minimum size of data transfer is 512 byte or one block, and then, they are written to the emmc devices ( emmc Write cycle ) as shown in Fig. 8. The upper part (denoted by emmc Write cycle ) of the waveform shows the data transfer in the physical channels and the lower part (denoted by DMAC Read Data Cycle ) shows the operation of the application adaptor. Fig. 9 shows the simulation results when each processor requests reading four blocks of data to compare the data transfer using one and four logical channels for the same number of memory devices. The conventional memory controller uses one VC with four devices or four VCs with a device. With one VC, the

7 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, P0_16 P1_2 P2_2 P3_2 P0_2 Fig. 9. Waveforms of reading four blocks of data for the requests of four processors Single VC with four devices, Four VCs with one device. controller reads one block of data from each device simultaneously, and completes the transfer of four blocks of data for P0. After that, it transfers data for P1, P2 and P3 in turn as shown in Fig. 9, and it takes 1810 cycles to finish the job. The operation corresponds to that of the conventional memory controllers with a single channel and multiple devices [7-9, 14]. Otherwise, it transfers one block of data for each request with four VCs and then repeats the transfers as shown in Fig. 9. It takes 1838 cycles to finish the job. The first block of data for P1 is transferred after the transfer of the first block for P0 which is denoted by a small rectangle on the P0 arrow in Fig. 9. The second block of data for P0 follows the transfer of the first block of data for P3. Fig. 9 shows that the single VC configuration outperforms by 1.5% if the number of cycles to complete all the requests are compared. However, the system-level performance of the four VC configuration will be better if all the processors request simultaneously and wait for the data for the following operation. From now on, the conventional controller represents the single VC configuration to compare the performance with the proposed controller since the total number of cycles is smaller with the single VC. Fig. 10 shows the simulation results when a processor requests much larger amount of data than others. _0 writes 16 blocks (P0_16) and 2 blocks Fig. 10. Waveforms of write operations for the requests of four processors. _0 16 and 2 blocks of data. Others 2 blocks of data Conventional memory controller, Proposed memory controller. (P0_2) of data, and other processors write 2 blocks of data (P1_2, P2_2, P3_2). The conventional memory controller writes 16 blocks of data first according to the priority and the order of arrival, and the 2 blocks of data sequentially. The transfer of 2 blocks of data consumes cycles for 4 blocks of data which is 6889 cycles while it takes advantage of the tied connection to transfer 16 blocks of data. On the other hand, the proposed controller writes 16 blocks of data first using VC0 with four physical channels, and then it processes two requests of writing 2 blocks of data simultaneously using two VCs with two physical channels (VC1 and VC2). The second request starts the data transfer after the latency for filling up the buffer, and the entire job is completed in 6256 cycles. The performance of the proposed memory controller is higher by 22% than that of the conventional one if the numbers of cycles to complete the job are compared. Fig. 11 shows the simulations results when four processors request writing and reading different amount of data. _0, _1, and _3 write 4 blocks of data (P0_W, P1_W, P3_W), and _2 reads 4 blocks of data (P2_R). In addition, _0 reads 10 blocks of data (P0_R) after _2 writes 10 blocks of data (P2_W). The conventional memory controller processes the requests sequentially in the order of arrival or according to the priority as shown in Fig.

8 234 CHANHO LEE et al DESIGN OF EMMC CONTROLLER WITH VIRTUAL CHANNELS FOR MULTIPLE PROCESSORS FPGA Block RAM AXI4 network AHB to APB Bridge emmc memory controller CLK DS DAT CMD emmc device Fig. 11. Waveforms of write operations for the requests of four processors. 3, 4, 6, and 7 blocks of data Conventional memory controller, Proposed memory controller. 11. It takes 6,889 cycles to complete the data transfer, and the processors have to wait for the responses. The proposed memory controller creates two VCs (VC0, VC1) with two physical channels and processes two requests together using two VCs as shown in Fig. 11. It takes 6,256 cycles to complete the requests, and the performance of the proposed memory controller is higher by 19% than that of the conventional one. The proposed controller can create four VCs with single physical channels for the requests of 4 blocks and another two VCs with two physical channels for the requests of 10 blocks if the waiting time is important. The waiting time represents the time for which a processor waits until the first data or the response signals arrive. The proposed memory controller can adjust the waiting time and the transfer time of the requests of processors depending on the requirement of host systems by assigning appropriate VCs. It can process four requests simultaneously using four VCs if the waiting time is important for the processors as described above. It can process the request of _2 using a four channel VC if the request needs to be completed immediately, and then processes other requests using three VCs simultaneously. The overall performance of the proposed memory controller is better than that of the conventional one in all cases while the waiting time and the transfer time can be adjusted depending on the Fig. 12. Implementation of verification system Block diagram, FPGA prototyping board. demand of the host system. 2. Implementation The proposed memory controller is implemented using an FPGA and a 0.18 um CMOS standard cell library. Fig. 12 shows the verification system on an FPGA prototyping board. It is similar to the verification system for simulation except that the ROM is removed and the data in the main memory are initialized when programming the FPGA. A single emmc device on a customized PCB is connected to the FPGA prototyping board due to the limited extensibility of the prototyping board and the availability of the devices. Fig. 13 shows the operation sequence of emmc devices for Identification and Data Transfer mode. The memory controller identifies the device information and CID of the device, and selects the device using CMD7 to read or write data in the Data Transfer mode. A software for verification is loaded on the block RAM and a

9 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, Fig. 13. Operation sequence of emmc devices. processor sends emmc commands to the device according to the operation sequence of emmc devices. The software displays the status of execution including commands and responses in a display. Fig. 14 shows verification results of device identification and data read after write. The responses of CMD2 are shown in Fig. 14 as binary raw CID data in the left side and are translated into alphanumeric characters in the right side. Fig. 14 shows 16 x 32 bit data written to the emmc device in the left side, and the data read from the same device and addresses. The data are exactly the same, which shows that the memory controller.works correctly. Fig. 15 shows the measurement results of clock (CLK) and data (DAT[0]) signals of the emmc memory controller implemented on the FPGA as shown in Fig. 12. The clocks of 50 MHz and 75 MHz are applied in the measurement with the operation mode of the device is HS400 because of the performance limitation in the connection between the prototyping board and the emmc daughter board. The measured results show that the emmc controller reads data sequentially through the DAT[0] pin at 50 MHz and 75 MHz, respectively after writing them. The proposed emmc controller is synthesized using Synopsys Design Compiler and a 0.18 um CMOS standard cell library. The maximum operating frequency is 295 MHz which is much higher than the operation frequency of the HS400 Fig. 14. Measurement results of writing and reading an emmc device with the proposed memory controller Identification results. Left raw CID data. Right translated CID data, Writing and reading results. Left data before writing to emmc device. Right data read from emmc device after writing. Fig. 15. Measured results of clock and data line signals from an FPGA at 50 MHz, 75 MHz. mode, 200 MHz as shown in Table 1. The controller occupies 42,095 gate counts and includes 12.2 kb SRAM for buffers.

10 236 CHANHO LEE et al DESIGN OF EMMC CONTROLLER WITH VIRTUAL CHANNELS FOR MULTIPLE PROCESSORS Table 1. Synthesis results using Synopsys Design Compiler Technology Max. operating frequency IV. CONCLUSIONS The architecture for an emmc memory controller is proposed and implemented. It has a virtual channel controller which creates virtual channels and assigns memory requests to them. A virtual channel can consist of multiple physical channels and can be created and assigned dynamically to increase the performance. The application adaptor of the controller has one or more master interfaces with DMACs for high performance of data transfer and a slave interface for configuration, memory requests, and providing information. The proposed emmc memory controller shows higher performance by up to 22% than the conventional one with multiple devices and without virtual channels. The proposed architecture can adjust the waiting time and the transfer time dynamically depending on the demand of the host system, and shows good performance for multiple processor systems. It is implemented on an FPGA prototyping board and the operation is verified and the maximum operation frequency is 295 MHz when it is synthesized using a 0.18um CMOS standard cell library. The proposed architecture can change the physical channel configurations dynamically depending on the requests of multiple processors using the virtual channels in order to maximize the system performance and to increase the efficiency of resource utilization. It can satisfy both the requirement of the bandwidth and the waiting time of data transfer, and can apply to embedded systems with the limited number of memory devices. ACKNOWLEDGMENTS 0.18 um CMOS 295 MHz Logic gate counts 42,095 SRAM size in buffers 12.2 kb This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MOE) (NRF-2016R1D1A1B ). The EDA tools were supported by IDEC. The authors thank to PaxDisk Inc. for the fabrication of a prototyping board and measurements. REFERENCES [1] Y. Song, K. Samadi and B. Lin, Single-tier virtual queuing An efficacious memory controller architecture for MPSoCs with multiple realtime cores, DAC2016, Austin, TX, USA, pp. 1-6, June [2] A. Mohamed, A. El-Moursy and H. Fahmy, Real- Time Memory Controller for Embedded Multi-core System, HPCC2015, New York, USA, pp , August [3] M. Gomony, B. Akesson, and K. Goossns, Architecture and optimal configuration of a realtime multi-channel memory controller, DATE2013, Grenoble, France, pp , March [4] X.-T. Nguyen, H.-T. Nguyen and C.-K. Pham, Parallel pipelining configurable multi-port memory controller for multimedia applications, ISCAS2015, Lisbon, Portugal, pp , May [5] JEDEC., Embedded Multi-Media Card (emmc) Electrical Standard(5.1), JEDEC JESD84-B51, February [6] SNIA, Common raid Disk Data Format (DDF), SNIA, April [7] S. Treesa J. and C. Pradeep, Design of a multichannel NAND Flash memory controller for efficient utilization of bandwidth in SSDs, imac4s 2013, Kottayam, Kerala, India, pp , March [8] J.-U. Kang, J.-S. Kim, C. Park, H. Park, and J. Lee, A multi-channel architecture for high-performance NAND flash-based storage system, Journal of Systems Architecture, Vol. 53, No. 9, pp , September, 2007 [9] Y. Ou, N. Xiao, and M. Lai, A Scalable Multichannel Parallel NAND Flash Memory Controller Architecture, ChinaGrid 2011, Dalian, Liaoning, China, pp Aug [10] Y. J. Seong, E. H. Nam, J. H. Yoon, H. Kim, J.-Y. Choi, S. Lee, Y. H. Bae, J. Lee, Y. Cho, and S. L. Min, Hydra A Block-Mapped Parallel Flash Memory Solid-State Disk Architecture, IEEE Transactions on Computers, Vol. 59, No. 7, pp , July 2010 [11] ARM, AMBA APB Protocol Specification, ARM

11 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.18, NO.2, APRIL, IHI 0024C, April [12] ARM, AMBA AXI and ACE Protocol Specification.., ARM IHI 0022E, February 2013 [13] C. Kim and C. Lee, "Design of programmable high performance emmc controller," IEIE SoC Conference, Seoul, Rep. of Korea, May [14] C. Kim and C. Lee, "Design of emmc controller with multiple channels," ISOCC2016, Jeju, Korea, pp , October [15] N. Fu, Y. Li, B. Liu, H. Xu and Y. Zhang, "Realization of controlling emmc 5.0 device based on FPGA for automation test system," AUTOTESTCON2015, National Harbor, MD, USA, pp , November Chulhoon Kim received the B.S. degree in the School of Electronic Engineering from Soongsil University, Seoul, Korea in Currently, he is a researcher in SK Hynix. His research interest is memory controllers for flash memory and DRAM. Chanho Lee received the BS and MS degrees in electronic engineering from Seoul National University, Seoul, Korea, in 1987 and 1989, and the PhD degree from the University of California, Los Angeles, in In 1994, he joined the semiconductor R&D center of Samsung Electronics, Giheung, Korea. Since 1995, he has been a faculty member of the School of Electronic Engineering, Soongsil University, Seoul, Korea. His research interests are in SoC on-chip-network, SoC platform, memory controller, image recognition using deep learning for ADAS. He is a senior member of IEEE.