A Low Power 720p Motion Estimation Processor with 3D Stacked Memory

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1 A Low Power 720p Motion Estimation Processor with 3D Stacked Memory Shuping Zhang, Jinjia Zhou, Dajiang Zhou and Satoshi Goto Graduate School of Information, Production and Systems, Waseda University 2-7 Hibikino, Kitakyushu , Japan Abstract In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to 1) reduce the memory and core power consumption; 2) provide higher bandwidth. Firstly, a memory die is designed and staked with MEP die. By adding face-to-face (F2F) pad and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is applied to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization, power network generation, etc. Comparing with 2D technology, the number of IO pins is reduced by 77%. After optimizing the floor plan of the MEP die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the max bandwidth is more than 14GB/s and whole design can support real-time 720p@60fps encoding at 8MHz with less than 65mW, which is only one sixth of the stateof-the-art MEP. Keywords 3DIC design; motion estimation processor; low power design; memory stacking I. INTRODUCTION With the development of semiconductor technology, the portable devices become more and more powerful. Meanwhile, the camera integrated in the portable devices has higher and higher performance. The most obvious feature is that the capture resolution has been improved from 0.3 Megapixel to 10 Megapixel. With such a powerful camera, 720p, 1080p video recording and playback have been a common function in the new portable devices. Benefit from the portability of smart phones and the great expressivity of the video, more and more users tend to record their lives by video. But in the same time, power consumption has been the bottleneck of portable devices, many devices need to be charged once or even twice per day, which makes a bad experience to users. Users prefer a long battery life time to their portable devices. In a word, the popularity of video capture and playback by portable devices is increasing, so that a low power video codec is required. Many researches focused on the reduction of the power consumption on the video codec itself and got quite good results. V. Sze et al. [1] implemented a full real-time 720p H.264 decoder in 65nm, by using variety of techniques such as multiple voltage, frequency domains, frame level dynamic voltage and frequency scaling, the video decoder core power is reduced to 1.8mW. Y. Lin et al. [2] implemented a 1080p@30fps This research was supported by the regional innovation strategy support program of MEXT and Waseda University Graduate Program for Embodiment Informatics (FY2013-FY2019). H.264/AVC (advanced video coding) encoder in 130nm, by applying several techniques including complexity reduction, cross-stage hardware sharing, etc., the encoder core power is optimized to 242mW. However, although the video encoder/decoder core power is reduced significantly, working with an external dynamic random access memory (DRAM), the total power consumption is still high. Many works have been focused on reducing the DRAM power by decreasing the DRAM bandwidth requirement [3][4]. But conventional 2D integrated circuit process technology has encountered the bottleneck. Now many researchers are trying to solve the DRAM problem by 3D large scale integration (LSI). A good example is, for the regularity of the architecture of DRAM, an industrial high performance 8Gb 3D DDR3 memory has been developed in [5]. What s more, Samsung has applied 3D-TSV technology to its 30nm-class DRAM products to keep pace with Moore s Law and industry projections. Also many researches focus on wide IO memory [6] and hybrid memory cube (HMC) [7] to improve the performance. Not limited to the memory area, many researches were focusing on 3D LSI design. A 64 core processor with stacked memory was designed in [8], whose max throughput is up to 63.8GB/s. T. Zhao et al. [9] introduced a 5-tier stacked H.264 application with on-chip DRAM stacking. Even though the memory power is not given in [9], we can figure it out by [10] according to the characteristics given in [9]. The memory power is 492.5mW, which is still too high. In this paper, a motion estimation processor (MEP) with 3D stacked memory architecture is proposed to reduce the memory power and provide higher memory bandwidth. MEP is a key encoding component of almost all modern video coding standards. As profiled in [11], MEP takes more than 50% of the total computation time in an H.264/AVC encoder when configured to use single-direction full search and a search range (SR) of 32. The MEP used in this design is with a SR of 211 and 2 reference frames, which will consume more. This work focuses on reducing the MEP power by 3D integration technology. Firstly, a memory die is designed and stacked with our previous MEP die. By adding face-to-face (F2F) pads and through silicon vias (TSV) definitions, 2D electronic design automation (EDA) tools are extended to support the proposed 3D stacking architecture. Moreover, a novel memory controller is designed to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including TSV/F2F placement, floor plan optimization of two dies, power network generations, and so on. As a result, comparing with 2D technology based /14/$ IEEE

2 wire TSV Motion Estimation Processor dummy silicon substrate Memory package substrate F2F bonding pads Fig. 1. Side view of the stacked dies MEP, the number of input/output (IO) pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation results show that the power consumption of the whole design is 64.85mW and the max bandwidth is 14.06GB/s, which is much better compared to the state-of-the-art works. II. ARCHITECTURE DESIGN A. 2-Die Stacked 3D Architecture Fig. 1 shows the side view of the stacked dies. Two dies (MEP and memory) with same size are stacked face to face. MEP die is put on the top because of the following considerations. Firstly, all the IO cells are in MEP die, and are connected with the landing pads on the backside of the MEP die (the upper surface of the 3D chip) by TSV technology. The landing pads are connected with the lead by wire bonding. Secondly, the MEP consumes more power than the memory so that the MEP die generated more heat than the memory die. Thus, a better cooling can be provided for MEP on top die. Based on this design,io pins are not needed for memory die since all the data transmission and power delivery in memory die are through F2F bonding pads. Therefore, without the limitation of IO pins, 128/256 bit width IO memory can be applied in this design. access memory (SRAM) interfaces and schedule MB-level tasks. Two independent memory interfaces are employed to provide connectivity to the memory die. SRAM (A) is a 256 bit interface for buffering reference frame while SRAM (B) is a 128 bit interface for buffering source frame and motion vectors (MVs). Data is stored to SRAM (A) after frame compression [4]. Two caches implemented with on-chip SRAMs are employed for serving reference frame data to IMEC and IMER [3]. The 24KB IMEC cache consists of 16 data memory banks with independent read addresses. Each bank is implemented with a 1R1W SRAM of 256x48bits. The 512KB IMER cache is also composed of 16 data memory banks. Each bank is implemented with a 1RW SRAM with 2048x128bits. The MEP can provide a max throughput of 1.59Gpixels/s. Therefore, real-time 720p@60fps video encoding can be supported at 8MHz. C. Memory Architecture The MEP requires two memories for data access, so 2 memories are designed in this work. The memory is composed of many normal SRAM blocks. With the limitation of the chip size and the big size of SRAM blocks, the capacity is limited. Memory (A) is designed to be 14.25Mb because one 720p frame requires 7.032Mb memories and two reference frames are stored in memory (A). Memory (B) is designed to be 8Mb because one source frame and some MVs are stored in Memory (B). Fig. 3(a) shows the block diagram of memory (A) buffering reference frame. It consists of three 4Mb banks and one 2.25Mb bank. Eight 32bit 512Kb sub-banks which are in a 4Mb bank are combined together to generate a 256 bit width memory bank. The small 2.5Mb bank including four 64b B. MEP Architecture The top-level block diagram of MEP is shown in Fig. 2. Based on our previous work [3], the MEP contains a hierarchical integer motion estimation (IME) component and a fractional motion estimation (FME) component. The IME component is separated into an IME coarse search engine (IMEC) and an IME refinement search engine (IMER). IMEC, IMER and FME work in parallel in an MB-level pipeline and a memory scheduler component issues data requests to static random (a) Block diagram of SRAM memory (A) Sub bank 0 Sub bank 1 Sub bank 2 Sub bank 3 (b) Block diagram of SRAM memory (B) Fig. 2. Top-level block diagram of MEP Fig. 3. Architecture of memory

3 Controller A Controller B Processor netlist SDC file Processor def file Floor plan (manually) verification Memory scheduler Memory netlist SDC file Power/ground network generation TSV & F2F pads placement (manually) Auto placement & routing CTS, global/detail routing Fix violations Insert decap/fill cells Memory A: reference frame buffer Memory B: source frame buffer Memory def file Fig. 5. Backend design flow ME processor Fig. 4. Architecture of memory controller 512Kb sub-banks and two 128b 128Kb sub-banks is also a 256 bit width memory bank. The 4 banks share the same data bus while all sub-banks share the same address bus. Fig. 3(b) shows the block diagram of memory (B) buffering source frame and MVs. It consists of four 2Mb banks. Each 2Mb bank contains four 32b 512Kb sub-banks making up a 128 bit-width memory bank. These 4 banks share another data bus and all sub-banks in memory (B) share another address bus. To reduce the power consumption of the memory die, all memory banks will switch to standby mode automatically until there is data access on the corresponding bank. Benefited from this approach, 13.89% power is saved. Table I summarizes the specification of these 2 memories. The address width of both two memories is 16bit. The synthesis results show that the memory die can run at 300MHz. So the max bandwidth can be up to 14GB/s. TABLE I. Specification of memories Memory (A) Memory (B) Memory type SRAM SRAM Capacity 14.25Mb 8Mb Bit-width Address Capacity of sub-bank 512Kb(I),512Kb(II),128Kb 512Kb Technology file Timing library Physical library D. Architecture of Memory Controller Double-data-rate (DDR) memory controller is integrated in the original MEP [3]. In this work, a novel SRAM memory controller is designed to take the place of the DDR memory controller. There are two main functions of the memory controller. Firstly, it can Control the data transmission between MEP and the two memories. Moreover, it is capable of controlling the timing of MEP and the two memories. The novel memory controller includes 2 independent controllers (controller A and B) as shown in Fig. 4. It responds the data access requests from memory scheduler in MEP. Controller A undertakes the data transmission between memory A and MEP while memory B and MEP are connected by controller B. Both two memories are compatible to the burst mode whose burst length is 8. There are some other benefits from this design. Firstly, all the interfaces between MEP die and memory dies are included in this module. As long as we need to change the interfaces, we only need to modify this module. Secondly, the MEP can be integrated into this design easily. III. 3D PHYSICAL DESIGN In this section, we will introduce the proposed 3D physical design. Design flow is also introduced in [9], but cell definition is not included. We firstly define F2F pad, TSV by modifying library exchange format (LEF) file and timing library. And then, floor plan of the memory die and the MEP die, F2F pads and TSVs placement, and power network are presented in this section. A. Backend Design Flow Fig. 5 shows the backend design flow. The net list file and timing constraint file which are generated in front end design are imported to the EDA tool. Cadence encounter is used in backend design. The MEP die and the memory die run the backend design respectively. Thus, we need to separate the generated net list into 2 net list files before the beginning of backend design. Also we need to prepare many files including 65nm technology file, timing library, physical library, etc. before beginning. In backend design flow, we optimize the floor plan so that the EDA tools can get good result in subsequent steps such as placement, clock tree synthesis (CTS) and routing. After floor plan, power network needs to be designed. Even though this is a low frequency low power 3DLSI design, a strong power network is built to ensure the power delivery. Thirdly, TSV and F2F pads are placed manually. TSV is used in IO area for connecting IO cell and landing pad. Consequently, TSV placement is only run in MEP die. The rest of steps can be done automatically by EDA tools. In step of auto routing, some special settings are done to reserve the top metal layer for F2F bonding. B. F2F Pad and TSV Definitions The side view of the defined TSV is shown in Fig. 6(a). The diameter of TSV is 2um while the diameter of the landing (a) (b) Fig. 6. (a) Side view of TSV, (b) Shape of F2F pad

4 Sub bank 0 in SRAM (B) share low 32 bit data bus Bank 0 0 Bank 1 0 Bank 2 0 Bank 0 1 Bank 1 1 Bank 2 2 Bank 2 1 Bank 3 1 Bank 0 2 Bank 1 2 Bank 0 3 Blocks belonging to SRAM (B) Bank 1 3 Triangle that indicates the orientation of the block and the locations of the pins in the block Bank 2 3 Bank 3 3 Bank 3 0 Bank 3 2 Bank 3 3 The blocks belonging to SRAM (A) are placed together Bank 0 1 Bank 1 1 Bank 2 1 Bank 3 1 Bank 0 3 Bank 1 3 Bank 2 3 Bank 0 5 Bank 1 5 Bank 2 5 Bank 0 7 Bank 1 7 Bank 2 7 Fig. 9. (a) Locations of the F2F pads, (b) F2F signal pads, (c) F2F P/G pads Fig. 7. Floor plan of the memory die pad on the first metal layer is 5um. A large landing pad allows a large misalignment of TSV, so that it can improve the yield. Fig. 6(b) illustrates the shape of the customized F2F pad. The diameter of the F2F pad is 3.4um and the F2F pad has 2 pins. The one on the top metal layer is used for connecting the other die while another one on the low metal layer is used for connecting the signal, power or ground (P/G). C. Floor Plan of Memory Die Both memory A and memory B are integrated in the memory die. Memory B includes 16 memory blocks while Memory A includes 30 memory blocks, i.e. there are 46 available memory blocks in total. In addition, a backup block is set in memory die. These 47 blocks are placed in a 4384um by 4640um core area as shown in Fig. 7. To minimize the chip size, the blocks are placed as close as possible. Floor plan is a key step in backend design flow. It will affect the auto placement and routing results greatly and directly. Several ideas are proposed to optimize the floor plan of memory die. Firstly, to minimize the wire length, the blocks, which share the same address bus and data bus, are lumped together. As described in section II.C, since all the banks from same SRAM (SRAM A or B) share the address bus, placing these banks together can greatly reduce the wire length. As shown in Fig. 7, the blocks covered by the white box are placed together since all the blocks are belonged to SRAM A and share address bus. Secondly, the triangle in the corner of the block indicates the orientation of the block and the locations of the pins of the block. The location and the order of the pins in a block are fixed. But the orientation of the block can be set by user. By making the pins of each block as close as possible and in the same order, the routing congestion can be reduced. Finally, within the SRAM (SRAM A or B), the blocks which share the same part of data bus are put together to reduce the length of the routing wire. As described in section II.C, E.g. the 4 blocks covered by the red box in Fig. 7 are the sub-bank 0 of each bank in SRAM B, and they share the same low 32bit data bus, so they neighbor with each other. Consequently, after optimizing the floor plan, the total routing wire length is reduced by more than 50%. D. F2F Pads and TSVs Placement In this design, TSV is used in IO area of MEP die. Fig. 8 shows the TSVs inserted in the location of the IO pads. To improve the yield, redundant TSVs (32 per IO pad) are placed to connect one IO pad. The pitch of the redundant TSV is 10um. There are 10 input cells, 14 output cells and 32 P/G cells in processor die, i.e., 56 IO pads. So the total number of TSV is Table II lists the TSV parameters. TABLE II. TSV parameters Diameter 2um Pitch 10um Depth 6um # per IO pad 32 Total number 1792 The locations of the F2F pads are decided by the floor plan of the memory die, as shown in Fig. 9(a). The F2F signal pads are placed in the white boxes where the pins of the memory blocks are gathered nearly in. The order of F2F signal pads is the same as the pins in the blocks, so that routing congestion can be reduced. Fig. 9(b) shows the F2F signal pads and the pitch is 5um. There are 803 F2F signal pads in total. The F2F P/G pads are located on the core power ring and Fig. 8. TSVs inserted in an IO pad Fig. 10. Floor plan of MEP die

5 enclosed with the red boxes. The enlarged view of F2F P/G pads is shown in Fig. 9(c). The pitch of the F2F P/G pad is 10um and the number of F2F P/G pads is 500/500. Table III lists the F2F pad parameters in one die. TABLE III. Diameter Pitch Total number F2F pad parameters 3.4um Signal P/G 5um 10um Signal 803 Power 500 Ground 500 E. Floor Plan of Processor Fig. 10 shows the floor plan of MEP die. Since the locations of the F2F pads are decided by memory die, the floor plan of MEP is optimized based on the fixed F2F pads. As described in section II.B, the IMEC cache is composed of 16 memory banks and the IMER cache also consists of 16 memory banks. Each bank is composed of 2 RAM blocks. In order to reduce the routing wire, these 2 blocks are put together. 2.2M logic gates and 72 cache blocks are placed in a 3340um by 3400um core area. Blocks of IMER cache are placed in the bottom while the blocks of IMEC cache are placed in the top. The blocks are placed from periphery to interior with proper orientation. Compared to the floor plan automatically generated by encounter, the routing wire length is reduced by 13.4%. The IO cells are mainly placed in the left and right side of the IO area since the top and the bottom sides are occupied by F2F P/G pads. There are only 24 control signal cells and 32 P/G cells in the processor die because most of pins connecting to memory die are replaced by the F2F signal pads. Compared to [3], the number of IO pin is reduced by 77%. F. Power Network A strong power delivery network ensures reliable operation of circuits on a chip, especially in a 3D IC. Fig. 11 shows the power network of the processor die. The core area is surrounded by a wide P/G core ring connecting inside and outside. Inside the core area, power rails which connect to the power ring horizontally supply power to the standard cells. Furthermore, the power stripes, which connect to the power ring and power rails vertically, are set to reduce the IR-drop. To enhance the power supply to the RAM blocks, block rings are also added, which are not shown in the figure. The F2F P/G pads are used for power delivering from MEP die to the memory die, and they are connected to the power ring directly. The power network of the memory die is similar to the processor die, except that there is no P/G cell and the locations of the F2F P/G pads are on the power ring. So the power network of the memory die is not introduced again. IV. SIMULATION RESULTS AND COMPARISON The proposed architecture is synthesized with synopsys design-compiler by using 65 G standard cell library. And then, cadence encounter is used in backend design including floor plan, power network generation, TSV and F2F placement, CTS, auto placement and routing, etc. Fig. 12 shows the layout of the MEP die, the memory die, and the physical characteristic of the whole design is summarized in table IV. The simulations are based on these layouts. Since this is a low frequency and low power design, much verification such as signal integrity (SI) analysis and thermal simulation are not necessary. The result of the 3D power analysis and 3D IR-drop simulation are shown in the following parts. TABLE IV. Physical characteristic of this design Process technology 65nm Chip size 5000um x 5000um Core size Processor die Memory die Frequency@voltage # of TSV um x 3400um 4384um x 4640um 8MHz@1.2V # of F2F signal/p/g pad 803/500/500 #of signal/pg IO cell 24/32 A. 3D power analysis 3D power analysis is performed by cadence encounter Power system (EPS). Not only the physical library, timing library, technology file, but also the net list file, design exchange format (DEF) file, standard delay format file, etc. are imported into EPS. Then, the analysis method is set to static and the corner mode is set to normal (1.2V at 25 ). The frequency is read from the timing constraint file and the toggle rate is set. Finally, EPS reports the result that the total power is 64.85mW. The power of the processor die and memory die is 37.67mW and 27.18mW respectively. B. 3D IR-Drop simulation IR-drop simulation is also done by EPS. Firstly, a cell list is done to create power grid library. Then the analysis method is IO cell F2F pad Power ring Ground ring Fig. 11. Power network of the processor die Fig. 12. Layout of processor die (left) and memory die (right)

6 set to static mode, the temperature is set to 25 and the locations of the source power are set. Here the source power of the processor die is the power cell and the source power of the memory die is the F2F power pad. Thirdly, the result files of power analysis are imported. After finishing these steps, EPS analyzes the IR-drop automatically. The worst IR-drop of the processor die is 5.478mV while the maximum IR-drop of the memory die is only 1.555mV. Note that the voltage of the power net is 1.05V, so there are plenty of margins for the 3D stacked case. C. Comparison Here we do not compare this design with [1] and [2] for their different functions. Ref. [1] is a video decoder which is without MEP. Ref. [2] is a whole encoder including not only MEP but also other parts. An MEP with system-in-silicon architecture is introduced in [12], whose core power and memory power is 2383mW and 190mW respectively. The total power is 2573mW. After normalization, the power and energy efficiency are 432.5mW and 6.952nJ/pixel respectively. TABLE V. Memory type Design specification and power comparison [12] This design System-in-Silicon DRAM / on chip 3D stacked memory / on chip Technology 180nm/110nm 65nm Frequency 200MHz/25MHz@1.8V 8MHz@1.2V Throughput 1080p@30fps 720p@60fps Core power Norm. core power a Memory power Norm. memory power 2383mW 382.5mW 190mW 50mW 37.67mW 27.18mW Norm. total power 432.5mW 64.85mW Energy efficiency b 6.952nJ/pixel 1.173nJ/pixel a. Power normalized to 65nm (P65 = P180 / 6.23 = P110 / 3.8) b. Energy efficiency = Norm. total power / throughput TABLE VI. Bandwidth comparison [9] [6] This design Footprint 12.3mm x 21.8mm - 5mm x 5mm # of tier/die Max frequency 133MHz - 300MHz Working frequency 60MHz 200MHz 8MHz Data width x Max bandwidth 8.5GB/s 12.8GB/s 14GB/s Table V shows the specification of this design and the power comparison to [12]. Benefit from the algorithm optimization, the MEP can process 9 pixels per cycle in average, so that it can encode 720p@60fps video sequences with 2 reference frames at 8MHz. Under this frequency, the power consumption of the MEP die and the memory die is as shown. Benefit from the frequency reduction, and 3D integration, the energy efficiency of this design is 1.173nJ/pixel, which is only one sixth of [12]. Bandwidth comparison is given in table VI. A 3D implementation of H.264 encoder is introduced in [9], whose max bandwidth is 8.5GB/s. The max bandwidth of this design is 14GB/s, which are about 1.64 times of [9]. Also the max bandwidth of this design is a little higher than the wide IO single date rate memory [6], since the bandwidth of [6] is 12.8GB/s. V. CONCLUSION In this paper, a MEP with 3D stacked memory architecture is proposed to reduce the memory power and provide higher bandwidth. By adding F2F pad and TSV definitions, 2D EDA tools are extended to support the proposed 3D stacking architecture. Furthermore, a novel memory controller is designed to control the data transmission and the timing between memory die and MEP die. Finally, 3D physical design is completed for the whole system including floor plan optimization of two dies, TSV/F2F placement, power network generations, etc. As a result, comparing with 2D technology based MEP, the number of IO pins is reduced by 77%. After optimizing the floor plan of the processor die and memory die, the routing wire length is reduced by 13.4% and 50% respectively. The simulation result show that the power consumption and the max bandwidth of the whole design is 64.85mW and 14GB/s respectively, which is much better compared to the state-of-the-art. REFERENCES [1] Sze, Vivienne, et al. "A 0.7-v 1.8-Mw H. 264/AVC 720p Video Decoder". Solid-State Circuits, IEEE Journal of (2009): [2] Yu-Kun Lin, et al. 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