Asynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus
|
|
- Erica Ryan
- 6 years ago
- Views:
Transcription
1 Asynchronous on-chip Communication: Explorations on the Intel PXA27x Peripheral Bus Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley 1 Slide 1
2 Introduction 2 Slide 2
3 Intel PXA27x Processor Design General Purpose I/O (GPIO) RTC OS Timers 4x PWM Interrupt 3x SSP USIM I 2 S AC 97 Std UART Full UART Bluetooth UART Fast Infrared I 2 C USB Client BB Interface Keypad Interface MMC/SC/SDIO Memory Stick USB On-The-Go 32.7 khz khz / 13 MHz 13 / 26 MHz khz / 13 MHz /104 MHz 13 MHz / 26 MHz 48 MHz 2 to 12 MHz MHz 14.7 MHz 14.7 MHz 14.7 MHz 48 MHz 33.3 MHz 48 MHz 48 MHz 32 khz 20 / 25 MHz to 20 MHz MHz Peripheral Bus (PB) 13 MHz / 26 MHz DMA Controller & Bridge Quick Capture Interface Intel Wireless MMX TM Power Management / Clock Control Internal SRAM LCD Controller System Bus 104/133/208 MHz Intel Xscale Core Debug Controller khz Osc USB Host Controller 13 MHz Osc Memory Controller Address & Data Variable Latency I/O Control PC Card / CompactFlash Control Dynamic Memory Control Static Memory Control Slide 3
4 Intel PXA27x Processor Design General Purpose I/O (GPIO) RTC OS Timers 4x PWM Interrupt 3x SSP USIM I 2 S AC 97 Std UART Full UART Bluetooth UART Fast Infrared I 2 C USB Client BB Interface Keypad Interface MMC/SC/SDIO Memory Stick USB On-The-Go 32.7 khz khz / 13 MHz 13 / 26 MHz khz / 13 MHz /104 MHz 13 MHz / 26 MHz 48 MHz 2 to 12 MHz MHz 14.7 MHz 14.7 MHz 14.7 MHz 48 MHz 33.3 MHz 48 MHz 48 MHz 32 khz 20 / 25 MHz to 20 MHz MHz Peripheral Bus (PB) 13 MHz / 26 MHz DMA Controller & Bridge Quick Capture Interface Intel Wireless MMX TM Power Management / Clock Control Internal SRAM LCD Controller System Bus 104/133/208 MHz Intel Xscale Core Debug Controller khz Osc USB Host Controller 13 MHz Osc Memory Controller Address & Data Variable Latency I/O Control PC Card / CompactFlash Control Dynamic Memory Control Static Memory Control Slide 4
5 Async Peripheral Bus Team General Purpose I/O (GPIO) RTC OS Timers 4x PWM Interrupt 3x SSP USIM I 2 S AC 97 Std UART Full UART Bluetooth UART Fast Infrared I 2 C USB Client BB Interface Keypad Interface MMC/SC/SDIO Memory Stick USB On-The-Go 32.7 khz khz / 13 MHz 13 / 26 MHz khz / 13 MHz /104 MHz 13 MHz / 26 MHz 48 MHz 2 to 12 MHz MHz 14.7 MHz 14.7 MHz 14.7 MHz 48 MHz 33.3 MHz 48 MHz 48 MHz 32 khz 20 / 25 MHz to 20 MHz MHz Peripheral Bus (PB) 13 MHz / 26 MHz DMA Controller & Bridge Quick Capture Interface Intel Wireless MMX TM Power Management / Clock Control SoC Flow Development Internal SRAM LCD Controller System Bus 104/133/208 MHz Intel Xscale Core Debug Controller Andy & Jin-Jer khz Osc USB Host Controller 13 MHz Osc Memory Controller Address & Data Extreme Low-Power product Design Mark & Mark Fullerton Asynchronous Tools Marly & Andrew Variable Latency I/O Control PC Card / CompactFlash Control Dynamic Memory Control Asynchronous Fabrics John John & Dave Static Memory Control Slide 5
6 Objectives Build an Asynchronous NoC in a Synchronous SoC flow Assess design tradeoffs from Product Developer s Perspective Identify gaps in current design capabilities Slide 6
7 What do SoC Developers worry about? Inflexible product-introduction cycles Shorter product lead times & product life times Growing Complexity Design & Manufacturing rules Product & System design Slide 7
8 What do SoC Developers want from their flow? Fast integration and validation of IP Minimal IP and IP-collateral redesign Modular Design Flows Minimal disruption to their synchronous SoC flow Slide 8
9 Exploration - What we did 9 Slide 9
10 Peripheral Bus Baseline Design General Purpose I/O (GPIO) RTC OS Timers 4x PWM Interrupt 3x SSP SSP USIM I 2 S AC 97 Std UART Full UART Bluetooth UART Fast Infrared I 2 C USB Client BB Interface Keypad Interface 32.7 khz khz / 13 MHz 13 / 26 MHz khz / 13 MHz /104 MHz 13 MHz / 26 MHz 48 MHz 2 to 12 MHz MHz 14.7 MHz 14.7 MHz 14.7 MHz 48 MHz 33.3 MHz 48 MHz 48 MHz 32 khz Peripheral Bus (PB) 13 MHz / 26 MHz DMA Controller & Bridge 3 representative Bus Slaves: SSP UART Baseband Peripheral Bus Fabric Bus Master DMA Controller MMC/SC/SDIO Memory Stick USB On-The-Go 20 / 25 MHz to 20 MHz MHz Slide 10
11 Peripheral Bus Synchronous Interface SSP UART Std UART DMAC BB BB Interface PB clock domain SSP UART BB DMAC clock domains synchronizer Slide 11
12 Peripheral Bus Asynchronous Interface SSP UART Std UART Synchronizing Synchronizing 3 Async Interface Adaptations Synchronizing Adapter no Master/Slave redesign simplest, adds synchronizers DMAC BB Interface Asynchronous clock Pausible Clock Adapter no Master/Slave redesign locally generated interface clock no extra synchronizers Pausible Clock Asynchronous Interface requires redesign (UART) removes synchronizers to PB Slide 12
13 Transaction Level Testing 13 Slide 13
14 Transaction-Level Testing (TLT) Test scope Functional coverage Stress & Error Conditions Multiple Use Models & Traffic Scenarios Peripheral, Subsystem, and System Level How? Specify Transactions Automatic Protocol Adherence and Results Checking Strengths Test Re-use at Peripheral, Subsystem & System level Test Re-use for Synchronous & Asynchronous Facilitated abstraction to higher-level traffic patterns AND HENCE: Highly portable & powerful!!! Slide 14
15 EDA Flow & Network Construction 15 Slide 15
16 Scope Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Intel Design Entry Intel PXA27x IP, text Build 5 representative Synchronous & Asynchronous top-level networks Synthesis & Netlist Integration Intel Stdcell / SRAM libraries RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Evaluate Functionality Timing & Realistic Power Metrics Assess Asynchronous Design & EDA Flow integration issues Slide 16
17 Silístix Design Entry & Asynchronous Network Construction Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Intel Design Entry Intel PXA27x IP, text Enter high-level description of self-timed NoC topology Synthesis & Netlist Integration Intel Stdcell / SRAM libraries RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Generate hierarchical, structural Verilog netlists Modify UART PB-facing logic to attach directly to the asynchronous fabric Slide 17
18 Intel Design Entry & Network Construction Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Intel Design Entry Intel PXA27x IP, text Typical Low-Power SoC flow uses commercial EDA tools used for wide product & process range (180, 130, 90nm etc.) Synthesis & Netlist Integration Intel Stdcell / SRAM libraries RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Slide 18
19 Intel Design Entry & Network Construction Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Synthesis & Netlist Integration Intel Stdcell / SRAM libraries Intel Design Entry Intel PXA27x IP, text Our Usage Model: Synthesize synchronous blocks at 2 PVT corners 1M-gate Wire-load model to match original 27-peripheral PB No clock-gating, scan-insertion RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Import Asynchronous blocks Stitch top-level networks Slide 19
20 Evaluation Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Intel Design Entry Intel PXA27x IP, text Validate SoC flow usage Gate-to-gate FV For key synchronous blocks Synthesis & Netlist Integration Intel Stdcell / SRAM libraries RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Slide 20
21 Evaluation Silístix Design Entry Async network IP, text Async Network Generation Silístix tools Intel Design Entry Intel PXA27x IP, text Dynamic Simulation Functionality, Timing & Power Unit-delay models Back-annotation, 2 PVT corners Synthesis & Netlist Integration Intel Stdcell / SRAM libraries RTL & Gate-level Validation functionality, latency, throughput Gate-level Power Simulation Metric (Area) Analysis Intel Stdcell / SRAM models Intel & Formal Verification to validate PB flow scripting Typical PB Traffic scenarios 0.5MB/s (PB idle) 1MB/s (PB Normal) 10MB/s (PB max) Netlist-based Metric collection Slide 21
22 Top-Level Networks Small test cases for debug: sync_1i3t, async_1i3t 1x (UART-sync, BB, SSP), 1x (UART-async, BB, SSP) Primary test cases for Async-Sync comparisons: async_127t 9x (UART-async, BB, SSP) UART-sync + Synchronizing Adapter substituted for Metrics sync_1i27t 9x (UART-sync, BB, SSP) + up-scaled PB_MUX Extra test case to check scaling properties: async_1i30t 10x (UART-async, BB, SSP) Slide 22
23 Results 23 Slide 23
24 Active Power x Traffic: Async Fabric Active Power (uw) % async_1i3t async_1i27t async_1i30t 0.5 M B /s M B / s M B / s Async Fabric Power SCALES with traffic Slide 24
25 Active Power x Traffic: UART Active Power (uw) MB/s 1 MB/s 10 MB/s UA RT-sync UA RT-async Reduction 71% 70% 72% 70% Lower Power for Async Redesign NOTE Async power scaling not visible for given TLT Slide 25
26 Active Power x Data: async_1i27t Active Power (mw) Total PB UART SSP BB 0.5 M B /s M B / s M B / s Synchronous Peripherals dominate the Power spectrum REASON: A small piece of Asynchronous in a BIG synchronous World MEANS frequent interfacing AND HENCE smaller up-scale of advantages Slide 26
27 Metrics: Full Top-Level PB System Ratio to Synchronous Cells Gates (NAND2) Raw Cell A rea sync_1i27t async_1i27t Increase 26% 17% 15% Adapter overhead is small at the PB system level ~15% raw area... add in WIRES: 66% fewer wires which should result in: better routing flexibility better layout density Slide 27
28 Interface Adaptation Metrics Ratio to Asynchronous Interface Cells Gates Raw Area Latency All 3 adaptation schemes worked! Asynchronous Synchro nizing P ausible Clock KEY learning is HERE... Slide 28
29 Latency and bandwidth PB had no latency requirement, but every transfer was 2 cycles, with no transfer overlapping or pipelining all latency directly limits bandwidth. PB bus protocol requires 2 cycles per transfer Self-timed time interval Clocked time interval (one cycle) Slide 29
30 Latency and bandwidth 1 rsp transfer PB had no latency requirement, but every transfer was 2 cycles, with no Client DMA/bridge transfer overlapping or pipelining all latency directly limits bandwidth. 1 cmd transfer PB bus protocol requires 2 cycles per transfer Self-timed time interval Clocked time interval (one cycle) Slide 30
31 Latency and bandwidth 2 protocol clocking 1 rsp transfer 2 rsp synchronization PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. 2 - cmd synchronization 1 cmd transfer 1 cmd setup PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Self-timed time interval Clocked time interval (one cycle) Slide 31
32 Latency and bandwidth 2 protocol clocking 1 rsp transfer 2 rsp synchronization PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. 1 cmd transfer 1 cmd setup PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Pausible clock adapter ~ 7 cycles Removes 2 cycles of command synchronization Self-timed time interval Clocked time interval (one cycle) Slide 32
33 Latency and bandwidth 1 rsp transfer 2 rsp synchronization PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. 1 cmd transfer 1 cmd setup PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Pausible clock adapter ~ 7 cycles Removes 2 cycles of command synchronization Async peripheral interface ~ 5 cycles Removes ~2 cycles protocol clocking overhead Self-timed time interval Clocked time interval (one cycle) Slide 33
34 Latency and bandwidth 1 rsp transfer 2 rsp synchronization PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. 1 cmd transfer PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Pausible clock adapter ~ 7 cycles Removes 2 cycles of command synchronization Async peripheral interface ~ 5 cycles Removes ~2 cycles protocol clocking overhead Logic optimization ~ 4 cycles Bus arbitration cycle unnecessary for PB protocol Self-timed time interval Clocked time interval (one cycle) Slide 34
35 Latency and bandwidth 1 rsp transfer PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. 1 cmd transfer PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Pausible clock adapter ~ 7 cycles Removes 2 cycles of command synchronization Async peripheral interface ~ 5 cycles Removes ~2 cycles protocol clocking overhead Logic optimization ~ 4 cycles Bus arbitration cycle unnecessary for PB protocol Async bridge ~ 2 cycles Removes 2 cycles of response synchronization Self-timed time interval Clocked time interval (one cycle) Slide 35
36 Latency and bandwidth PB had no latency requirement, but every transfer was 2 cycles, with no Client Network Network Adapter Adapter DMA/bridge transfer overlapping Gateway or pipelining all latency Gateway directly limits bandwidth. Self-timed time interval AND 1 rsp transfer 1 cmd transfer PB bus protocol requires 2 cycles per transfer Synchronizing adapter ~ 9 cycles Latency limits bandwidth - only 90% of target Pausible clock adapter ~ 7 cycles Removes 2 cycles of command synchronization Async peripheral interface ~ 5 cycles Removes ~2 cycles protocol clocking overhead Logic optimization ~ 4 cycles Bus arbitration cycle unnecessary for PB protocol Async bridge ~ 2 cycles Removes 2 cycles of response synchronization Future: Concurrent command&response ~1 cycle 200% (2x improvement) of target Clocked time interval (one cycle) Slide 36
37 Key Learnings & Future Directions Partition with NoC in Mind Minimize the number of timing domain crossings Partition between NoC, Peripherals & Interface logic Encapsulate asynchronous NoCs to simplify integration with mostlysynchronous tools Take advantage of NoC Strengths! Exploit the layered communication approach Concurrency can dramatically improve throughput & latency Lower IP generation & validation costs Self-timed NoC promotes faster timing closure and lower standby power Employ Transaction Level Test Suites They were invaluable in testing, debugging, and benchmarking our NoCs Enables portable, maintainable, flexible validation suites re-usable at multiple levels of abstraction Real SoC traffic isn t homogeneous, and is much easier to model in a flexible, modular TLT Slide 37
38 Key Learnings & Future Directions It s still a mostly-synchronous SoC world New methods must seamlessly integrate with mostly-synchronous flows Static Timing analysis flows & engines need to be enhanced to better handle complex multi-frequency and asynchronous design content (see SRC investigation by Beerel/Stevens) SoC Developers want flexibility in choosing Power, Latency, Bandwidth and Area Our four-phase 1-hot QDI style was very robust, but a limiting factor in power reduction and achievable bandwidth We see potential benefits in two-phase, single-rail and alternate QDI encodings We expect that additional asynchronous cells and single-rail FIFOs will enable further improvements Slide 38
39 Summary We built an asynchronous NoC in a synchronous SoC flow, today We demonstrated asynchronous NoC advantages We explored a number of tradeoffs We learned lessons & identified areas for further development Slide 39
40 Asynchronous NoC in SoC. Do it. Slide 40
Age nda. Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications
Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications N.C. Paver PhD Architect Intel Corporation Hot Chips 16 August 2004 Age nda Overview of the Intel PXA27X processor
More informationPerformance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models. Jason Andrews
Performance Optimization for an ARM Cortex-A53 System Using Software Workloads and Cycle Accurate Models Jason Andrews Agenda System Performance Analysis IP Configuration System Creation Methodology: Create,
More informationPlace Your Logo Here. K. Charles Janac
Place Your Logo Here K. Charles Janac President and CEO Arteris is the Leading Network on Chip IP Provider Multiple Traffic Classes Low Low cost cost Control Control CPU DSP DMA Multiple Interconnect Types
More informationASYNC Rik van de Wiel COO Handshake Solutions
ASYNC 2006 Rik van de Wiel COO Handshake Solutions Outline Introduction to Handshake Solutions Applications Design Tools ARM996HS Academic Program Handshake Solutions Started as research project in Philips
More informationModeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces
Modeling Performance Use Cases with Traffic Profiles Over ARM AMBA Interfaces Li Chen, Staff AE Cadence China Agenda Performance Challenges Current Approaches Traffic Profiles Intro Traffic Profiles Implementation
More informationThe CoreConnect Bus Architecture
The CoreConnect Bus Architecture Recent advances in silicon densities now allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripherals formerly attached
More informationApplying the Benefits of Network on a Chip Architecture to FPGA System Design
white paper Intel FPGA Applying the Benefits of on a Chip Architecture to FPGA System Design Authors Kent Orthner Senior Manager, Software and IP Intel Corporation Table of Contents Abstract...1 Introduction...1
More informationEffective System Design with ARM System IP
Effective System Design with ARM System IP Mentor Technical Forum 2009 Serge Poublan Product Marketing Manager ARM 1 Higher level of integration WiFi Platform OS Graphic 13 days standby Bluetooth MP3 Camera
More informationIMPROVES. Initial Investment is Low Compared to SoC Performance and Cost Benefits
NOC INTERCONNECT IMPROVES SOC ECONO CONOMICS Initial Investment is Low Compared to SoC Performance and Cost Benefits A s systems on chip (SoCs) have interconnect, along with its configuration, verification,
More informationL2: Design Representations
CS250 VLSI Systems Design L2: Design Representations John Wawrzynek, Krste Asanovic, with John Lazzaro and Yunsup Lee (TA) Engineering Challenge Application Gap usually too large to bridge in one step,
More informationMulti-core microcontroller design with Cortex-M processors and CoreSight SoC
Multi-core microcontroller design with Cortex-M processors and CoreSight SoC Joseph Yiu, ARM Ian Johnson, ARM January 2013 Abstract: While the majority of Cortex -M processor-based microcontrollers are
More informationSoC Communication Complexity Problem
When is the use of a Most Effective and Why MPSoC, June 2007 K. Charles Janac, Chairman, President and CEO SoC Communication Complexity Problem Arbitration problem in an SoC with 30 initiators: Hierarchical
More information101-1 Under-Graduate Project Digital IC Design Flow
101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL
More informationThe RM9150 and the Fast Device Bus High Speed Interconnect
The RM9150 and the Fast Device High Speed Interconnect John R. Kinsel Principal Engineer www.pmc -sierra.com 1 August 2004 Agenda CPU-based SOC Design Challenges Fast Device (FDB) Overview Generic Device
More informationHotChips An innovative HD video and digital image processor for low-cost digital entertainment products. Deepu Talla.
HotChips 2007 An innovative HD video and digital image processor for low-cost digital entertainment products Deepu Talla Texas Instruments 1 Salient features of the SoC HD video encode and decode using
More informationEffective Verification of ARM SoCs
Effective Verification of ARM SoCs Ron Larson, Macrocad Development Inc. Dave Von Bank, Posedge Software Inc. Jason Andrews, Axis Systems Inc. Overview System-on-chip (SoC) products are becoming more common,
More informationDigital Signal Processor Core Technology
The World Leader in High Performance Signal Processing Solutions Digital Signal Processor Core Technology Abhijit Giri Satya Simha November 4th 2009 Outline Introduction to SHARC DSP ADSP21469 ADSP2146x
More informationThe S6000 Family of Processors
The S6000 Family of Processors Today s Design Challenges The advent of software configurable processors In recent years, the widespread adoption of digital technologies has revolutionized the way in which
More informationThe Challenges of System Design. Raising Performance and Reducing Power Consumption
The Challenges of System Design Raising Performance and Reducing Power Consumption 1 Agenda The key challenges Visibility for software optimisation Efficiency for improved PPA 2 Product Challenge - Software
More informationSONICS, INC. Sonics SOC Integration Architecture. Drew Wingard. (Systems-ON-ICS)
Sonics SOC Integration Architecture Drew Wingard 2440 West El Camino Real, Suite 620 Mountain View, California 94040 650-938-2500 Fax 650-938-2577 http://www.sonicsinc.com (Systems-ON-ICS) Overview 10
More informationFlexRay The Hardware View
A White Paper Presented by IPextreme FlexRay The Hardware View Stefan Schmechtig / Jens Kjelsbak February 2006 FlexRay is an upcoming networking standard being established to raise the data rate, reliability,
More informationIntellectual Property Macrocell for. SpaceWire Interface. Compliant with AMBA-APB Bus
Intellectual Property Macrocell for SpaceWire Interface Compliant with AMBA-APB Bus L. Fanucci, A. Renieri, P. Terreni Tel. +39 050 2217 668, Fax. +39 050 2217522 Email: luca.fanucci@iet.unipi.it - 1 -
More informationFujitsu SOC Fujitsu Microelectronics America, Inc.
Fujitsu SOC 1 Overview Fujitsu SOC The Fujitsu Advantage Fujitsu Solution Platform IPWare Library Example of SOC Engagement Model Methodology and Tools 2 SDRAM Raptor AHB IP Controller Flas h DM A Controller
More informationAT-501 Cortex-A5 System On Module Product Brief
AT-501 Cortex-A5 System On Module Product Brief 1. Scope The following document provides a brief description of the AT-501 System on Module (SOM) its features and ordering options. For more details please
More informationECE 551 System on Chip Design
ECE 551 System on Chip Design Introducing Bus Communications Garrett S. Rose Fall 2018 Emerging Applications Requirements Data Flow vs. Processing µp µp Mem Bus DRAMC Core 2 Core N Main Bus µp Core 1 SoCs
More informationOCB-Based SoC Integration
The Present and The Future 黃俊達助理教授 Juinn-Dar Huang, Assistant Professor March 11, 2005 jdhuang@mail.nctu.edu.tw Department of Electronics Engineering National Chiao Tung University 1 Outlines Present Why
More informationTransaction level modeling of SoC with SystemC 2.0
Transaction level modeling of SoC with SystemC 2.0 Sudeep Pasricha Design Flow and Reuse/CR&D STMicroelectronics Ltd Plot No. 2 & 3, Sector 16A Noida 201301 (U.P) India Abstract System architects working
More informationChapter 6 Storage and Other I/O Topics
Department of Electr rical Eng ineering, Chapter 6 Storage and Other I/O Topics 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Feng-Chia Unive ersity Outline 6.1 Introduction 6.2 Dependability,
More informationProduct Technical Brief S3C2440X Series Rev 2.0, Oct. 2003
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003 S3C2440X is a derivative product of Samsung s S3C24XXX family of microprocessors for mobile communication market. The S3C2440X s main enhancement
More informationAchieving UFS Host Throughput For System Performance
Achieving UFS Host Throughput For System Performance Yifei-Liu CAE Manager, Synopsys Mobile Forum 2013 Copyright 2013 Synopsys Agenda UFS Throughput Considerations to Meet Performance Objectives UFS Host
More informationIntelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
More informationAchieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation
Achieving Lightweight Multicast in Asynchronous Networks-on-Chip Using Local Speculation Kshitij Bhardwaj Dept. of Computer Science Columbia University Steven M. Nowick 2016 ACM/IEEE Design Automation
More informationCreating hybrid FPGA/virtual platform prototypes
Creating hybrid FPGA/virtual platform prototypes Know how to use the PCIe-over-Cabling interface in its HAPS-60-based system to create a new class of hybrid prototypes. By Troy Scott Product Marketing
More informationTen Reasons to Optimize a Processor
By Neil Robinson SoC designs today require application-specific logic that meets exacting design requirements, yet is flexible enough to adjust to evolving industry standards. Optimizing your processor
More informationESE Back End 2.0. D. Gajski, S. Abdi. (with contributions from H. Cho, D. Shin, A. Gerstlauer)
ESE Back End 2.0 D. Gajski, S. Abdi (with contributions from H. Cho, D. Shin, A. Gerstlauer) Center for Embedded Computer Systems University of California, Irvine http://www.cecs.uci.edu 1 Technology advantages
More informationThe Design and Implementation of a Low-Latency On-Chip Network
The Design and Implementation of a Low-Latency On-Chip Network Robert Mullins 11 th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 24-27 th, 2006, Yokohama, Japan. Introduction Current
More informationFive Key Steps to High-Speed NAND Flash Performance and Reliability
Five Key Steps to High-Speed Flash Performance and Reliability Presenter Bob Pierce Flash Memory Summit 2010 Santa Clara, CA 1 NVM Performance Trend ONFi 2 PCM Toggle ONFi 2 DDR SLC Toggle Performance
More informationChoosing an Intellectual Property Core
Choosing an Intellectual Property Core MIPS Technologies, Inc. June 2002 One of the most important product development decisions facing SOC designers today is choosing an intellectual property (IP) core.
More informationOptimizing ARM SoC s with Carbon Performance Analysis Kits. ARM Technical Symposia, Fall 2014 Andy Ladd
Optimizing ARM SoC s with Carbon Performance Analysis Kits ARM Technical Symposia, Fall 2014 Andy Ladd Evolving System Requirements Processor Advances big.little Multicore Unicore DSP Cortex -R7 Block
More informationCS152 Computer Architecture and Engineering Lecture 20: Busses and OS s Responsibilities. Recap: IO Benchmarks and I/O Devices
CS152 Computer Architecture and Engineering Lecture 20: ses and OS s Responsibilities April 7, 1995 Dave Patterson (patterson@cs) and Shing Kong (shing.kong@eng.sun.com) Slides available on http://http.cs.berkeley.edu/~patterson
More informationMore on IO: The Universal Serial Bus (USB)
ecture 37 Computer Science 61C Spring 2017 April 21st, 2017 More on IO: The Universal Serial Bus (USB) 1 Administrivia Project 5 is: USB Programming (read from a mouse) Optional (helps you to catch up
More informationModeling and Simulation of System-on. Platorms. Politecnico di Milano. Donatella Sciuto. Piazza Leonardo da Vinci 32, 20131, Milano
Modeling and Simulation of System-on on-chip Platorms Donatella Sciuto 10/01/2007 Politecnico di Milano Dipartimento di Elettronica e Informazione Piazza Leonardo da Vinci 32, 20131, Milano Key SoC Market
More informationBuses. Disks PCI RDRAM RDRAM LAN. Some slides adapted from lecture by David Culler. Pentium 4 Processor. Memory Controller Hub.
es > 100 MB/sec Pentium 4 Processor L1 and L2 caches Some slides adapted from lecture by David Culler 3.2 GB/sec Display Memory Controller Hub RDRAM RDRAM Dual Ultra ATA/100 24 Mbit/sec Disks LAN I/O Controller
More informationEmbedded Systems: Architecture
Embedded Systems: Architecture Jinkyu Jeong (Jinkyu@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu ICE3028: Embedded Systems Design, Fall 2018, Jinkyu Jeong (jinkyu@skku.edu)
More informationFujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02
Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC
More informationProcessor and Peripheral IP Cores for Microcontrollers in Embedded Space Applications
Processor and Peripheral IP Cores for Microcontrollers in Embedded Space Applications Presentation at ADCSS 2010 MESA November 4 th, 2010 www.aeroflex.com/gaisler Presentation outline Microcontroller requirements
More informationOberon M2M IoT Platform. JAN 2016
Oberon M2M IoT Platform JAN 2016 www.imgtec.com Contents Iot Segments and Definitions Targeted Use Cases for IoT Oberon targeted use cases IoT Differentiators IoT Power Management IoT Security Integrated
More informationMarvell PXA3xx (88AP3xx) Processor Family
Cover Marvell PXA3xx (88AP3xx) Processor Family Electrical, Mechanical, and Thermal Functional Specification PXA30x Processor (88AP300, 88AP301, 88AP302, 88AP303) PXA31x Processor (88AP310, 88AP311, 88AP312)
More informationSYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS
SYSTEMS ON CHIP (SOC) FOR EMBEDDED APPLICATIONS Embedded System System Set of components needed to perform a function Hardware + software +. Embedded Main function not computing Usually not autonomous
More informationImplementing Flexible Interconnect Topologies for Machine Learning Acceleration
Implementing Flexible Interconnect for Machine Learning Acceleration A R M T E C H S Y M P O S I A O C T 2 0 1 8 WILLIAM TSENG Mem Controller 20 mm Mem Controller Machine Learning / AI SoC New Challenges
More informationProduct specification
MJIOT-AMB-03 Product specification 1 MJIOT-AMB-03module appearance 2 目录 1. Product overview...4 1.1 Characteristic... 5 1.2 main parameters...6 1.2 Interface definition... 7 2. appearance and size... 8
More informationImplementing Tile-based Chip Multiprocessors with GALS Clocking Styles
Implementing Tile-based Chip Multiprocessors with GALS Clocking Styles Zhiyi Yu, Bevan Baas VLSI Computation Lab, ECE Department University of California, Davis, USA Outline Introduction Timing issues
More informationProduct Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
More informationEmbedded Systems. 8. Communication
Embedded Systems 8. Communication Lothar Thiele 8-1 Contents of Course 1. Embedded Systems Introduction 2. Software Introduction 7. System Components 10. Models 3. Real-Time Models 4. Periodic/Aperiodic
More informationEE108B Lecture 17 I/O Buses and Interfacing to CPU. Christos Kozyrakis Stanford University
EE108B Lecture 17 I/O Buses and Interfacing to CPU Christos Kozyrakis Stanford University http://eeclass.stanford.edu/ee108b 1 Announcements Remaining deliverables PA2.2. today HW4 on 3/13 Lab4 on 3/19
More informationHardware Design Environments. Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University
Hardware Design Environments Dr. Mahdi Abbasi Computer Engineering Department Bu-Ali Sina University Outline Welcome to COE 405 Digital System Design Design Domains and Levels of Abstractions Synthesis
More informationKeyStone C665x Multicore SoC
KeyStone Multicore SoC Architecture KeyStone C6655/57: Device Features C66x C6655: One C66x DSP Core at 1.0 or 1.25 GHz C6657: Two C66x DSP Cores at 0.85, 1.0, or 1.25 GHz Fixed and Floating Point Operations
More informationSystem Level Design For Low Power. Yard. Doç. Dr. Berna Örs Yalçın
System Level Design For Low Power Yard. Doç. Dr. Berna Örs Yalçın References System-Level Design Methodology, Daniel D. Gajski Hardware-software co-design of embedded systems : the POLIS approach / by
More informationSEMICON Solutions. Bus Structure. Created by: Duong Dang Date: 20 th Oct,2010
SEMICON Solutions Bus Structure Created by: Duong Dang Date: 20 th Oct,2010 Introduction Buses are the simplest and most widely used interconnection networks A number of modules is connected via a single
More informationSimplify System Complexity
1 2 Simplify System Complexity With the new high-performance CompactRIO controller Arun Veeramani Senior Program Manager National Instruments NI CompactRIO The Worlds Only Software Designed Controller
More informationDesign and Test Solutions for Networks-on-Chip. Jin-Ho Ahn Hoseo University
Design and Test Solutions for Networks-on-Chip Jin-Ho Ahn Hoseo University Topics Introduction NoC Basics NoC-elated esearch Topics NoC Design Procedure Case Studies of eal Applications NoC-Based SoC Testing
More information100M Gate Designs in FPGAs
100M Gate Designs in FPGAs Fact or Fiction? NMI FPGA Network 11 th October 2016 Jonathan Meadowcroft, Cadence Design Systems Why in the world, would I do that? ASIC replacement? Probably not! Cost prohibitive
More informationChapter Seven Morgan Kaufmann Publishers
Chapter Seven Memories: Review SRAM: value is stored on a pair of inverting gates very fast but takes up more space than DRAM (4 to 6 transistors) DRAM: value is stored as a charge on capacitor (must be
More informationThe Need for Speed: Understanding design factors that make multicore parallel simulations efficient
The Need for Speed: Understanding design factors that make multicore parallel simulations efficient Shobana Sudhakar Design & Verification Technology Mentor Graphics Wilsonville, OR shobana_sudhakar@mentor.com
More informationV8uC: Sparc V8 micro-controller derived from LEON2-FT
V8uC: Sparc V8 micro-controller derived from LEON2-FT ESA Workshop on Avionics Data, Control and Software Systems Noordwijk, 4 November 2010 Walter Errico SITAEL Aerospace phone: +39 0584 388398 e-mail:
More informationHardware Software Bring-Up Solutions for ARM v7/v8-based Designs. August 2015
Hardware Software Bring-Up Solutions for ARM v7/v8-based Designs August 2015 SPMI USB 2.0 SLIMbus RFFE LPDDR 2 LPDDR 3 emmc 4.5 UFS SD 3.0 SD 4.0 UFS Bare Metal Software DSP Software Bare Metal Software
More informationModule 6: INPUT - OUTPUT (I/O)
Module 6: INPUT - OUTPUT (I/O) Introduction Computers communicate with the outside world via I/O devices Input devices supply computers with data to operate on E.g: Keyboard, Mouse, Voice recognition hardware,
More informationBuses. Maurizio Palesi. Maurizio Palesi 1
Buses Maurizio Palesi Maurizio Palesi 1 Introduction Buses are the simplest and most widely used interconnection networks A number of modules is connected via a single shared channel Microcontroller Microcontroller
More informationReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
1 ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology Mikkel B. Stensgaard and Jens Sparsø Technical University of Denmark Technical University of Denmark Outline 2 Motivation ReNoC Basic
More informationAnalyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components
Analyzing and Debugging Performance Issues with Advanced ARM CoreLink System IP Components By William Orme, Strategic Marketing Manager, ARM Ltd. and Nick Heaton, Senior Solutions Architect, Cadence Finding
More informationHardware/Software Partitioning for SoCs. EECE Advanced Topics in VLSI Design Spring 2009 Brad Quinton
Hardware/Software Partitioning for SoCs EECE 579 - Advanced Topics in VLSI Design Spring 2009 Brad Quinton Goals of this Lecture Automatic hardware/software partitioning is big topic... In this lecture,
More informationThe Design of MCU's Communication Interface
X International Symposium on Industrial Electronics INDEL 2014, Banja Luka, November 0608, 2014 The Design of MCU's Communication Interface Borisav Jovanović, Dejan Mirković and Milunka Damnjanović University
More informationI/O Systems. Amir H. Payberah. Amirkabir University of Technology (Tehran Polytechnic)
I/O Systems Amir H. Payberah amir@sics.se Amirkabir University of Technology (Tehran Polytechnic) Amir H. Payberah (Tehran Polytechnic) I/O Systems 1393/9/15 1 / 57 Motivation Amir H. Payberah (Tehran
More informationFunctional Verification of xhci (extensible host controller Interface) for USB 3.1 Using HDL
Functional Verification of xhci (extensible host controller Interface) for USB 3.1 Using HDL 1 Mr. Dipesh Gehani, 2 Prof. Ketan N. Patel, M.E. Student, Assistant Professor Vishwakarma Government Engineering
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP TFT Controller General Description The Digital Blocks TFT Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA 2.0 to a TFT panel. In an FPGA,
More informationAn Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart
An Asynchronous NoC Router in a 14nm FinFET Library: Comparison to an Industrial Synchronous Counterpart Weiwei Jiang Columbia University, USA Gabriele Miorandi University of Ferrara, Italy Wayne Burleson
More informationDesign of Embedded Hardware and Firmware
Design of Embedded Hardware and Firmware Introduction on "System On Programmable Chip" NIOS II Avalon Bus - DMA Andres Upegui Laboratoire de Systèmes Numériques hepia/hes-so Geneva, Switzerland Embedded
More informationDIGITAL DESIGN TECHNOLOGY & TECHNIQUES
DIGITAL DESIGN TECHNOLOGY & TECHNIQUES CAD for ASIC Design 1 INTEGRATED CIRCUITS (IC) An integrated circuit (IC) consists complex electronic circuitries and their interconnections. William Shockley et
More informationChapter 2 Designing Crossbar Based Systems
Chapter 2 Designing Crossbar Based Systems Over the last decade, the communication architecture of SoCs has evolved from single shared bus systems to multi-bus systems. Today, state-of-the-art bus based
More informationDesign of AMBA Based AHB2APB Bridge
14 Design of AMBA Based AHB2APB Bridge Vani.R.M and M.Roopa, Reader and Head University Science Instrumentation Center, Gulbarga University, Gulbarga, INDIA Assistant Professor in the Department of Electronics
More informationCHAPTER 3 ASYNCHRONOUS PIPELINE CONTROLLER
84 CHAPTER 3 ASYNCHRONOUS PIPELINE CONTROLLER 3.1 INTRODUCTION The introduction of several new asynchronous designs which provides high throughput and low latency is the significance of this chapter. The
More informationDigital Blocks Semiconductor IP
Digital Blocks Semiconductor IP -UHD General Description The Digital Blocks -UHD LCD Controller IP Core interfaces a video image in frame buffer memory via the AMBA 3.0 / 4.0 AXI Protocol Interconnect
More informationSystem-level simulation (HW/SW co-simulation) Outline. EE290A: Design of Embedded System ASV/LL 9/10
System-level simulation (/SW co-simulation) Outline Problem statement Simulation and embedded system design functional simulation performance simulation POLIS implementation partitioning example implementation
More informationTIMA Lab. Research Reports
ISSN 1292-862 TIMA Lab. Research Reports TIMA Laboratory, 46 avenue Félix Viallet, 38000 Grenoble France Session 1.2 - Hop Topics for SoC Design Asynchronous System Design Prof. Marc RENAUDIN TIMA, Grenoble,
More informationTest and Verification Solutions. ARM Based SOC Design and Verification
Test and Verification Solutions ARM Based SOC Design and Verification 7 July 2008 1 7 July 2008 14 March 2 Agenda System Verification Challenges ARM SoC DV Methodology ARM SoC Test bench Construction Conclusion
More informationModule Introduction. CONTENT: - 8 pages - 1 question. LEARNING TIME: - 15 minutes
Module Introduction PURPOSE: The intent of this module is to introduce a series of modules that explain important features of Motorola s i.mx applications processors. OBJECTIVES: - Explain the need for
More informationThe Use Of Virtual Platforms In MP-SoC Design. Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006
The Use Of Virtual Platforms In MP-SoC Design Eshel Haritan, VP Engineering CoWare Inc. MPSoC 2006 1 MPSoC Is MP SoC design happening? Why? Consumer Electronics Complexity Cost of ASIC Increased SW Content
More informationProcessor Architectures At A Glance: M.I.T. Raw vs. UC Davis AsAP
Processor Architectures At A Glance: M.I.T. Raw vs. UC Davis AsAP Presenter: Course: EEC 289Q: Reconfigurable Computing Course Instructor: Professor Soheil Ghiasi Outline Overview of M.I.T. Raw processor
More informationDigital Design Methodology
Digital Design Methodology Prof. Soo-Ik Chae Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008, John Wiley 1-1 Digital Design Methodology (Added) Design Methodology Design Specification
More informationEliminating Routing Congestion Issues with Logic Synthesis
Eliminating Routing Congestion Issues with Logic Synthesis By Mike Clarke, Diego Hammerschlag, Matt Rardon, and Ankush Sood Routing congestion, which results when too many routes need to go through an
More information08 - Address Generator Unit (AGU)
October 2, 2014 Todays lecture Memory subsystem Address Generator Unit (AGU) Schedule change A new lecture has been entered into the schedule (to compensate for the lost lecture last week) Memory subsystem
More informationUniversal Serial Bus Host Interface on an FPGA
Universal Serial Bus Host Interface on an FPGA Application Note For many years, designers have yearned for a general-purpose, high-performance serial communication protocol. The RS-232 and its derivatives
More informationARM Processors for Embedded Applications
ARM Processors for Embedded Applications Roadmap for ARM Processors ARM Architecture Basics ARM Families AMBA Architecture 1 Current ARM Core Families ARM7: Hard cores and Soft cores Cache with MPU or
More informationPrefetch Cache Module
PIC32 TM Prefetch Cache Module 2008 Microchip Technology Incorporated. All Rights Reserved. PIC32 Prefetch Cache Module Slide 1 Hello and welcome to the PIC32 Prefetch Cache Module webinar. I am Nilesh
More informationNoC Round Table / ESA Sep Asynchronous Three Dimensional Networks on. on Chip. Abbas Sheibanyrad
NoC Round Table / ESA Sep. 2009 Asynchronous Three Dimensional Networks on on Chip Frédéric ric PétrotP Outline Three Dimensional Integration Clock Distribution and GALS Paradigm Contribution of the Third
More informationSoC Design Lecture 11: SoC Bus Architectures. Shaahin Hessabi Department of Computer Engineering Sharif University of Technology
SoC Design Lecture 11: SoC Bus Architectures Shaahin Hessabi Department of Computer Engineering Sharif University of Technology On-Chip bus topologies Shared bus: Several masters and slaves connected to
More informationADPCM-LCO Voice Compression Logic Core
ADPCM-LCO Voice Compression Logic Core Functional Description The ADPCM-LCO logic core [Adaptive Differential Pulse Code Modulation-Low Channel count Optimized] is a peripheral for digital voice compression/de-compression
More informationDepartment of Computer Science, Institute for System Architecture, Operating Systems Group. Real-Time Systems '08 / '09. Hardware.
Department of Computer Science, Institute for System Architecture, Operating Systems Group Real-Time Systems '08 / '09 Hardware Marcus Völp Outlook Hardware is Source of Unpredictability Caches Pipeline
More informationContents 1 Introduction 2 Functional Verification: Challenges and Solutions 3 SystemVerilog Paradigm 4 UVM (Universal Verification Methodology)
1 Introduction............................................... 1 1.1 Functional Design Verification: Current State of Affair......... 2 1.2 Where Are the Bugs?.................................... 3 2 Functional
More informationCadence SystemC Design and Verification. NMI FPGA Network Meeting Jan 21, 2015
Cadence SystemC Design and Verification NMI FPGA Network Meeting Jan 21, 2015 The High Level Synthesis Opportunity Raising Abstraction Improves Design & Verification Optimizes Power, Area and Timing for
More information