Survey on Virtual Memory

Transcription

1 Survey on Virtual Memory 1. Introduction Today, Computers are a part of our everyday life. We want to make our tasks easier and we try to achieve these by some means of tools. Our next preference would be to have our work done faster for which we need improvement in performance. We usually upgrade our system by increasing our RAM size or selecting a faster processor. How far can this go? We need to find a way to use our resource to its maximum. This improvement in performance is achieved by increasing the memory size i.e. by increasing the address space known as the Virtual memory which is an imaginary memory on the disk handled by most of today s Operating systems in conjunction with the hardware. Initially the programmers used to swap memory blocks between the secondary memory and the main memory for improving the performance but this is now taken care by the Operating system and the memory management unit efficiently. 2. Basics of Virtual Addressing The size of the main memory is limited and thus we need to store the information in the secondary memory and access it whenever necessary. But the performance will be very less if we access the disk every time as the access time is more and thus we need a larger main memory. In order to maintain a well organized and efficient usage of memory, most frequently used addresses space should be kept in the main memory and swapped with the other portions whenever necessary from a particular memory space allocated in the disk called as the virtual memory. This kind of transaction gives an illusion of a single large main memory which is managed by the Operating system with the hardware. In a system with a virtual memory the CPU works with the virtual address space and so refers to the virtual address for data access. The virtual address need to be translated to a physical address to access the main memory. A page table is maintained to translate the virtual address to a physical address. This will be discussed in detail in the following sections. 2.1 Paging To help the physical address translation, the Virtual memory is divided into small equal sized blocks known as virtual pages which are identified with a virtual page number. The physical memory is also divided into pages with same size as the virtual pages and identified using a physical frame number. Each virtual page can be mapped to one physical page or frame. The virtual pages are paged into or paged out of the physical memory as needed. When paged in physical memory is allocated to that page and a mapping is maintained by the OS in a page table on the RAM.

2 Figure1. Allocation of Main memory frames to Virtual memory pages As we can see in Figure 1 a virtual memory of 40KB is divided into 10 equal pages of 4KB each. The page needed is paged into the physical memory of 12KB which is divided into three frames of 4KB each. The mapping for the allocation is recorded in the page table. This page table is used by the MMU to translate the virtual address to physical address. 2.2 Page Table Entries A page table is used to map a virtual page to physical frame thus it has one entry for each page. The page table is stored in the RAM and the origin of the page table is stored in a page table register. Thus, having the page number as an offset and adding with the page table pointer we can locate the page entry. The page entry for that page number gives the frame address for the physical memory if present which is maintained by a valid bit. The frame address with the offset of the virtual address can be used to locate the memory in that frame. Along with the frame number the page table also caries some more bits which reveals few information about the frame. Valid bit: indicates whether the translation is valid i.e. if the frame is present in the physical memory. Reference bit: indicates if the page was recently used Modify bit: indicates whether the page was recently written Page protection bit: holds the page access rights such as read-write or read only. Figure 2a helps us understand page table better. Let us consider a virtual address of 32 bits which gives a virtual address space of 4GB. The virtual address is split into two; an offset of 12 bits which corresponds to the page size of 4KB and virtual page number of 20 bits signifies 2 20 pages. The page table consists of 2 20 entries mapping to each page. The 32 bit virtual address is translated to 30 bit physical address (1GB). If the page is available in the physical memory then the page table gives a frame number of 18

3 bits which along with the page offset helps access the required data on the physical memory. Figure2. Virtual address to Physical address translation a) one level page table b) multi level page table Similarly we can also use multi level page table also called as hierarchical page tables. Multi level page table provides more sophisticated protection, allows accommodate larger address space and also page sharing between processes. Here it has a first level of root directory and corresponding levels of page table. Figure 2b shows a two level page table. 2.3 Translation Look-aside Buffer Accessing the page table entries every time to translate the physical address takes time. To reduce the translation time a buffer is maintained in the hardware which records the last n pages paged in the main memory called as a Translation Look-aside Buffer (TLB). The buffer organization is just as the page table where it is accessed with the virtual address and it gives the corresponding frame number. It also maintains a valid bit indicating the availability of the address in the main memory. The difference of the TLB from the page table is that it is associative. As the TLB maintains only a limited number of entries, if an address is not present in it then the page table is looked for and if the page is not in the physical memory then it is called as page fault which is similar to a cache miss. 3. Segmentation So far we have seen how we could obtain a large memory space and how it could be managed to access through address translation by paging. A new problem has been raised due smaller page size which will lead to frequent paging in and out giving more of overhead and thus reducing the performance. This problem caused is known as

4 Thrashing. A simple solution to this would be to use larger page sizes but it would lead to inefficient usage of memory as the pages may not be used completely. The reason behind is that the page size is fixed, so a possible solution will be to use a variable block size depending on the data size swapped in. This is known as segmentation. Figure3. Address translation with segmentation. The above figure3 shows the address translation for a segment. Similar to page table we use a segment descriptor table which holds the segment base address and the bound in other words the size of the segment. Here arises a doubt bout how the segment is managed? The answer is that the minimum segment size is fixed to the address space of the offset i.e. 2 n where n is the number of bits in the offset of the address. For the address translation the offset is compared to the bounds to validate its availability. If the offset is larger then the limit size then it is a fault. For better utilization segment pages are used which is an advancement. 4. Cache Access In a system which uses a virtual memory the CPU uses virtual address during its execution. The immediate memory that a CPU will access for data is the cache. The data from the cache is required to be fetched using the virtual address issued. The cache can be used as a physical cache or a virtual cache.

5 Figure4. Physical cache access a) pipelined TLB and cache access b) parallel TLB and cache access A physical cache is one which is accessed with the physical address. For the physical cache to be accessed the virtual address needs to be translated with the TLB and on a TLB miss the page table needs to be accessed as in figure4a. Thus this technique requires a higher access time. The improvement of this was that the TLB and the physical cache can be accessed simultaneously but the limitation is that the size of the cache is limited by the offset. Due to this limitation of cache size in the physical cache we migrate to the virtual cache which uses the virtual address for its access. In figure5a the cache is accessed with a virtual address and needs a TLB access only if a miss occurs in the cache at this level. The cache uses virtual tags and is called as a virtually indexed, virtually tagged cache (V/V). In figure5b the TLB and the cache are accessed in parallel and are thus physically tagged and the organization is known as virtually indexed physically tagged cache (V/P). Comparing figure4b and figure5b the difference is the extra m bit that is used from the VPN. These n bits are called as superset bits and are different from the physical address bits. All possible values for the superset are generated and we can obtain the superset containing the accessed value. These values of the set contain all the synonyms address and the physical address in it. Apart form synonym being a problem of redundant use of memory; it is also a problem with the address translation. The synonym problem needs to be removed to be free from this problem.

6 Figure5. Virtual cache access a) pipelined TLB and cache access b) parallel TLB and cache access 4.1 Synonym Problem Synonym problem is an important issue to be considered as it would occupy the memory multiple times with read access and with a read writes access makes the processor use a stale copy. Some solutions to the synonym problem are: Synonym prevention: The synonym can be prevented by implementing sharing at the segment level in segment page hierarchy. The other way would be to use a single address space operating system where all the processes share a single global virtual address. Synonym avoidance: This can be done by software by invalidating all or part of the cache when needed so that synonyms never appear in the cache. These invalidations are achieved by flushes or purges. Dynamic synonym reduction reverse mapping: In a memory hierarchy of virtual cache first level cache and a physical second level cache we can use reverse mapping where the physical cache will have a back pointer to the virtual cache and thus the tag has the virtual color of the first level tag. In a virtual memory hierarchy with virtual caches at first level and second level a Synonym look aside buffer (SLB) is used to avoid synonym 5. TLB Tag Reduction As seen above the time TLB access is based on the cache memory addressing. TLB is accessed by comparing the virtual address from the CPU with the virtual address tag in them. The TLB is said to consume 20-25% of the total cache power consumption. It has been proposed that the power consumption by the TLB can be reduced significantly by just using n least significant bits of the virtual address tags for comparison with the assumption that we have the knowledge f the process code and data occupancy in the virtual memory.

7 Figure6. VPN Tag resolution For a process and data set of a single process TLB can be accessed with last few LSB depending on the process set. Most of the program execution time is spent in a number of tight loops or functions called as hot spots. These hot spots would access only a limited number of pages helping us to apply the tag reduction. To apply this technique we need to know the address space of the application instruction set and data. This information need to be handled by the OS and thus manage the number of VPN bits in the tag required for the address translation. Hardware support is also required to provide access right for the OS to enable the number of bits to be compared. 5.1 Future Work In the above implementation OS needs to take control of the hardware and will be a over head to decide in advance for every process set that has been loaded to the physical memory. A better means of deciding the number of tag bits required can be done dynamically by comparing the VPN in the TLB. Thus the decision is based only on the n entries in the TLB rather then the all process sets. 6. Conclusion Virtual memory proves to be a boon to the programmers reducing their burden to take care of physical addressing. It also gives a larger address space improving the overall performance of the system. Though it brings in challenges in cache accesses, and with synonym problems, solutions are available and also a developing field where improvements will prove significantly good performance. References 1) Bruce Jacob, Trevor Mudge, Virtual Memory :Issues of Implementation, Volume 31, Issue 6, June 1998 Page(s): ) Michel Cekleov, Michel Dubois, VIRTUAL-ADDRESS CACHES Part 1: Problems and Solutions in Uniprocessors, Micro IEEE Volume 17, Issue 5, Sept.-Oct Page(s):64-71

8 3) Michel Cekleov, Michel Dubois, VIRTUAL-ADDRESS CACHES Part 2: Multiprocessors Issues, Micro IEEE Volume 17, Issue 6, Nov.-Dec Page(s): ) Xiaogang Qiu, Michel Dubois, Towards Virtually-Addressed Memory Hierarchies High-Performance Computer Architecture, HPCA. The Seventh International Symposium on Jan Page(s): ) Prof. D. Morris, C.J. Theaker, R. Phillips and W.R. Love, Virtual memory for microcomputers, IEE PROCEEDINGS, Vol. 132, Pt. E, No. 6, NOVEMBER ) Peter Petrov, Alex Orailoglu, Virtual Page Tag Reduction for Low-power TLBs, Computer Design, Proceedings. 21st International Conference on Oct Page(s):