6-output 3.3V PCIe Zero-Delay Buffer

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1 Description 6-output 3.3V PCIe Zero-Delay Buffer The 9DBL64 / 9DBL65 devices are 3.3V members of IDT's Full-Featured PCIe family. The 9DBL6 supports PCIe Gen-4 Common Clocked (CC) and PCIe Separate Reference Independent Spread (SRIS) systems. It offers a choice of integrated output terminations providing direct connection to 85Ω or Ω transmission lines. The 9DBL6P can be factory programmed with a user-defined power up default SMBus configuration. Recommended Application PCIe Gen-4 clock distribution for Riser Cards, Storage, Networking, JBD, Communications, Access Points utput Features 6-2 MHz Low-Power (LP) HCSL DIF pairs 9DBL64 default ZUT = 9DBL65 default ZUT = 85 9DBL6P factory programmable defaults Key Specifications PCIe Gen CC compliant in ZDB mode PCIe Gen2 SRIS compliant in ZDB mode Supports PCIe Gen2-3 SRIS in fan-out mode DIF cycle-to-cycle jitter <5 DIF output-to-output skew < 5 Bypass mode additive phase jitter is typical rms for PCIe Bypass mode additive phase jitter 6fs rms 56.25M (.5M to M) Block Diagram 9DBL64 / 9DBL65 DATASHEET Features/Benefits Direct connection to (xx4) or 85 (xx5) transmission lines; saves 24 resistors compared to standard PCIe devices 49mW typical power consumption (PLL mode@3.3v); eliminates thermal concerns VDDI allows 3% power savings at optional.5v; maximum power savings SMBus-selectable features allows optimization to customer requirements: control input polarity control input pull up/downs slew rate for each output differential output amplitude output impedance for each output 5,, 25MHz operating frequency Customer defined SMBus power up default can be programmed into P device; allows exact optimization to customer requirements E# pins; support DIF power management HCSL-compatible differential input; can be driven by common clock sources Spread Spectrum tolerant; allows reduction of EMI Pin/SMBus selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application utputs blocked until PLL is locked; clean system start-up Device contains default configuration; SMBus interface not required for device operation Three selectable SMBus addresses; multiple devices can easily share an SMBus segment Space saving 4-pin 5x5mm VFQFPN; minimal board space Note: Default resistors are internal on xx4/xx5 devices. P devices have programmable default impedances on an output-by-output basis. 9DBL64 / 9DBL65 FEBRUARY 8, Integrated Device Technology, Inc.

2 Pin Configuration ^CKPWRGD_PD# VDDI ve5# DIF5# DIF5 ve4# DIF4# DIF4 VDDI VDD vsadr_tri 3 NC ^vhibw_bypm_lbw# 2 29 ve3# FB_DNC 3 28 DIF3# FB_DNC# 4 27 DIF3 VDDR VDDI CLK_IN 6 9DBL64/5/P epad is GND 25 VDDA3.3 CLK_IN# 7 24 ve2# GNDDIG 8 23 DIF2# SCLK_ DIF2 SDATA_3.3 2 ve# VDDDIG3.3 VDDI ve# DIF DIF# VDD3.3 VDDI DIF DIF# NC SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# Power Management Table Power Connections 4-VFQFPN, 5mm x 5mm.4mm pin pitch ^ prefix indicates internal 2Khm pull up resistor ^v prefix indicates internal 2Khm pull up AND pull down resistor (biased to VDD/2) v prefix indicates internal 2Khm pull down resistor SADR Address M + Read/Write bit x x x Note: If not using CKPWRGD (CKPWRGD tied to VDD3.3), all 3.3V VDD need to transition from 2.V to 3.35V in <3usec. CKPWRGD_PD# CLK_IN SMBus DIFx Ex# Pin Ex bit True /P Comp. /P PLL X X X Low Low ff Running X Low Low n 2 Running Running Running n 2 Running Low Low n 2. The output state is set by B[:] (Low/Low default) 2. If Bypass mode is selected, the PLL will be off, and outputs will be running. PLL perating Mode Pin Number VDD VDDI GND Description 5 4 Input receiver analog 8 Digital Power 6, 3 2,7,26,32, DIF outputs, 4 39 Logic 25 4 PLL Analog HiBW_BypM_LoBW# MDE Byte [7:6] Readback Byte [4:3] Control PLL Lo BW M Bypass PLL Hi BW 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 2 FEBRUARY 8, 27

3 Pin Descriptions PIN # PIN NAME PIN TYPE DESCRIPTIN vsadr_tri LATCHED IN Tri-level latch to select SMBus Address. See SMBus Address Selection Table. 2 ^vhibw_bypm_lbw# LATCHED IN Trilevel input to select High BW, Bypass or Low BW mode. This pin is biased to VDD/2 (Bypass mode) with internal pull up/pull down resistors. See PLL perating Mode Table for Details. 3 FB_DNC DNC True clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 4 FB_DNC# DNC Complement clock of differential feedback. The feedback output and feedback input are connected internally on this pin. Do not connect anything to this pin. 5 VDDR3.3 PWR 3.3V power for differential input clock (receiver). This VDD should be treated as an Analog power rail and filtered appropriately. 6 CLK_IN IN True Input for differential reference clock. 7 CLK_IN# IN Complementary Input for differential reference clock. 8 GNDDIG GND Ground pin for digital circuitry 9 SCLK_3.3 IN Clock pin of SMBus circuitry, 3.3V tolerant. SDATA_3.3 I/ Data pin for SMBus circuitry, 3.3V tolerant. VDDDIG3.3 PWR 3.3V digital power (dirty power) 2 VDDI PWR Power supply for differential outputs 3 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 4 DIF UT Differential true clock output 5 DIF# UT Differential Complementary clock output 6 VDD3.3 PWR Power supply, nominal 3.3V 7 VDDI PWR Power supply for differential outputs 8 DIF UT Differential true clock output 9 DIF# UT Differential Complementary clock output 2 NC N/A No Connection. 2 ve# IN Active low input for enabling DIF pair. This pin has an internal pull-down. =disable outputs, = enable outputs 22 DIF2 UT Differential true clock output 23 DIF2# UT Differential Complementary clock output 24 ve2# IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. =disable outputs, = enable outputs 25 VDDA3.3 PWR 3.3V power for the PLL core. 26 VDDI PWR Power supply for differential outputs 27 DIF3 UT Differential true clock output 28 DIF3# UT Differential Complementary clock output 29 ve3# IN Active low input for enabling DIF pair 3. This pin has an internal pull-down. =disable outputs, = enable outputs 3 NC N/A No Connection. 3 VDD3.3 PWR Power supply, nominal 3.3V 32 VDDI PWR Power supply for differential outputs 33 DIF4 UT Differential true clock output 34 DIF4# UT Differential Complementary clock output 35 ve4# IN Active low input for enabling DIF pair 4. This pin has an internal pull-down. =disable outputs, = enable outputs 36 DIF5 UT Differential true clock output 37 DIF5# UT Differential Complementary clock output 38 ve5# IN Active low input for enabling DIF pair 5. This pin has an internal pull-down. =disable outputs, = enable outputs 39 VDDI PWR Power supply for differential outputs 4 ^CKPWRGD_PD# IN Input notifies device to sample latched inputs and start up on first high assertion. Low enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal pull-up resistor. 4 epad GND Connect paddle to ground. FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

4 Test Loads Low-Power push-pull HCSL utput test load (integrated terminations) L inches Differential Zo 2pF 2pF Terminations Device Zo (Ω) Rs (Ω) 9DBL64 None needed 9DBL DBL6P Prog. 9DBL64 85 N/A 9DBL65 85 None needed 9DBL6P 85 Prog. L = 5 inches Alternate Terminations The 9DBL64 / 9DBL65 can easily drive LVPECL, LVDS, and CML logic. See AN-89 Driving LVPECL, LVDS, and CML Logic with IDT's "Universal" Low-Power HCSL utputs for details. 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 4 FEBRUARY 8, 27

5 Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 9DBL64 / 9DBL65. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Supply Voltage VDDx 4.6 V,2 Input Voltage V IN -.5 V DD +.5 V,3 Input High Voltage, SMBus V IHSMB SMBus clock and data pins 3.9 V Storage Temperature Ts C Junction Temperature Tj 25 C Input ESD protection ESD prot Human Body Model 25 V Guaranteed by design and characterization, not % tested in production. 2 peration under these conditions is neither implied nor guaranteed. 3 Not to exceed 4.6V. Electrical Characteristics Clock Input Parameters TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Input Crossover Voltage - DIF_IN V CRSS Cross ver Voltage 5 9 mv Input Swing - DIF_IN V SWING Differential value 3 mv Input Slew Rate - DIF_IN dv/dt Measured differentially.4 8 V/ns,2 Input Leakage Current I IN V IN = V DD, V IN = GND -5 5 ua Input Duty Cycle d tin Measurement from differential wavefrom % Input Jitter - Cycle to Cycle J DIFIn Differential Measurement 25 Guaranteed by design and characterization, not % tested in production. 2 Slew rate measured through +/-75mV window centered around differential zero Electrical Characteristics SMBus Parameters TA = T AMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES SMBus Input Low Voltage V ILSMB V DDSMB = 3.3V.8 V SMBus Input High Voltage V IHSMB V DDSMB = 3.3V V SMBus utput Low Voltage V I PULLUP.4 V SMBus Sink Current I V L 4 ma Nominal Bus Voltage V DDSMB V SCLK/SDATA Rise Time t RSMB (Max VIL -.5) to (Min VIH +.5) ns SCLK/SDATA Fall Time t FSMB (Min VIH +.5) to (Max VIL -.5) 3 ns SMBus perating Frequency f SMB SMBus operating frequency 5 khz 2,3 Guaranteed by design and characterization, not % tested in production. 2. The device must be powered up for the SMBus to function. 3. The differential input clock must be running for the SMBus to be active FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

6 Electrical Characteristics Input/Supply/Common Parameters Normal perating Conditions TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Supply Voltage VDDx Supply voltage for core and analog V utput Supply Voltage VDDI Supply voltage for Low Power HCSL utputs V Ambient perating Temperature T AMB Industrial range C Input High Voltage V IH Single-ended inputs, except SMBus.75 V DDx V DDx +.3 V Input Low Voltage V IL V DDx V Input High Voltage V IHtri.75 V DDx V DD +.3 V Input Mid Voltage V IMtri Single-ended tri-level inputs ('_tri' suffix).4 V DDx.5 V DDx.6 V DDx V Input Low Voltage V ILtri V DDx V I IN Single-ended inputs, V IN = GND, V IN = VDD -5 5 ua Input Current Single-ended inputs I INP V IN = V; Inputs with internal pull-up resistors -5 5 ua V IN = VDD; Inputs with internal pull-down resistors Bypass mode 2 MHz 2 Input Frequency F IN MHz PLL mode 6. 4 MHz 2 5MHz PLL mode MHz 2 25MHz PLL mode MHz 2 Pin Inductance L pin 7 nh C IN Logic Inputs, except DIF_IN.5 5 pf Capacitance C INDIF_IN DIF_IN differential clock inputs pf C UT utput pin capacitance 6 pf From V Clk Stabilization T DD Power-Up and after input clock STAB stabilization or de-assertion of PD# to st clock ms,2 Input SS Modulation Frequency PCIe f MDINPCIe Allowable Frequency for PCIe Applications (Triangular Modulation) 3 33 khz Input SS Modulation Frequency non-pcie f MDIN Allowable Frequency for non-pcie Applications (Triangular Modulation) 66 khz DIF start after E# assertion E# Latency t LATE# DIF stop after E# deassertion 3 clocks,3 DIF output enable after Tdrive_PD# t DRVPD PD# de-assertion 3 us,3 Tfall t F Fall time of single-ended control inputs 5 ns 2 Trise t R Rise time of single-ended control inputs 5 ns 2 Guaranteed by design and characterization, not % tested in production. 2 Control input must be monotonic from 2% to 8% of input swing. 3 Time from deassertion until outputs are >2 mv 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 6 FEBRUARY 8, 27

7 Electrical Characteristics DIF Low-Power HCSL utputs TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES Slew rate dv/dt Scope averaging on, fast setting V/ns,2,3 dv/dt Scope averaging on, slow setting V/ns,2,3 Slew rate matching ΔdV/dt Slew rate matching 7 2 %,2,4 Voltage High V HIGH Statistical measurement on single-ended signal using oscilloscope math function. (Scope mv Voltage Low V LW averaging on) Max Voltage Vmax Measurement on single ended signal using mv Min Voltage Vmin absolute value. (Scope averaging off) Crossing Voltage (abs) Vcross_abs Scope averaging off mv,5 Crossing Voltage (var) Δ-Vcross Scope averaging off 4 4 mv,6 Guaranteed by design and characterization, not % tested in production. 2 Measured from differential waveform 3 Slew rate is measured through the Vswing voltage range centered around differential V. This results in a +/-5mV window around differential V. 4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. 5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e. Clock rising and Clock# falling). 6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute. 7 At default SMBus settings. Electrical Characteristics Current Consumption TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES I DDA VDDA, PLL 7 5 ma perating Supply Current I DD VDDx, All outputs 7 22 ma I DDI VDDI, All outputs 2 25 ma I DDAPD VDDA, CKPWRGD_PD#=.6 2 ma 2 Powerdown Current I DDPD VDDx, CKPWRGD_PD#= ma 2 I DDIPD VDDI, CKPWRGD_PD#=.4. ma 2 Guaranteed by design and characterization, not % tested in production. 2 Input clock stopped. FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

8 Electrical Characteristics utput Duty Cycle, Jitter, Skew and PLL Characteristics TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS NTES PLL Bandwidth BW -3dB point in High BW Mode (MHz) MHz,5-3dB point in Low BW Mode (MHz).5 2 MHz,5 PLL Jitter Peaking t JPEAK Peak Pass band Gain (MHz).8 2 db Duty Cycle t DC Measured differentially, PLL Mode % Duty Cycle Distortion t DCD Measured differentially, Bypass Mode -. %,3 Skew, Input to utput t pdbyp Bypass Mode, V T = 5% t pdpll PLL Mode V T = 5% - 8,4 Skew, utput to utput t sk3 V T = 5% 2 55,4 Jitter, Cycle to cycle t jcyc-cyc PLL mode 5 5,2 Additive Jitter in Bypass Mode.,2 Guaranteed by design and characterization, not % tested in production. 2 Measured from differential waveform 3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode. 4 All outputs at default slew rate 5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN. Electrical Characteristics Filtered Phase Jitter Parameters - PCIe Common Clocked (CC) Architectures T AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions INDUSTRY PARAMETER SYMBL CNDITINS MIN TYP MAX UNITS Notes LIMIT t jphpcieg-cc PCIe Gen (p-p),2,3,5 PCIe Gen 2 Lo Band khz < f <.5MHz.6.8 3,2,5 (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) Phase Jitter, PLL Mode Additive Phase Jitter, Bypass mode t jphpcieg2-cc PCIe Gen 2 High Band.5MHz < f < Nyquist (5MHz) (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) PCIe Gen 3 t jphpcieg3-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz).4.48 PCIe Gen 4 t jphpcieg4-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) t jphpcieg-cc PCIe Gen.. PCIe Gen 2 Lo Band khz < f <.5MHz (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) t jphpcieg2-cc PCIe Gen 2 High Band.5MHz < f < Nyquist (5MHz) (PLL BW of 5-6MHz or 8-5MHz, CDR = 5MHz) PCIe Gen 3 t jphpcieg3-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) PCIe Gen 4 t jphpcieg4-cc (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) Applies to all outputs. 2 Based on PCIe Base Specification Rev4. version.7draft. See for latest specifications. 3 Sample size of at least K cycles. This figures extrapolates to 8 M cycles for a BER of For RMS values additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter. 5 Driven by 9FGL84 or equivalent n/a (p-p),2,5,2,5,2,5,2,5,2,4,5,2,4,5,2,4,5,2,4,5 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 8 FEBRUARY 8, 27

9 Electrical Characteristics Filtered Phase Jitter Parameters - PCIe Separate Reference Independent Spread (SRIS) Architectures 5 T AMB = over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX Phase Jitter, PLL Mode Additive Phase Jitter, Bypass mode t jphpcieg2- SRIS t jphpcieg3- SRIS t jphpcieg2- SRIS t jphpcieg3- SRIS PCIe Gen 2 (PLL BW of 6MHz, CDR = 5MHz) PCIe Gen 3 (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) PCIe Gen 2 (PLL BW of 6MHz, CDR = 5MHz) PCIe Gen 3 (PLL BW of 2-4MHz or 2-5MHz, CDR = MHz) Electrical Characteristics Unfiltered Phase Jitter Parameters INDUSTRY LIMIT Applies to all outputs. 2 Based on PCIe Base Specification Rev3.a. These filters are different than Common Clock filters. See for latest specifications. 3 Sample size of at least K cycles. This figures extrapolates to 8 M cycles for a BER of For RMS values, additive jitter is calculated by solving the following equation for b [a^2+b^2=c^2 ] where a is rms input jitter and c is rms total jitter. 5 As of PCIe Base Specification Rev4. draft.7, SRIS is not currently defined for Gen or Gen4. 6 This device does not support PCIe Gen3 SRIS in PLL mode. It supports PCIe Gen3 SRIS in bypass mode. TA = T AMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions PARAMETER SYMBL CNDITINS MIN TYP MAX Additive Phase Jitter, Fanout Mode t jph56m t jph56m2k MHz,.5MHz to MHz, -2dB/decade rollover <.5MHz, -4db/decade rolloff > MHz 56.25MHz, 2kHz to 2MHz, -2dB/decade rollover <2kHz, -4db/decade rolloff > 2MHz Guaranteed by design and characterization, not % tested in production. 2 DRiven by Rohde&Schartz SMA n/a.5 n/a 59 N/A 363 N/A 3 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2] UNITS Notes,2,2,6,2,4,2,4,6 INDUSTRY LIMIT UNITS Notes fs fs,2,3,2,3 FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

10 General SMBus Serial Interface Information How to Write Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X- IDT clock will acknowledge each byte one at a time Controller (host) sends a Stop bit Index Block Write peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK Byte N + X - ACK P stop bit X Byte Note: SMBus Address is Latched on SADR pin. Unless otherwise indicated, default values are for the 64 and 65. P devices are fully factory programmable. How to Read Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X- IDT clock sends Byte through Byte X (if X (H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit Index Block Read peration Controller (Host) IDT (Slave/Receiver) T start bit Slave Address WR WRite ACK Beginning Byte = N ACK RT Repeat start Slave Address RD ReaD ACK N P ACK ACK Not acknowledge stop bit X Byte Data Byte Count=X Beginning Byte N Byte N + X - 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER FEBRUARY 8, 27

11 SMBus Table: utput Enable Register Byte Name Control Function Type Default Bit 7 DIF E5 utput Enable RW Pin Control See B[:] Bit 6 DIF E4 utput Enable RW Pin Control Bit 5 Reserved Bit 4 DIF E3 utput Enable RW Pin Control Bit 3 DIF E2 utput Enable RW See B[:] Pin Control Bit 2 DIF E utput Enable RW Pin Control Bit Reserved Bit DIF E utput Enable RW See B[:] Pin Control. A low on these bits will overide the E# pin and force the differential output to the state indicated by B[:] (Low/Low default) SMBus Table: PLL perating Mode and utput Amplitude Control Register Byte Name Control Function Type Default Bit 7 PLLMDERB PLL Mode Readback Bit R Latch See PLL perating Mode Table Bit 6 PLLMDERB PLL Mode Readback Bit R Latch Values in B[7:6] Values in B[4:3] Bit 5 PLLMDE_SWCNTRL Enable SW control of PLL Mode RW set PLL Mode set PLL Mode Bit 4 PLLMDE PLL Mode Control Bit RW Bit 3 PLLMDE PLL Mode Control Bit RW See PLL perating Mode Table Bit 2 Reserved Bit AMPLITUDE RW =.6V =.68V Controls utput Amplitude Bit AMPLITUDE RW =.75V =.85V. B[5] must be set to a for these bits to have any effect on the part. SMBus Table: Slew Rate Control Register Byte 2 Name Control Function Type Default Bit 7 SLEWRATESEL DIF5 Slew rate selection RW Slow Setting Fast Setting Bit 6 SLEWRATESEL DIF4 Slew rate selection RW Slow Setting Fast Setting Bit 5 Reserved Bit 4 SLEWRATESEL DIF3 Slew rate selection RW Slow Setting Fast Setting Bit 3 SLEWRATESEL DIF2 Slew rate selection RW Slow Setting Fast Setting Bit 2 SLEWRATESEL DIF Slew rate selection RW Slow Setting Fast Setting Bit Reserved Bit SLEWRATESEL DIF Slew rate selection RW Slow Setting Fast Setting Note: See "Low-Power HCSL utputs" table for slew rates. SMBus Table: Slew Rate Control Register Byte 3 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 FREQ_SEL_EN Enable SW selection of SW frequency SW frequency RW frequency change disabled change enabled Bit 4 FSEL Freq. Select Bit RW = M, = 25M Bit 3 FSEL Freq. Select Bit RW = 5M, = Reserved Bit 2 Reserved Bit Reserved Bit SLEWRATESEL FB Adjust Slew Rate of FB RW Slow Setting Fast Setting. B3[5] must be set to a for these bits to have any effect on the part. Byte 4 is Reserved FEBRUARY 8, 27 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER

12 SMBus Table: Revision and Vendor ID Register Byte 5 Name Control Function Type Default Bit 7 RID3 R Bit 6 RID2 R Revision ID B rev = Bit 5 RID R Bit 4 RID R Bit 3 VID3 R Bit 2 VID2 R VENDR ID = IDT Bit VID R Bit VID R SMBus Table: Device Type/Device ID Byte 6 Name Control Function Type Default Bit 7 Device Type RW = FGx, = DBx ZDB/FB, Device Type Bit 6 Device Type RW = DMx, = DBx FB Bit 5 Device ID5 RW Bit 4 Device ID4 RW Bit 3 Device ID3 RW Device ID binary or 6 hex Bit 2 Device ID2 RW Bit Device ID RW Bit Device ID RW SMBus Table: Byte Count Register Byte 7 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 BC4 RW Bit 3 BC3 RW Writing to this register will configure how Bit 2 BC2 Byte Count Programming RW many bytes will be read back, default is Bit BC RW = 8 bytes. Bit BC RW Bytes 8 and 9 are Reserved SMBus Table: PD_Restore Byte Name Control Function Type Default Bit 7 Reserved Bit 6 Power-Down (PD) Restore Restore Default Config. In PD RW Clear Config in PD Keep Config in PD Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit Reserved 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 2 FEBRUARY 8, 27

13 SMBus Table: Stop State and Impedance Control Byte Name Control Function Type Default Bit 7 FB_imp[] FB Zout RW =33Ω DIF Zout =Ω DIF Zout Bit 6 FB_imp[] FB Zout RW =85Ω DIF Zout = Reserved see Note Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit STP[] True/Complement DIF utput RW = Low/Low = High/Low Bit STP[] Disable State RW = HiZ/HiZ = Low/High Note: xx4 =, xx5 =, P = factory programmable. SMBus Table: Impedance Control Byte 2 Name Control Function Type Default Bit 7 DIF2_imp[] DIF2 Zout RW =33Ω DIF Zout =Ω DIF Zout Bit 6 DIF2_imp[] DIF2 Zout RW =85Ω DIF Zout = Reserved Bit 5 DIF_imp[] DIF Zout RW =33Ω DIF Zout =Ω DIF Zout see Note Bit 4 DIF_imp[] DIF Zout RW =85Ω DIF Zout = Reserved Bit 3 Reserved X Bit 2 Reserved X Bit DIF_imp[] DIF Zout RW =33Ω DIF Zout =Ω DIF Zout Bit DIF_imp[] DIF Zout RW =85Ω DIF Zout = Reserved see Note Note: xx4 =, xx5 =, P = factory programmable. SMBus Table: Impedance Control Byte 3 Name Control Function Type Default Bit 7 DIF5_imp[] DIF5 Zout RW =33Ω DIF Zout =Ω DIF Zout Bit 6 DIF5_imp[] DIF5 Zout RW =85Ω DIF Zout = Reserved Bit 5 DIF4_imp[] DIF4 Zout RW =33Ω DIF Zout =Ω DIF Zout see Note Bit 4 DIF4_imp[] DIF6 Zout RW =85Ω DIF Zout = Reserved Bit 3 Reserved X Bit 2 Reserved X Bit DIF3_imp[] DIF3 Zout RW =33Ω DIF Zout =Ω DIF Zout Bit DIF3_imp[] DIF3 Zout RW =85Ω DIF Zout = Reserved see Note Note: xx4 =, xx5 =, P = factory programmable. SMBus Table: Pull-up Pull-down Control Byte 4 Name Control Function Type Default Bit 7 E2_pu/pd[] E2 Pull-up(PuP)/ RW =None =Pup Bit 6 E2_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit 5 E_pu/pd[] E Pull-up(PuP)/ RW =None =Pup Bit 4 E_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit 3 Reserved X Bit 2 Reserved X Bit E_pu/pd[] E Pull-up(PuP)/ RW =None =Pup Bit E_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Note: These values are for xx4 and xx5. P is factory programmable. FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

14 SMBus Table: Pull-up Pull-down Control Byte 5 Name Control Function Type Default Bit 7 E5_pu/pd[] E5 Pull-up(PuP)/ RW =None =Pup Bit 6 E5_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit 5 E4_pu/pd[] E4 Pull-up(PuP)/ RW =None =Pup Bit 4 E4_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Bit 3 Reserved X Bit 2 Reserved X Bit E3_pu/pd[] E3 Pull-up(PuP)/ RW =None =Pup Bit E3_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn Note: These values are for xx4 and xx5. P is factory programmable. SMBus Table: Pull-up Pull-down Control Byte 6 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved X Bit 2 Reserved X Bit CKPWRGD_PD_pu/pd[] CKPWRGD_PD Pull-up(PuP)/ RW =None =Pup Bit CKPWRGD_PD_pu/pd[] Pull-down(Pdwn) control RW =Pdwn = Pup+Pdwn * 9DBL9xx devices only. Note: These values are for xx4 and xx5. P is factory programmable. Bytes 7 is Reserved and and reads back h. SMBus Table: Polarity Control Byte 8 Name Control Function Type Default Bit 7 E5_polarity Sets E5 polarity RW Enabled when Low Enabled when High Bit 6 E4_polarity Sets E4 polarity RW Enabled when Low Enabled when High Bit 5 Reserved Bit 4 E3_polarity Sets E3 polarity RW Enabled when Low Enabled when High Bit 3 E2_polarity Sets E2 polarity RW Enabled when Low Enabled when High Bit 2 E_polarity Sets E polarity RW Enabled when Low Enabled when High Bit Reserved Bit E_polarity Sets E polarity RW Enabled when Low Enabled when High SMBus Table: Polarity Control Byte 9 Name Control Function Type Default Bit 7 Reserved Bit 6 Reserved Bit 5 Reserved Bit 4 Reserved Bit 3 Reserved Bit 2 Reserved Bit Reserved Bit CKPWRGD_PD Determines Power Down when Power Down when RW CKPWRGD_PD polarity Low High 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 4 FEBRUARY 8, 27

15 Marking Diagrams ICS BL64BI YYWW C LT ICS BL65BI YYWW C LT ICS B6PBI YYWW C LT Notes:. LT is the lot sequence number. 2. C denotes country of origin. 3. YYWW is the last two digits of the year and week that the part was assembled. 4. Line 2: truncated part number 5. I denotes industrial temperature range device. Thermal Characteristics PARAMETER SYMBL CNDITINS PKG TYP. VALUE UNITS NTES θ JC Junction to Case 42 C/W θ Jb Junction to Base 2.4 C/W Thermal Resistance θ JAθ Junction to Air, still air 39 C/W NDG4 θ JA Junction to Air, m/s air flow 33 C/W θ JA3 Junction to Air, 3 m/s air flow 28 C/W θ JA5 Junction to Air, 5 m/s air flow 27 C/W epad soldered to board FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

16 Package utline and Dimensions (NDG4) 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 6 FEBRUARY 8, 27

17 Package utline and Dimensions, cont. (NDG4) FEBRUARY 8, UTPUT 3.3V PCIE ZER-DELAY BUFFER

18 rdering Information Part / rder Number utput Impedance Shipping Packaging Package Temperature 9DBL64BKILF Trays 4-pin VFQFPN -4 to +85 C Ω 9DBL64BKILFT Tape and Reel 4-pin VFQFPN -4 to +85 C 9DBL65BKILF Trays 4-pin VFQFPN -4 to +85 C 85Ω 9DBL65BKILFT Tape and Reel 4-pin VFQFPN -4 to +85 C 9DBL6PBxxxKILF Factory configurable. Contact Trays 4-pin VFQFPN -4 to +85 C 9DBL6PBxxxKILFT IDT for addtional information. Tape and Reel 4-pin VFQFPN -4 to +85 C LF suffix to the part number are the Pb-Free configuration and are RoHS compliant. B is the device revision designator (will not correlate with the datasheet revision). xxx is a unique factory assigned number to identify a particular default configuration. Revision History Rev. Initiator Issue Date Description Page # B RDW 6/2/26. Electrical Table and SMBus Updates/Corrections 2. Release to final. Various C RDW 6/7/26. SMBus operating frequency is now set to 5kHz max. 2. Removed duplicate Absolute Maximum Table. Various 3. Corrected "Test Loads" table D RDW 6/8/26. Added Frequency Select info to Byte 3 E RDW 6/4/26. Updated IDD tables 7 F RDW 9/2/26. Corrected Byte 2 to properly indicate slew rate control bits G RDW 2/8/27 Updated part numbering throughout datasheet to be 9DBL64 / 9DBL65 Various 6-UTPUT 3.3V PCIE ZER-DELAY BUFFER 8 FEBRUARY 8, 27

19 Corporate Headquarters 624 Silver Creek Valley Road San Jose, CA 9538 USA Sales or Fax: Tech Support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. ther trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. Copyright 27 Integrated Device Technology, Inc.. All rights reserved.

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