Enabling success from the center of technology. Interfacing FPGAs to Memory

Transcription

1 Interfacing FPGAs to Memory

2 Goals 2 Understand the FPGA/memory interface Available memory technologies Available memory interface IP & tools from Xilinx Compare Performance Cost Resources Demonstrate a memory interface using the Xilinx Memory Interface Generator (MIG)

3 Agenda 3 The FPGA/memory solution Memory technologies FPGA-based memory controllers MIG demonstration Conclusion

4 Agenda 4 The FPGA/memory solution Memory technologies FPGA-based memory controllers MIG demonstration Conclusion

5 The FPGA/Memory Interface 5 Memory interface success in an FPGA is dependent on many things FPGA Controller Termination Termination Memory FPGA fabric Controller Memory Layout PCB Power Power

6 Layout and Power 6 This session does not cover layout and power Recommendations Follow the manufacturer s guidelines Analyze signal integrity Use proper termination If done correctly, these do not determine bandwidth and performance

7 Factors Affecting Performance 7 FPGA must support I/O standard for the memory System clock frequency requirements Controller IP must support Targeted FPGA architecture Memory modes and features Memory must support Desired bandwidth Cost objectives Solution = FPGA + IP + Memory Performance based on the weakest link

8 Two Examples 8 Virtex-4 FX embedded PowerPC with DDR SDRAM DDR SDRAM operates up to 200 MHz Maximum realistic processor bus speed is 100 MHz Processor bus is 64-bit, single data rate Bandwidth determined by processor bus Slowest speed grade, 32-bit DDR is acceptable Spartan-3A with DDR2 DDR2 SDRAM operates up to 533 MHz Xilinx IP can run at 333 MHz in Virtex-5 Spartan-3A max speed is 166 MHz Limited to 32-bit, double data rate Bandwidth determined by FPGA Slowest speed grade, 32-bit DDR2 is acceptable

9 Memory Selection Criteria 9 System What performance is required? What are the power or voltage limitations? Does the solution meet the cost target? FPGA and controller What controllers are available? How fast will those controllers run in each FPGA? Memory What memory technology meets application requirements? What speed grade memory is required for that performance? Which memory has an acceptable lifespan? Choose memory, FPGA, and controller that meet your needs

10 Agenda 10 The FPGA/memory solution Memory technologies FPGA-based memory controllers MIG demonstration Conclusion

11 Definitions for this Session 11 Clock rate is defined in MHz or GHz Data rate per pin is defined in Mbps or Gbps MHz GHz Mbps Gbps MBps GBps mega-hertz giga-hertz mega-bits per second giga-bits per second mega-bytes per second giga-bytes per second

12 Memory Technologies Flash and SRAM 12 Flash Non-volatile Varieties NOR NAND SRAM = Static Random Access Memory Volatile Varieties Standard synchronous ZBT / NoBL DDR-II / II+ QDR-II / II+

13 NOR Flash 13 Serial and parallel (x8, x8/x16, x16) Random-access Faster read speed than NAND FPGA configuration supported for both serial and parallel Serial option decreases pin count, cost, and bandwidth Simple interface (similar to standard synchronous SRAM) S33 SPI P30 / P33 8 SOIC 16 SOIC 16Mb 32Mb 64Mb 64Mb 512Mb

14 NAND Flash 14 Parallel (x8 or x16) Available in 2Gb, 4Gb, 8Gb, and 16Gb devices NAND has overtaken DRAM as the top selling memory Lowest price per bit Largest volume of shipping megabytes More complicated interface than NOR flash Controller must handle bad blocks and wear leveling Available from Micron and Intel

15 SRAM 15 Standard synchronous Simple interface 250 MHz 18 to 72Mb (144Mb coming) 2 to 9Mb not recommended for new designs Zero-Bus Turnaround (ZBT) or No Bus Latency (NoBL) Allows back-to-back read/write operations 250 MHz Similar densities to standard synchronous

16 DDR-II SRAM 16 DDR-II SRAM DDR = Double-data rate Single read/write port Data transferred on both clock edges Up to 300 MHz (600 Mbps) 18 to 72Mb DDR-II+ SRAM Next generation DDR-II Up to 400 MHz (800 Mbps) 500 MHz (1.0 Gbps) in to 72Mb

17 QDR-II SRAM 17 QDR-II QDR = Quad-data rate SRAM Data transferred on both clock edges Separate read and write ports 2x clock + 2x ports = 4x throughput 18 to 72Mb Up to 300 MHz (1.2 Gbps) QDR-II+ Next generation QDR-II Up to 400 MHz (1.6 Gbps) 500 MHz (2.0 Gbps) in to 72Mb

18 Memory Technologies - DRAM 18 DRAM = Dynamic Random Access Memory Volatile Refresh required Varieties SDR SDRAM DDR SDRAM DDR2 SDRAM DDR3 SDRAM RLDRAM-II

19 DRAM Technology Trends 19 Source: IDC, isuppli Q306 Choose mainstream memory technology

20 DRAM Component Density Trends 20 Source: IDC, Isuppli, Gartner Q306 Choose mainstream memory density

21 SDR SDRAM 21 SDR SDRAM = Single Data Rate Synchronous DRAM Only one clock edge used Simpler than DDR More expensive per bit than DDR Smaller density than DDR 64 to 512Mb Slower data rate than DDR 125 to 200 Mbps 3.3V LVTTL interface

22 DDR SDRAM 22 DDR = Double Data Rate Both clock edges used to transfer data More expensive per bit than DDR2 Smaller density than DDR2 128Mb to 1Gb Slower data rate than DDR2 200 to 400 Mbps SSTL 2.5V interface 1.25V reference voltage required

23 DDR2 SDRAM 23 DDR2 = 2 nd generation DDR Both clock edges used to transfer data Least expensive per bit Large density devices 256Mb to 2Gb Fast data rate devices 400 to 1066 Mbps On-die termination (ODT) for data May simplify board design Increased latency at higher frequencies SSTL 1.8V interface 0.9V reference voltage required

24 DDR3 SDRAM 24 DDR3 = 3rd generation DDR Both clock edges used to transfer data Limited device selection currently Micron.com shows only a 1Gb device (Feb 07) Data rates shown of 800 to 1066 Mbps Roadmap to 4Gb and 1.6 Gbps Improved packaging Thermal sensor for refresh frequency interval On-die termination (ODT) added for address/control May further simplify board design SSTL 1.5V interface 0.75V reference voltage required Expect to see DDR3 become lead device by 2010

25 DDR SDRAM Comparison 25 Voltage Speed Density On-Die Termination DDR 2.5V / 1.25V Mbps 128 Mb 1 Gb None DDR2 1.8V / 0.9V Mbps 256 Mb 2 Gb Data only DDR3 1.5V / 0.75V 800 Mbps 1.6 Gbps 512 Mb 4 Gb Data, address, control

26 RLDRAM-II 26 RLDRAM-II = 2nd generation Reduced Latency DRAM Also double data rate, similar to DDR2 More expensive per bit Limited device densities Device size range is 288 to 576Mb Fast devices Device data rate range is 400 to 1066 Mbps On-die termination (ODT) for data High, sustainable bandwidth in back-to-back read/writes L3 cache Networking applications High-end commercial graphics HSTL 1.5 interface (1.8V also available) 0.75V reference voltage required Programmable output impedance

27 Memory Modules 27 UDIMM or DIMM Unbuffered DIMM SODIMM Small Outline DIMM RDIMM Registered DIMM Modules simplify board layout Termination and routing

28 Memory Cost Comparison 28 Memory Part Number Speed (MHz) Size Cost Cost per MB SDR SDRAM MT48LC16M16A2P Mb $6.26 $0.196 DDR SDRAM MT46V16M16TG-6T Mb $4.56 $0.143 DDR2 SDRAM MT47H32M16BT-37E Mb $6.73 $0.105 RLDRAM MT49H16M18CFM Mb $ $3.03 Sync SRAM CY7C1382D-200AXCT Mb $24.42 $10.85 QDR SRAM CY7C1315BV18-200BZXC Mb $35.24 $15.66 Serial NOR M25P Mb $2.24 $1.12 NOR Flash RC28F320J Mb $7.03 $1.76 NAND Flash MT29F2G08AACWP -- 2Gb $8.20 $ piece web pricing (February 21, 2007)

29 Agenda 29 The FPGA/memory solution Memory technologies FPGA-based memory controllers Reference designs MIG EDK MPMC 3 rd -party MIG demonstration Conclusion

30 Why Do I Need a Controller? 30 EASIER TO USE! Manages multiple operations Initialization See the DDR datasheet excerpt Calibration Adjust the FPGA I/O delay Refresh DRAMs Interface to custom logic simplified Reduces the design effort

31 Xilinx Tools and IP 31 Application notes include reference designs Memory Interface Generator (MIG) Embedded Development Kit (EDK) IP Connect memory to MicroBlaze soft processor Connect memory to PowerPC hard processor Multi-port Memory Controller (MPMC) 3 rd -party controllers

32 Xilinx Application Notes 32 Based on a specific FPGA, memory, width, and speed Virtex-5 DDR SDRAM XAPP851 DDR2 SDRAM XAPP858 RLDRAM II XAPP852 QDR-II SRAM XAPP853 Virtex-4 DDR SDRAM XAPP709 DDR2 SDRAM Direct Clocking XAPP701 & XAPP702 DDR2 SDRAM SERDES XAPP721 & XAPP723 RLDRAM-II XAPP710 QDR-II SRAM XAPP703 Spartan-3/3E/3A DDR SDRAM XAPP768c DDR2 SDRAM XAPP454

33 Other Information 33 NAND Flash reference designs XAPP354 for CoolRunner-II Micron reference design TN ZBT SRAM reference design XAPP136 Based on Virtex/Spartan-II, but still useful SDR SDRAM reference design XAPP134 in ISE examples File Open Example XAPP 134: SDRAM Controller QDR-II+ SRAM Xilinx has it working with Virtex-5 in hardware Evaluating market demand before releasing and supporting

34 Memory Interface Generator (MIG) 34 Free utility to customize an FPGA s memory interface Based on XAPP reference designs Specify different FPGA device, package, or speed grade Specify particular memory type, width, and performance Customized outputs include RTL source for the memory controller in Verilog or VHDL Simulation testbench and support User Constraint File (UCF) Pinout specific for chosen FPGA device/package Logic block locations FPGA timing constraints Batch file to run ISE tools in command line mode Timing analysis Documentation

35 Example MIG Design Flow Using Project Navigator Project Navigator Core Generator Complete Design MIG MIG Outputs Download Design to Hardware

36 MIG Output Block Diagram 36 Testbench Memory Controller Memory Calibration Clock Mgmt Clock MIG Outputs FPGA

37 Testbench State Machine 37 Power On Write Initialize Memory Compare Read

38 MIG 1.7 Main Menu (Virtex-5) 38 Burst Length CAS Latency Additive Latency ODT Enable (Rtt) Select desired FPGA banks Set SSO limit per bank based on WASSO calculator User s ucf file checked against pin placement rules Slide courtesy of Xilinx

39 MIG 1.7 Component Controllers 39 DDR DDR2 RLDRAM-II QDR-II SRAM DDR-II SRAM Virtex MHz 333 MHz 300 MHz Virtex MHz 300 MHz 250 MHz 250 MHz 250 MHz Spartan-3A 166 MHz 166 MHz Spartan-3E 166 MHz Spartan MHz 166 MHz Fastest clock rate in fastest FPGA speed grade

40 MIG 1.7 DIMM Controllers 40 DDR DDR2 Virtex MHz Virtex MHz 267 MHz Spartan-3A 133 MHz 133 MHz Spartan-3E Spartan MHz 133 MHz Fastest clock rate in fastest FPGA speed grade

41 Agenda 41 The FPGA/memory solution Memory technologies FPGA-based memory controllers Reference designs MIG EDK MPMC 3 rd -party MIG demonstration Conclusion

42 MIG Controller Generation Demonstration 42 Generate a DDR2 controller in MIG 1.7 Based on Spartan-3A FPGA Parameterize controller Generate and review controller files Demonstrate operation of DDR2 controller in ISE Project Navigator 9.1 Configure Spartan-3A with sample testbench design View user interface in ChipScope logic analyzer Verify data Tools ISE 9.1 MIG 1.7 Chipscope 9.1 Hardware used Spartan-3A Starter Board XC3S700A Xilinx FPGA MT47H32M16 Micron DDR2

43 Demo Summary 43 Project Navigator.. Core Generator 1 2 Complete Design MIG MIG Outputs Download Design to Hardware

44 Demo Results 44 Verify memory controller function Use ChipScope logic analyzer DDR2 review Write 20 data words Open Row (RAS asserted) Write (CAS and WE asserted) Close Row (RAS and WE asserted) Read Open Row (RAS asserted) Read (CAS asserted) Close Row (RAS and WE asserted)

45 Agenda 45 The FPGA/memory solution Memory technologies FPGA-based memory controllers Reference designs MIG EDK MPMC 3 rd -party MIG demonstration Conclusion

46 Xilinx Processor-based Memory Controllers 46 Xilinx supports memory interfaces for two embedded processors MicroBlaze soft processor Available in all Virtex and Spartan-3 FPGAs PowerPC hard processor Available in Virtex-II Pro and Virtex-4 FX Controllers are included in the Embedded Development Kit (EDK) Controllers connect to processor busses XCL (high-speed) or OPB (low-speed) in MicroBlaze PLB (high-speed) or OPB (low-speed) in PowerPC Memory controller performance limited by bus

47 EDK 9.1 Memory Controllers 47 Serial NOR Flash Parallel NOR Flash Standard Sync. SRAM ZBT / NoBL SRAM SDR SDRAM DDR SDRAM DDR2 SDRAM MicroBlaze XCL X X X X X X MicroBlaze OPB X X X X X X PowerPC PLB X X X X X X PowerPC OPB X X X X X X Spartan-3/3E/3A typical bus speed = MHz Virtex-4/5 typical bus speed = 100 MHz

48 EDK Memory Controller Summary 48 Advantages Seamless interface to processor Supported by Base System Builder (BSB) Very easy to use No logic location constraints Pin location constraints are more flexible Challenges DDR/DDR2 use more clocking resources than MIG 2-3 DCMs and 5-7 BUFGs may be consumed

49 MPMC2 49 Multi-Port Memory Controller (2 nd generation) Stand-alone or processor-based Example projects are all processor-based Features Supports SRAM, DDR and DDR2 SDRAM Supports multiple masters DMA capable Programmable arbitration Applications Gigabit System Reference Design (GSRD) Dual processor access to a single memory

50 Standalone MPMC2 50

51 Minimum DDR2 Controller Resource Usage 51 Slices DCMs BUFGs BRAMs Spartan-3A MicroBlaze CacheLink Spartan-3A MIG Virtex-4 PowerPC PLB Virtex-4 PowerPC MPMC Virtex-5 MIG

52 3rd Party Memory Controllers 52 Northwest Logic DDR3, DDR2, DDR, SDR, Mobile DDR, Mobile SDR, RLDRAM II, and FCRAM MemCore High performance controllers Denali Widely used DDR controller solution (Databahn )

53 Agenda 53 The FPGA/memory solution Memory technologies FPGA-based memory controllers Reference designs MIG EDK MPMC 3 rd -party MIG demonstration Conclusion

54 Conclusion 54 Xilinx provides a rich offering of memory controllers Numerous memory types supported Stand-alone and processor-based options All are free (with Xilinx tools) Solution = FPGA + IP + Memory Performance typically limited by FPGA or IP Memory speed is not the limiting factor Compare cost, resources, and performance MIG is a very valuable tool Creating a pinout Complete controller design

55 What s Next? 55 Contact your Avnet FAE Get Xilinx tools ISE WebPACK can be downloaded free Get controller info at Get a development board Create your own memory design Memory speedway scheduled for Fall