ASIC Prototyping 32MX16 DDR SDRAM XILINX XILINX FPGA F XC2VP70/100 (FF1704) BD 104. Overview and Selection Guide. Logic Emulation ROCKETIO EF 180

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1 SMB SMB LED0 MX TEST HEDER (00PIN) MX SMB SMB LED LED SMB ONFIGURTION USING RTMEDI Large boards from Primary / Bit, / PI Bus / PI-X Bus RTMEDI RD RTMEDI the D[0:7] world s & ONTROL leading supplier: /// MB ONFIG BIT FILES STTUS LED 'S controlled by LED LED ROKETIO 0 LED 0 LED B ROKET IO ROKET IO B XVP70/00 (FF70) BD 0 D XVP70/00 (FF70) DF 00 F XVP70/00 (FF70) U U U XVP70/00 (FF70) ROKET IO 0 XVP70/00 (FF70) ROKETIO 00 E XVP70/00 (FF70) U U U K X L U USB.0 RS LED7 LED LED PROGRMMBLE LOK SOUR X LOK SOUR JUMPER GRID JP MX USB MX ONFIG JUMPERS ROBOLOK PLL Y7BV U0 D 0 B 0 MB [ :0] USB MIRO- ONTROLLER X PP / DEBUG PP / DEBUG ROKETIO MX MX MX MX YPRESS M X Y7 MLV0B U (measured U the real way) 0 D D ED F 00 SI Prototyping MX MX MX MX ONFIGURTION SRM K X Y70V Short lead times (usually < - weeks) U SPRTN-II XS0 U LK[0..] The best reliability no cables or stacks of boards to shake apart RS PORTs (x) EF Logic Emulation Overview and Selection Guide (Short Version) ROKETIO 0 Standard, off-the-shelf boards and systems with one or many of the MU_D[0:7] biggest, fastest, newest, & baddest s (Xilinx or ltera) MU_[0:] Our largest board provides > million practical SI gates Ease of use High performance The lowest cost ISP PROM XV0 U SMB MX TEST HEDER (00PIN) P MX SMB SMB X B ROBOLOK PLL Y7BV U ONFIG JUMPERS BLK[0..] LOK INDITORS ROBO ROBO SERIL/ v.

2 OMPT ONFIGURTION Xilinx DDR SODIMM (GB max) DDR SODIMM (GB max) DDR SODIMM (GB max) onnector (0-pin) D 0 (P) onnector (0-pin) D onnector (0-pin) D DDR SODIMM (GB max) DIMM0 DIMM DIMM DIMM Mb Mb DDR SODIMM (GB max) DN000K0 Million SI gates DIMM Mb Mb DDR SODIMM (GB max) DIMM Mb MBV Mb = LVDS when paired, but can be run single-ended at reduced frequency onnector (0-pin) D MBH MBH onnector (0-pin) D onnector (0-pin) D onnector (0-pin) D7 onnector (0-pin) D v. QuickSwitch QuickSwitch MBH 7 0 MBLK Boot EPROM Y7 up uration controller lock Mux Reference lock GLK GLK D_ D_GLK D_GLK D_GLK SRM Kb x M x LX (FF) Single- lock RS PROM LD Panel Si Si serial port USB.0 RS Reset Ports (Tx/Rx) onnector (0-pin) PI0 External lock 's Si External lock 's Si External lock 's from Daughter ard (D) from Daughter ard (D) from Daughter ard (D) from Daughter ard (D) from Daughter ard (D) from Daughter ard (D) from Daughter ard 7 (D7) from Daughter ard (D) B D Q F E RJ RJ RS (bussed) LL s 0/00/000 (VS) connector (0-pin) connector (0-pin) connector (0-pin) 0/00/000 (VS) Reset LL s USB.0 ( Mb/s) RS (from ) OMPT Global locks Si Si Si uration Spartan up clock GLK GLK MB [:0] data DDR SODIMM QL0 DDR SODIMM QL0 D MB [:0] 0 0(0 ) LX0T T Mb Mb Mb Mb E B DDR SODIMM Mb Mb F DDR SODIMM DDR SODIMM DDR SODIMM Daughtercard D Daughtercard E Daughtercard F (zero delay) EXT (zero delay) MBLK PIe Express Endpoint PI Express - lane GEN -. Gb/s (-lanes) GEN -.0 Gb/s (-lanes) lternate SODIMM s:, DDR,, Test Points, DRM LL s USB PHY, RLDRM (LL DDR Sockets) Yellow (x0) = LVDS when paired, but can be used single-ended at reduced frequency v. B FBB E FBE 0 MHZ Ref_LK DN000K0PIe-T PIe GEN/GEN Fixed PIe controller with DM or prototype your own

3 LL s RJ RJ RS LL s 0/00/000 (VS) connector (0-pin) connector (0-pin) 0 connector (0-pin) 0/00/000 (VS) LL s 0 USB.0 ( Mb/s) RS OMPT uration Spartan up MB [:0] DDR SODIMM QL0 D MB [:0] E F 0 0 DDR SODIMM (from ) Global locks..0 clock GLK GLK DDR SODIMM QL0 7 Mhz PILK QL0 B DDR SODIMM DDR SODIMM DDR SODIMM PI ler Daughtercard D Daughtercard E Daughtercard F B E EXT MBLK FBB FBE / -bit PI.V/V / Bit /Mhz LL s Yellow (x0) v. DN000K0PI Million SI gates s, PI ux Power... +V +V GTP GTP lock (Si) lock (Si) lock (Si) EE 0 RS LK- LK QSE LK- LK- LK0- LK0- LEDs () Green = Differential when paired, but can be used single ended at reduced frequency ( Mbit) Ext lock User GTP DDR SODIMM T LX0T/T/0T SX0T/SXT (FFG) Battery + 00 (DDR) GTP GTP GTP GTP (Bottom) connector (0-pin) (Top) Infiniband SPF Socket (x) LK-QSE 0 QSE (LX0T/SXT only) v.0 DNMEG_VT Supports FXT SFP Modules enable all sorts of high speed serial phys --

4 Xilinx - LL s RJ RS LL s LL s DRM, SRM,, RLDRM DDR SODIMM 0/00/000 (VS0) USB.0 ( Mb/s) RS OMPT uration Spartan up MB [:0] LX0, LX0 or B LX0, LX0 0 clock Global locks. GLK 7 Mhz 7 QL0 (from ) PI ler connector (0-pin) connector (0-pin).0 +.V, +.V, +.V +.V, +.V, +.V Daughtercard / -bit PI +.V/V / Bit /Mhz = LVDS when paired, but can be run single-ended Daughtercard B (BOT) EXT = only MBLK v. DN00K0PI million SI gates, LX0, LX0 B F E D RJ D connector (0-pin) connector (0-pin) connector (0-pin) RJ F RS (bussed) LL s 0/00/000 (VS0) /00/000 (VS0) USB.0 ( Mb/s) RS Reset OMPT LL s uration up clock Ethernet MB [:0] data F D DDR SODIMM QL0 +.V I/O mac addr () User ( Mbit) 7 D Stratix SL D E Stratix SL x MB [:0] E LED F Stratix SL 7 mac addr () User ( Mbit) F x +.V I/O Main Bus onnector DDR SODIMM. B clock D F sourcing clk_tp single step clock (from ) clk_g0 from Si Khz to 00. Si Khz to 00. Si Khz to 00 MB clock clk_g0 clk_g clk_g clk_mb DDR SODIMM QL0 PIe Express Endpoint Stratix SL (0 ) User ( Mbit) x B Stratix SL x B User ( Mbit) Stratix SL x DDR SODIMM Daughter card D clk_ Daughter card F Daughter card E clk_ext PI Express - lane GEN -. Gb/s (-lanes) GEN -.0 Gb/s (-lanes) = LVDS when paired, but can be used single-ended at reduced frequency v. PIe endpoint clk_ref Global locks to all s DN700K0PIe-T million SI gates PIe GEN/GEN

5 connector (0-pin) ltera Stratix B RS USB.0 ( Mb/s) RS OMPT LL s (bussed) LL s uration Spartan up MB [:0] DRM, SRM,, RLDRM DDR 0 LX0, LX0 or 0 0/00/000 (VS0) DRM, SRM,, RLDRM DDR SODIMM B LX0, LX0 or clock Global 7. GLK 7 Mhz PILK QL0 (from ) PI ler connector (0-pin) connector (0-pin) Daughtercard Daughtercard B (top) Daughtercard B (BOT).0 GLK EXT / -bit PI +.V/V / Bit /Mhz = LVDS when paired, but can be run single-ended = only +.V, +.V, +.V +.V, +.V, +.V Top of PWB v.0 DN00K0PI million SI gates +.V, +.V, +.V RS B LL s LL s DRM, SRM,, RLDRM, DDR DDR SODIMM RJ 0/00/000 (VS0) USB.0 ( Mb/s) RS OMPT uration Spartan up clock. Gb/s 0 MB [:0] LX0, LX0 or (00Mb/s) 7 0 B LX0, LX0 0 (USB or PIe) Global locks 0 (USB or PIe) Si Si GLK 0 0 LX0T (FF) (from ) PIe ler connector (0-pin) connector (0-pin) Daughtercard Si clock synthesizers GLK PI Express PI Express. (. Gb/s) (or) PI Express.0 (.0 Gb/s) (with FXT) +.V, +.V, +.V = LVDS when paired, but can be run single-ended +.V, +.V, +.V v. = only EXT Daughtercard B 0 MBLK REFLK DN00K0PIe-T million SI gates PIe GEN/GEN - Fixed PIe controller provided --

6 DNMEG_Obs ccessories - the oth +V +V +.V () () () +V +V +.V Power LEDs +.V Linear v V_B0 v0 I/O Voltage (.V to +.V) Bank 0 Bank +.V 0-pin Header Linear I/O Voltage Rocket I/O ( hannel) MGTLK input (Rx/Tx) ( Pairs LVDS) V_B FI MEG-array Ball Grid onnector 00-pin ( Pairs LVDS) clk G GB -pin Header (0." pin spacing) Samtec ( Rocket I/O channels) G +.V Linear V_B _clk_out [P,N] Resistor Select Resistor Select Bank I/O Voltage -pin Header ( Pairs LVDS) 0-pin ( Pairs LVDS) -pin Header v.0 DNMEG_D_D ux Power +V +V EE DDR SODIMM connector (0-pin) D0 RS D D0 lock D D lock ID onverter -bit 0 MSPS (D0) D ID onverter -bit 0 MSPS LEDs () (D0) D Data 0 ( mbit) D Data Virtex LX, LX0 LX, LX00, SX (FF) Data hannel D B Data Digital to hannel nalog onverter -bit, 0 MSPS (D777) D lock v.0 DNMEG_DVI-0 External Power (stand alone operation only) PROM +V +V To p Bottom onnector (0-pin) Base Board onnections 0. Gb/s Rocket I/O (tx/rx) +.V +.V +.V +.V +.V MGT DVI Input (Dual-Link). MHZ Si Freq DVI TX0 SILB SILB clk 0 clk control & RESET PROM XF Virtex FX0/FX00 (FF) PP PP Rocket I/O DDR 00 SIL7 SIL7 hannel 0 DVI Output (Dual-Link). MHZ Freq DVI TX clk 0 clk control & Rocket I/O URT 0. MHZ Freq clk 0 clk control & LED's DDR SODIMM MGT RS Santec High Speed able onnector (QSE-DP) SFP socket v. LVDS when paired, but can be run single-ended at reduced frequencies.

7 DQ[:0] (:0) K K K WPS BWS K [:0] DK[7:] DQ[:] (:0) WPS BWS K K [:0] DQ[:] [7:0] [7:0] () ddress Register LK. Gen. Logic () ddress Register LK. Gen. Logic Read Data 7 Read Data 7 ddress Register Logic ddress Register Logic RPS () RPS () bank 0 (:0) Q Q Q [7:0] (:0) Q Q Q [7:0] bank bank bank bank bank bank bank 7 bank 0 bank bank bank bank bank bank bank 7 TMS TK TDI v.0 TDO S [:0] SDP SL ID PRom DV OE WE WP RST DV OE WE WP RST v.0 v. v.0 er stuff you need DNSODM00_QDR SODIMM Two QDR s chips in a x uration for a total of megabytes. The -bit input and -bit output busses are separate. Stuffed with the ypress Y7BV, the DNSODM00_QDR has separate input and output busses. Each bus is double data rate (DDR), allowing for very high performance reads and writes. With Xilinx Virtex- s from the LX or FX family, a -0 will operate at 7 (Mbits/s per pin). DNSODM00_RLDRM Two RLDRM s chips in an M x -bit uration for a total of megabytes. Stuffed with the two Micron MTHMs, all the features of RLDRMstyle DRM can be realized including non-multiplex addressing, double data rate clocking, and dramatically reduced data latencies.,* Q,Q* K* K* Write dd. Decode Write dd. Decode x rray x rray x rray x rray x rray x rray k x QDR RPS* Q,Q*,* RLDRM (Mxx) [:0], B[:0] DVLD (upper) DQ[:0] Memory rray DQS[:0] DQS[:0] * K K * S * WE * S * REF * DM[:0] x rray x rray Read dd. Decode k x QDR RLDRM (Mxx) DVLD (lower) DQ[:] Memory rray DQS[:0] DQS[:0] * K K * Read dd. Decode Data Data TDO TDI TDO v.0 DNSODM00_ The DNSODM00_ is an SODIMM module that can be installed in a 00-pin DDR SODIMM socket. This module contains two s chips in a M x uration for a total of megabytes. DNSODM00_ SODIMM Two Mictor connectors and three, -pin ID-type headers. Logic analyzers from Tektronix and gilent can be directly connected to pins enabling direct highspeed observation. DNSODM00_QUDMI SODIMM Four Mictor connectors. Logic analyzers from Tektronix and gilent can be directly connected to pins enabling direct high-speed observation. B[,B,,D] (lane enable) ddress [:] ddress [:0] DQ [:0] * WE * DV * OE * clk B[,B,,D] (lane enable) DQ[:] clk SD, SL, [:0] (Mx) [:] [:0] +.V DQ[:0] WE FT DV OE 00TQFP GS0V (Mx) [:] [:0] DQ[:0] +.V WE FT DV OE 00TQFP GS0V ID VDDSPD 7 0 (+.V or +.V) LED's [:] Mictor DQ[:0], [:0] Mictor DQ [:7], [:] DM [7:] DQS [:0]n." spacing DQS [:0]p.0" square -pin header DQS [7:]n DQS [7:]p DNSODM00_USB SODIMM USB.0 Phy for USB SO prototyping. enough to blind large farm animals..v IO DIP Switch LED ULPI USB OTG.V IO LED onnector SDIO ard Slot Voltage Translation Power onverter.v.v Power Monitor PM udio o/dec L/R Mic L/R Speaker Kb PROM DNSODM00_INTERON SODIMM signals on mm ID able headers for access. The signals can be used single-ended or differential. Termination resistors are provided to allow the use of standard ID cabling. Generally used for board to board interconnect. DNSODM00_SDR onnect a standard P SODIMM module (up to MB of Single-Data rate memory) to connect to the DDR socket. DNSODM00_ SODIMM Two Spansion chips (S7WSNB0BFWN0-LF) in an M x uration for a total of megabytes of memory. (M x ) is also provided on the same address/data pins via a separate chip select. DV* [:0] [:] (f)* OE* WE* WP* Reset* (s)* VB* lower LB* clk VB* upper LB* clk* S7WS0J0B M x k x S7WS0J0B M x k x RDY DQ[:0] DQ[:] DNSODM00_SE SODIMM One Mb flash and two Mb module SDRM chips. lso, an EPROM socket can hold a serial prom with densities up to Kb. U U DRM U DRM DQ0-0- DQ- D D D D D DNSODM00_DDR DDR-to-P700 adapter card. It allows a standard P700 SODIMM module (up to MB) to connect to a DDR SODIMM socket. Each module is tested at Mhz. DDR controller is not provided. -- 7

8 Speed Grades (slowest to fastest) LUT Size (-input or -input) FF's Gate Estimate Max (00% util) (000's) Practical (0% util) (000's) Max I/O's Multipliers (x) Multipliers (x) Blocks (kbits) Memory (kbits) (kbytes) Xilinx ltera Virtex- VirtexII Pro Stratix StratixII GX StratixII -,- -input 07,0,0,0, ,, LX LX0 -,- -input,,0,0 0 0, LX -,-,- -input 7,, 0 0, LX0 -,-,- -input,, ,0 7 LXTT -,-,- -input 7,, 0 7, LX0T -,-,- -input,,0 0, LXT LXT -,-,- -input, 0 0, LX0T -,-,- -input, ,0 70 LX0T -,-,- -input, , SXT -,-,- -input, 0,7,0 SXT SX0T -,-,- -input, 0,7 SXT -,-,- -input,70 0 0,0 7 FX00T -,-,- -input,000,0 0,0,0 FXT FX70T -,-,- -input, , FX0T -,-,- -input 0, 7 0 0, 0 LX00-0,- -input 7,7,0,0 0 0,0 7 LX LX0-0,-,- -input,,,0 0 0, LX00-0,-,- -input,0, 0 0 0,0 FX FX00-0,-,- -input,, ,7 FX0-0,-,- -input 0, ,7 LX0-0,-,- -input,,,0 7 0, LX00-0,-,- -input,0, 0 7 0,0 LX LX -0,-,- -input 7,, ,00 0 LX0-0,-,- -input, , 0 LX -0,-,- -input, 0 0 0,7 SX SX -0,-,- -input, ,70 70 vp00 -,- -input,, , vp70 -,-,-7 -input, ,0 7 vp0 -,-,-7 -input 7, 0 0 0,7 Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (00% util) (000's) Practical (0% util) (000's) MLB () MK ( kbit) MK ( kbit) (kbits) (kbytes) SL -,-,- -input 70,000,0, ,, SE0 -,-,- -input 0,000,, ,7, SL00 -,-,- -input 0,000,0, ,,7 M (x) MK (x) M-RM (kx) (kbits) (kbytes) SGX0E -,-,- -input 7,7,00 0, S -,-,- -input,0,00,0,70 0 7,, Max I/O's Multipliers (x) Memory The DINI Group 7 Draper ve. La Jolla, 07-0 Phone: () - Fax: () -7 sales@dinigroup.com