FPGA Boards ASIC Prototyping FPGA-Based High-Performance Computing Low Latency Trading. Nov v6.12c

Transcription

1 Boards ASIC Prototyping -Based High-Performance Computing Low Latency Trading Nov. v.c

2 TABLE OF CONTENTS TABLE OF CONTENTS Main Products Xilinx Virtex-7 DNV7FA: Feature Breakdown DNV7FA: Godzilla s Butcher DNV7FA: Twin of Godzilla s Life Coach DNV7FA: Godzilla s Life Coach Stacking the DNV7FA DNV7FB: Return of Twin of Godzilla s Life Coach Altera Stratix V DNSGX_F: Monster s Evil Interior Decorator Xilinx Kintex-7 DN_G_K7_LL : Xilinx Kintex-7 Son of Godzilla s Bad Hair Day DN_G_K7_LL_QSFP: Xilinx Kintex-7 Daughter of Godzilla s Bad Hair Day Alternate Memory -pin SODIMM Options IP IP - TCP Offload (TOE) IP - TCP Offload Engine IP - Sessions (TOE) IP - (Gen,,) Slowdown DN_Readbacker Virtex Ultrascale DN_G_KU_LL DNVU_F Specialty -pin SODIMM -pin SODIMM Options Virtex - 7 (using DINAR_SODM) Virtex - DNSODM_DDR_GB, DNSODM_ARMDEBUG, DNSODM_QDRII+, DNSODM IO DINAR_SOC DINAR Daughter Cards DN 7 DNMEG Daughter Cards DNIOB: High-Speed Serial Interfaces SEAM Expansion 9 Miscellaneous Peripherals High Performance Computing (HPC) DNK7F Cluster DNK7_F DNBFC_S Cluster DNBFC_S_ 9

3 WHO, WHAT, WHERE, WHY? Speed Grades (slowest to fastest) FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's Multipliers (x) Multipliers (7x) Multipliers (x) Blocks (kbits) Memory Total (kbits) Total (kbytes) Xilinx UltraScale Virtex-7 Virtex- Spartan - Kintex-7 Virtex Kintex V LX HXT SXT LXT LX VH VX VU -,-L,-,-,7,, 9,,,, 9,7, VU9 -,-L,-,-,,,,,, 7,, 7, VU -,-L,-,-,, 7,,7,,, 7,9,7 VU -,-L,-,-,,,7,,,, 9,7, VU9 -,-L,-,-,7,,,9 7,, 7, VU -,-L,-,- 9,9,, 7,,,9 VU -,-L,-,- 7,,7,,,,7 KU -,-L,-,-,,7, 7,,,,7 9,7 KU -,-L,-,-,9,,,,,, 7, KU7 -,-L,-,-,,9,9 7,9,7,7, KU -,-L,-,-,,,,7,,, KU -,-L,-,-,,,79,9,,,7 KU -,-L,-,-,,9,,7, 9,, 7VT -,-,,,,7,,,,, 7VT -,-,- 7,,99,,,9,,7 7VXT -,-,,,7,,,,7 7,, 7VX9T -,-,,,7 7,,,,,7 7VX9T -,-,-,,7,99,,,9,9, 7VXT -,-,- 9,,,99,,,, 7VXT -,-,- 7,,9, 7,, 7,, 7VXT -,-,-,,9,97,,7,,9 7VXT -,-,-,,97, 7,, 7,,7 7VH7T -,-,9,,, 7,,,7, 7VHT -,- 7,,9,,,,, 7KT -,-,- 97,,7,,9,9,,9 7KT -,-,-,,,,,7,,7 7KT -,-,-,,,9,,9,,7 7KT -,-,-,,7,,,,7, 7KT -,-,- 7,,9, 9,, 7KT -,-,-,,97,7,7, 7K7T -,-,-, 7 7, LX7 -L,-,- 9, 9,,9,,,9, LXT -L,-,- 7,,99,,,,7, LXT -L,-,-,-,,, 7,97,7 LXT -L,-,-,-,,9,7 7,97,7 LX9T -L,-,-,- 9,,9,,, LXT -L,-,-,-,, 9 9,, SX7T -L,-,- 9,,7,,,,,7 SXT -L,-,-,- 9,,7,9,,,, HXT -,- 7,,797,7 7,,, HXT -,-,- 7,,9,7 7, 7,, LXT -,-N,-,-,,,, LX -L,-,-N,-,,,, LX -L,-,-N,-,7, 79, LX7 -L,-,-N,- 9, 9 7,9 7 LX -L,-,-N,-,7, Who are you? The DINI Group was formed in May of 99. We started as a consulting organization specializing in and board-level design. We branched into ASIC design in 99, with particular emphasis in PCI and PCI-X. Our standard products are the direct result of unmet -based product needs discovered in our consulting practice. At present we have employees. Measured in numbers of gates shipped, we are the world s leading provider of ASIC prototyping hardware. What are your products? We make big boards. The most common application for big boards is ASIC and SOC prototyping. Big boards in specialized configurations can be used to accelerate certain types of algorithms. In other configurations, large boards can be used for high frequency, low-latency trading. Altera Stratix V E GX GS GT ArriaV GZ Stratix IV Stratix III Cyclone III Speed Grades (slowest to fastest) FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's MLAB () M9K (9 kbit) MK ( kbit) Memory MK ( kbit) Total (kbits) Total (kbytes) SEEB -,-,-,7,,79, 7,,, SEE9 -,-,-,,,7 7, 7,,, SGXAB -,-,-,7,,79, 7 79,,, SGXA9 -,-,-,,,7 7, 7,,, SGXA7 -,-,- 99, 9,, 7,,, SGXB -,-,- 9,,9, 79 7,,, SGXB -,-,- 7, 7,, 79 9,,, SGXA -,-,- 7, 7,,,,,7 SGXA -,-,-,,, 9,9,,7 SGXA -,-,-,,9, ,,9 SGSD -,-,-,,,, 9,7,, SGSD -,-,-,,,7,,, SGSD -,-,- 9,,,97 9,, 7,9 SGSD -,-,-,,, 9,,7, SGSD -,-,-,,,,,, SGTC7 -,-,- 99, 9,,,,, SGTC -,-,-,,,7,,,7 AGZME7 -,- 79,,, ,, AGZME -,-,,797, 7 7,, AGZME -,-,,, 97 9,,9 AGZME -,-,,,9,7, SE -,-,,7, 9,,9 SE -,-,-,9,799, 9,7,9 SL -,-,- 7,,,9 7 7,7, C -,-7 9,,7,, C -,-7,-, Multipliers (x) Where? We are based in La Jolla, California. La Jolla is about miles north of San Diego. Why? prototyping is rapidly becoming a requirement due to the complexity and costs of ASIC tapeouts and spins. However, boards require specialized teams to design and build: it is much easier and cheaper to buy off-the-shelf boards from those of us that already have that specialized set of skills

4 Feature Breakdown: DNV7FA HOSTING THE LARGEST EVER! Memory / Expansion / Stacking Memory / Expansion / Stacking DINAR DINAR -pin IDC -pin IDC DINAR DINAR 7 7.V I/O.V I/O 7 USB. / (device) QSPF+ for and GbE connectors for -lane GEN for GbE. Freq. Synth. Si GbE GbE or, GbE stack cable feedback IO Delay Expansion Socket Q (GEN) GCLK [:] // // baset Phy RJ RS USB. (X) x Host x Device A 7VX9T 7VT [F(F/H)G7] (Cabled GEN/GEN) Step Clock RGMII RS Config Clk USB DMA(x) SATA Gb/s Device Bus Virtex- Config (Gen) - lanes Marvell MV7 FPU FPU CPU CPU B 7VX9T 7VT [F(F/H)G7] SEAF (GEN) DN ( pins) Stacking M x DDR Mb Boot Global Clocks Config Clk Expansion Socket GbE (host) x RTC -lanes (GEN) Mb NAND Boot Add GbE, GbE et al with DNSEAM Expansion Cards (page 9) PCI EXPRESS Cable (GEN) 7VT Xilinx Virtex-7 s.the largest ever created. million ASIC gates plus memory and multipliers each! POWER! 7A per for VCCINT Marvell Processor running Linux hosts this board via USB.,, or GEN Global Clocks programmable to any frequency between KHz and 7 DINAR s Add memory (page ) Add custom peripherals Add off-the-shelf boards (page ) Stack two boards together (page ) We don t like hamsters and we don t think hamster cages belong in engineering labs! 9 7

5 DNV7FA: Godzilla s Butcher four Virtex-7 s 7VT million ASIC gates stackable x GbE or x GbE Expansion - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x x GbE or x GbE SATA (device) Q Expansion Q SATA (host) Memory / Expansion / Stacking DINAR DINAR top B Virtex-7 7VT (FLG9) bottom DINAR A Virtex-7 7VT (FLG9) DINAR Memory / Expansion / Stacking DINAR 7 7 C Virtex-7 7VT (FLG9) top D Virtex-7 7VT (FLG9) DINAR 7 7 bottom DINAR DINAR Expansion - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x Expansion x GbE (GEN/GEN) -lanes Hosted via - -lane GEN via cable, USB. - //BASE-T, or standalone Four Xilinx Virtex-7 s (FLG9) + million ASIC gates (ASIC measure) when stuffed with four 7VTs Memory can be added using DINAR_SODM on a DINAR expansion connector: - DNSODM_SSRAM (.V version) - DNSODM_QUADMIC (four Mictor connectors) - DNSODM_SE (mobile SDRAM) - DNSODM_USB (USB. PHY) - DNSODM_DDR_FAST - DNSODM_QDRII+ - DNSODM_DDR_GB - DNSODM IO (dual Mictor connectors) Marvell MV7 Discovery Innovation Dual CPU Five independent low-skew global clock networks and single fixed clock - Five, high-resolution, user-programmable synthe sizers for G, G, G Silicon Labs Si: khz to 9 - User-configurable via Marvell up RS, USB,, or - Global clock networks differentially distributed and balanced Flexible customization and stacking via daughter card positions per - DINAR expansion connector : non-proprietary; readily available; cheap - 7 LVDS pairs + clocks (or single-ended) - 7 on all signals with source-synchronous LVDS - Signal voltage set by daughter card (+.V to +.V) - Reset - Supplied power rails (fused): +V (W max), +.V (W max) - Pin multiplexing to/from daughter cards using LVDS (up to x) Fast and Painless configuration - USB, cabled,, - Standalone configuration with USB stick - Configuration Error reporting - Accelerated configuration readback for advanced debug RS port for embedded -based SOC up debug - Accessible from all s via separate -signal bus Full support for embedded logic analyzers via interface - ChipScope -controlled status s - Enough multicolored s to blind a hamster. Memory / Expansion / Stacking Memory / Expansion / Stacking SEAF RS (Cabled GEN/GEN) Step Clock Config Clk Virtex- Config DN ( pins) Global Clocks Stacking // // baset Phy RJ RS USB. (X) (host) x RGMII USB DMA(x) SATA RTC Device Bus PCI EXPRESS Cable (GEN) (Gen) - lanes Marvell MV7 FPU CPU CPU -lanes (GEN) FPU M x DDR Mb Boot Mb NAND Boot Virtex-7 Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Blocks (kbits) Total (kbits) Total (kbytes) 7VT -,- -input,,,,7,,,, Max I/O's Multipliers (x) Memory

6 DNV7FA: Twin of Godzilla s Life Coach two Virtex-7 s 7VT million ASIC gates stackable. Freq. Synth. Si GbE GbE or, GbE stack cable feedback // // baset Phy RJ RS USB. (X) = LVDS when paired, but can be run single-ended at a reduced frequency Expansion Socket Q IO Delay Memory / Expansion / Stacking DINAR 7 (GEN) GCLK [:] 7 x Host x Device (host) x (Cabled GEN/GEN) Config Clk Step Clock RGMII RS USB A 7VX9T 7VT [F(F/H)G7] DINAR 7 7 DMA(x) SATA RTC -pin IDC Gb/s Device Bus Virtex- Config (Gen) - lanes -lanes (GEN) PCI EXPRESS Cable (GEN) -pin IDC.V I/O.V I/O Marvell MV7 FPU FPU CPU CPU Memory / Expansion / Stacking DINAR 7 7 B 7VX9T 7VT [F(F/H)G7] SEAF (GEN) DN ( pins) Stacking M x DDR Mb Boot Mb NAND Boot DINAR 7 7 Global Clocks Config Clk Expansion Socket USB. /. (device) GbE Hosted via - -lane GEN via cable - USB. - //BASE-T - Standalone Dual Xilinx Virtex-7 + million ASIC gates (ASIC measure) when stuffed with two 7VT low-powered transceivers (assumes - speed grade or faster for GbE): - : sockets channels (device) USB. channels using connectors -lane GEN/GEN prototyping via cable Dual SEARAY Expansion headers, -lanes each.,cx, sockets or custom - : Q socket lanes GbE or single lane GbE socket channels (device) -lane GEN/GEN prototyping via cable Dual SEARAY Expansion headers, -lanes each,cx, sockets, or custom Marvell MV7 Discovery Innovation Dual CPU Five independent low-skew global clock networks - G, G, G, G, G - Five, high-resolution, user-programmable synthesizers for G, G, G, G and G - Silicon Labs Si: khz to 9 - User-configurable via Marvell up RS, USB,, or - Global clock networks differentially distributed and balanced Flexible customization via daughter card positions per - DINAR expansion connector - is non-proprietary, readily available, and cheap - 7 LVDS pairs + clocks (or single-ended) - 7 on all signals with source-synchronous LVDS - Signal voltage set by daughter card (+.V to +.V) - Reset - Supplied power rails (fused): - +V (W max) - +.V (W max) - Pin multiplexing to/from daughter cards using LVDS (up to x) - Support FMC, logic analyzer, memory expansion Fast and Painless configuration - USB, cabled,, - Standalone configuration with USB stick - Configuration Error reporting - Accelerated configuration readback for advanced debug RS port for embedded -based SOC µp debug - Accessible from all s via separate -signal bus Full support for embedded logic analyzers via interface - ChipScope -controlled status s - Enough multicolored s to illuminate a medium sized dungeon Virtex-7 V VX Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's (7) Multipliers (x) Blocks (kbits) Memory Total (kbits) Total (kbytes) 7VT -,- -input,,,,7,,,, 7VT -,-,- -input 7,,99,,,9,,7 7VX9T -,-,- -input,,7,99,,9,9, 7VXT -,-,- -input 7,,9, 7,, 7,, 7VXT -,-,- -input,,97, 7,, 7,,7 9

7 DNV7FA: Godzilla s Life Coach single Virtex-7 7VT million ASIC gates // // baset Phy RJ RS USB. (X) IDELAY Refclk Refclk (host) x. Frequency Synthesizer (Si). Frequency Synthesizer (Si). Frequency Synthesizer (Si) (Cabled GEN/GEN) Step Clock RGMII G G G RS USB.V DMA(x) SATA GBE -pin IDC.V RTC Device Bus PCI EXPRESS Cable (GEN) USB. /. Kintex-7 Config -lanes (GEN) Socket Socket Socket Socket (Gen) - lanes Marvell MV7 FPU FPU CPU CPU (device) Expansion M x DDR Mb Boot Mb NAND Boot clock Config Clk (GEN) (GEN) Virtex-7 7VX9T/7VT/ 7VT [F(F/L/H)G7] UDIMM (GB Max) (x) V DINAR DINAR DINAR -pin IDC (. ).V Hosted via - -lane GEN/ (v.) via cable - USB. - //BASE-T - Standalone Single Xilinx Virtex-7 + million ASIC gates (ASIC measure) when stuffed with 7VT low-powered transceivers (assumes - speed grade or faster for GbE): - sockets supports modules for any of the following interfaces: Gigabit Optical GBase-SR GBASE-LR GBASE-LRM GBase-ER Gigabit Copper GBASE-R direct attach Gigabit Sonet: GBase-LW Gigabit FibreChannel - (device) - USB. - channels using connectors - Dual, -lane GEN/GEN prototyping via cable - Dual SEARAY expansion headers, -lanes each CX sockets custom -pin UDIMM - 7-bit width (-bit with -bit ECC) - operation, PC- - Addressing/power to support GB (+ ECC) - Verilog/VHDL reference design provided (no charge) - Optional RLDRAM DIMM instead of for ultra low latency - Alternate pin-compatible memory cards available (consult factory for availability): SRAM: QDR, ASYNC, STD, or PSRAM, Flash DRAM: SDR, DDR, PSRAM or RLDRAM, DDR Mictor, USB PHY, Extra Interconnect Marvell MV7 Discovery Innovation Dual CPU Three independent low-skew global clock networks - G, G, G - Three high resolution, user-programmable synthesizers for G, G, G Silicon Labs Si: khz to 9 - User-configurable via Marvell up RS, USB,, or - Global clock networks differentially distributed and balanced Flexible customization via daughter card positions - DINARI expansion connector is non-proprietary, readily available, and cheap - 7 LVDS pairs + clocks (or single-ended) - 7 on all signals with source-synchronous LVDS - Signal voltage set by daughter card (+.V to +.V) - Reset - Supplied power rails (fused): +V (W max) +.V (W max) - Pin multiplexing to/from daughter cards using LVDS (up to x) Fast and Painless configuration - USB, cabled,, - Standalone configuration with USB stick - Configuration Error reporting - Accelerated configuration readback for advanced debug RS port for embedded -based SOC µp debug - Accessible from all s via separate -signal bus Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions -controlled status s - Enough multicolored s to light a fish tank. Virtex-7 V VX Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's (7) Multipliers (x) Blocks (kbits) Memory Total (kbits) Total (kbytes) 7VT -,- -input,,,,7,,,, 7VT -,-,- -input 7,,99,,,9,,7 7VX9T -,-,- -input,,7,99,,9,9, 7VXT -,-,- -input 7,,9, 7,, 7,, 7VXT -,-,- -input,,97, 7,, 7,,7 9

8 DNV7FA / DNV7FA: Chassis Photos DNV7FA/DNV7FA chassis without board DNV7FA/DNV7FA chassis with board installed 9

9 ..V I/O.V I/O -pin IDC -pin IDC.V I/O.V I/O... FPU FPU Stacking the DNV7FA four Virtex-7 s 7VT million ASIC gates Stacking two DINI Virtex-7 boards Two boards can be connected together to increase the amount of available resources. This example uses the DNV7FA. In this example, shown in figure, two DNV7FA cards are ganged together, seamlessly doubling the functionality. A memory module is added to each of the cards. The cable We use a custom Samtec cable, DINAR_CBL to connect the signals across the connectors of the two boards. You get these cables from us. The DINAR_CBL is a high-speed coax cable designed specifically to connect two -pin Samtec SEAM connectors together. We currently ship cables, but eventually we will have several different lengths. The busses: and The first cable, marked in Figure as, is required. This cable connects the busses together and adds a bus between the Config s on the two boards. The second bus is used to connect the busses from the slave card to the master card. Full functionality is maintained, including DMA movement between all s. Also, the host system sees all s as if they were placed on a single circuit board. The from the busses on the slave card must be re-clocked in the slave s Config, so this adds a few clock cycles of latency. The raw performance measured in terms of GB/s is not compromised. and other configuration of the slave DNV7FA is transferred over this second bus. Configuration of the slave board is also transparent to the host system and software. to Interconnect between boards The DNV7FA has expansion connectors, two per. These connectors are yellow in the block diagram and labeled through. When stacking two DNV7FAs, you can connect ANY DINAR expansion connector to any other DINAR expansion connector using a DINAR_CBL. It is perfectly reasonable to connect all four DINAR cables between the two DNV7FAs, but that would leave no expansion position open for memory or external peripherals. In the example shown in figure, I connected three of the expansion connectors together: DINAR (master DNV7FA) -> DINAR (slave) DINAR (master DNV7FA) -> DINAR (slave) DINAR (master DNV7FA) -> DINAR (slave) I chose these connections because it was easy to draw and not for any practical reason. Each of these cables carries 7 LVDS pairs, along with clocks, IDs and resets. I will state again: You can connect ANY DINAR connector to any other DINAR connector. Note that if you want to increase the interconnect between the s on a standalone DN- V7FA, you would not use the DINAR_CBL. Use the DINAR_INTERCON instead. Memory I added a DINAR_SODM to the spare DINAR connector on each DNV7FA. This card hosts a -pin SODIMM memory module. In the block diagram, I put an GB memory module in the socket. You aren t limited to. We have several other SODIMMs that work fine in this slot: DNSODM_SSRAM (.V version) (SSRAM) DNSODM_QUADMIC ( Mictor connectors) DNSODM_SE (Flash and Mobile SDRAM) DNSODM_USB (USB. Phy) DNSODM_DDR_FAST (DDR) DNSODM_QDRII+ (QDRII+ SSRAM) DNSODM_DDR_GB (more DDR, larger) DNSODM IO ( Mictors) Overview Figure shows the final functionality of the two DNV7FAs as seen from the host. + DINAR_CABLE Freq. Synth. Si Figure GbE or, GbE GbE GbE (device) USB. /. stack cable feedback Q Socket Expansion Expansion Socket IO Delay (GEN) DDR DINAR_SODM DINAR_SODM Config Clk DDR // baset RJ USB. (X) DINAR 7 7 (GEN) x Host x Device GCLK [:] RS (host) x Global Clocks // Phy Mb NAND Boot Mb Boot M x DDR DN ( pins) Stacking 7 7 DINAR RGMII to Interconnect RS USB DINAR_CABLE DINAR 7VX9T (Cabled GEN/GEN) Config Clk Step Clock SEAF 7 7 7VT [F(F/H)G7] 7VX9T 7VT [F(F/H)G7] 7 7 SATA CPU DMA(x) RTC (Gen) - lanes Gb/s -lanes (GEN) CPU FPU FPU Device Bus Virtex- Config PCI EXPRESS Cable (GEN) PCI EXPRESS Cable (GEN) Device Bus Marvell MV7 DINAR Virtex- Config (Gen) - lanes -lanes (GEN) Gb/s -pin IDC -pin IDC RTC Marvell MV7 FPU FPU CPU CPU SATA DMA(x) to Interconnect USB Config Clk DINAR_CABLE DINAR 7 7 7VX9T 7VT [F(F/H)G7] SEAF RGMII (Cabled GEN/GEN) RS Step Clock 7VX9T 7VT [F(F/H)G7] 7 7 DINAR DN M x DDR Mb Boot Mb NAND Boot // Phy Global Clocks RS to Interconnect 7 7 (host) x // baset RJ (GEN) x Host x Device 7 DINAR_CABLE DINAR (GEN) ( pins) Stacking 7 DINAR USB. (X) GCLK [:] Config Clk IO Delay Socket Expansion Expansion Socket Q stack cable feedback (device) USB. /. GbE GbE GbE or, GbE Si Freq. Synth. SLAVE MASTER Freq. Synth. Si Freq. Synth. Si GbE GbE or, GbE stack cable feedback Expansion Socket Q IO Delay // baset RJ USB. (X) = LVDS when paired, but can be run single-ended at a reduced frequency GbE or, GbE GbE GbE USB. /. (device) stack cable feedback = LVDS when paired, but can be run single-ended at a reduced frequency Figure Q Socket Expansion Expansion Socket IO Delay (GEN) // baset RJ USB. (X) Config Clk Memory / Expansion / Stacking DINAR 7 (GEN) (GEN) x Host x Device GCLK [:] RS (host) x GCLK [:] // Phy 7 x Host x Device RS (host) x RGMII // Phy S 7VX9T 7VT [F(F/H)G7] USB DINAR A 7VX9T (Cabled GEN/GEN) Config Clk Step Clock (Cabled GEN/GEN) Config Clk Step Clock GB SODIMM M 7VX9T 7VT [F(F/H)G7] RS RGMII 7 RS USB 7 7VT [F(F/H)G7] DMA(x) SATA RTC Device Bus DMA(x) SATA Gb/s Gb/s S PCI EXPRESS Cable (GEN) Virtex- Config RTC -pin IDC Gb/s Device Bus Virtex- Config PCI EXPRESS Cable (GEN) -pin IDC.V I/O.V I/O (Gen) - lanes -lanes (GEN) (Gen) - lanes -lanes (GEN) Marvell MV7 Marvell MV7 CPU CPU FPU FPU CPU CPU SEAF Memory / Expansion / Stacking M 7VX9T M x DDR DINAR S 7VX9T 7VT [F(F/H)G7] 7 7 DDR S GB SODIMM DDR 7VT [F(F/H)G7] Mb Boot Mb NAND Boot DN 7 7 SEAF (GEN) DN ( pins) Stacking B 7VX9T 7VT [F(F/H)G7] Global Clocks M x DDR Mb Boot Mb NAND Boot (GEN) ( pins) Stacking (GEN) 7 7 Global Clocks DINAR Config Clk Socket Expansion Expansion Socket Q Config Clk Expansion Socket (device) USB. /. GbE GbE GbE or, GbE USB. /. (device) GbE SLAVE MASTER

10 . A A Config DNV7FB: Return of Twin of Godzilla s Life Coach Dual Virtex-7 7VT million ASIC gates x GbE or x GbE x GbE Expansion - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x // // baset Phy RJ RS USB. (X) Type A USB. Type B (host) x Freq Synth Si Q A/B Memory / Expansion / Stacking DINAR CONTROL + STATUS Q CONTROL + STATUS A to DINAR_OBs A B Feedback from stacking Global Clocks GBE (Cabled GEN/GEN) RGMII A top 7 7 RS USB DINAR A DMA(x) SATA RTC A RS DCE bottom Device Bus RS DCE Virtex- Config (FFG) (Gen) - lanes Marvell MV7 FPU FPU CPU CPU Memory / Expansion / Stacking DINAR Memory / Expansion / Stacking B top 7 7 B DINAR A B DINAR DINAR CONTROL + STATUS Virtex-7 Virtex-7 CONTROL + STATUS 7VT 7VT (Cabled (FLG9) (FLG9) GEN/GEN) CONTROL + STATUS stacking G G G G G s (x) -lane s (x) (GEN via Cable) s (x) SIDEBAND CONTROL + STATUS B to DINAR_OBs SEAF DN ( pins) CONFIG M x DDR Mb Boot Mb NAND Boot B Expansion - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x Global Clocks CONFIG SIDEBAND Stacking x GbE Dual Xilinx Virtex-7 s (FLG9 package): 7VT-,- (fastest to slowest) + million ASIC gates (ASIC measure) when stuffed with two 7VTs Additional memory can be added using DINAR_SODM on a DINAR expansion connector: - SODIMM (native) - DNSODM_SSRAM (.V version) - DNSODM_QUADMIC (four mictor connectors) - DNSODM_SE (mobile SDRAM) - DNSODM_USB (USB. PHY) - DNSODM_DDR_FAST - DNSODM_QDRII+ - DNSODM_DDR_GB - DNSODM IO (dual Mictor connectors) low-power transceivers interfaces (- required for GbE): - A: sockets ( GbE) Q - channels GbE or single channel GbE Dual SEARAY Expansion headers, -lanes each - -lane, CX, sockets, USB.,, s - B: sockets ( GbE) -lane GEN/GEN prototyping via cable Dual SEARAY Expansion headers, -lanes each - -lane, CX, sockets, USB.,, s Five independent low-skew global clock networks and single fixed clock - Five, high-resolution, user-programmable synthesizers Silicon Labs Si: khz to 9 - User configurable via Marvell up RS, USB,, or - Global clocks networks distributed differentially and balanced Flexible customization and stacking via daughter cards positions per - DINARI expansion connector : non-proprietary; readily available; cheap - 7 LVDS pairs + clocks (or single-ended) - 7 on all signals with source synchronous LVDS - Signal voltage set by daughter card (+.V to +.V) - Reset - Supplied power rails (fused): +V (W max) +.V (W max) - Pin multiplexing to/from daughter cards using LVDS (up to x) Fast and Painless configuration - USB, cabled,, - Stand-alone configuration with USB stick - Configuration Error reporting - Accelerated configuration readback for advanced debug RS port for embedded -based SOC up debug - Accessible from all s via separate -signal bus Full support for embedded logic analyzers via interface - ChipScope Hosted via - -lane GEN (v.) via cable, USB. - //BASE-T, or stand alone Status -controlled s - Enough multicolored s to illuminate the coming zombie apocalypse Speed Gate Estimate Max Memory Grades Max Practical Multipliers LUT I/O's Blocks Total Total (slowest FF's (% util) (% util) (x) Size ('s) ('s) (9) (kbits) (kbits) (kbytes) to fastest) 7VT -,- -input,,,,7,,,, 9 9

11 DNSGX_F: Monster s Evil Interior Decorator dual Altera Stratix V s SGXAB. million ASIC gates Daughter Card Daughter Card CFG Cntl Cntl Cntl x // baset RJ x x x. Frequency Synthesizer (Si). Frequency Synthesizer (Si). GbE Frequency Synthesizer (Si) Global Clocks x host x device Cable (GEN ) RS RS USB (Type A) USB (Type B) (host) // Phy RGMII GCLK GCLK GCLK USB Frequency Synthesizer Frequency Synthesizer Frequency config Synthesizer Frequency config Synthesizer (Si) config (Si) config (Si) IOB_Clk IOB_Clk Config Stratix- SGXA, A, A, A7, SGSD, D, D (F7) CFG Clk Clk SATA Clk Si7 DMA(x) SATA RTC MPP Bus IOB Clocks (Si) (Gen) - lanes Marvell MV7 FPU IOB_Clk IOB_Clk CPU CPU -lanes (GEN) FPU PCI Express Cable (GEN ) SODIMM (GB Max) CFG Clk Out (x) Clk Clk Si7. GHz XCVR M x DDR Mb Boot Mb NAND Boot DC DC unidirectional LVDS when paired. Can be Clk connector (-pin) used single-ended at connector (-pin) reduced frequencies. Clk _CLK Si7 Stratix- SGXA, A7, A9, AB SGSD, D (F9) IOB Config OOB. GHz XCVR OOB IOB (x) IOB Options (each position): Gigabit (via CFP) Gigabit (via CFP) Quad Q ( GbE, GbE) Octal (GbE) GEN / GEN / GEN USB s A B (x) Stratix- SGXA, A7, A9, AB SGSD, D (F9). GHz XCVR OOB IOB config A B. GHz XCVR OOB IOB _CLK SODIMM (GB Max) - Position Dip Switch Cabled, -hosted logic prototyping system - - Altera Stratix V s SGXAB, A9, A7, A (largest to llest) -for logic prototyping SGSD,D -for signal processing - % resources available for user application.m+ ASIC gates (reasonable ASIC measure) with two SGXAB - 7, - x multipliers with dual SGSD (M gates of logic) configurable high-speed serial interface card slots (IOB), per - x. GHz serial links per slot - general-purpose I/O for out of band signaling (OOB) - Options interfaces include: GbE (via CFP module) GbE, Quad Q, Octal GEN/GEN, USB, s to interconnect is single-ended or LVDS - 7 LVDS chip-to-chip DDR with - speed grade (. Gb/s) - Reference designs for integrated I/O pad shift registers x to pin multiplexing per LVDS pair Greatly simplified logic partitioning Source-synchronous clocking for LVDS separate SODIMMs, PC- - -bit with addressing/power to support GB - Verilog reference design provided (no charge) VHDL on special request Marvell MV7 Discovery Innovation Dual CPU board-level global clock networks (GCLK[:]) - Separate programmable synthesizers for each network (Si) Ultra-low jitter khz - 7 User-configurable via USB,, et al. - Alternate clock sources: Config -single-step, divide for external clock insertion - Daughter Card global clock networks Allows insertion of global clock from daughter card x -pin MEG-Array connectors for daughter card expansion - signals - 7 on all signals with source-synchronous LVDS - Reset, presence detect - Supplied power rails (fused): +V (W max), +V (W max), +.V (W max) - Pin multiplexing to/from daughter cards with LVDS (up to x) Fast and Painless configuration - USB,, et al. - Integrated sanity checks on configuration files Custom base plate (standard) and optional rackmount chassis - Provides protection from those drooling engineers Full support for embedded logic analyzers via interface - SignalTap and other third-party debug tools Convert MEG-Array expansion connectors to interconnect with the DNMEG_Intercon. Enough status s to function as a bathroom nightlight Stratix- GS GX Gate Estimate Memory Speed Grades LUT Max Practical (slowest to FF's Size MLAB MK Total Total (% util) (% util) fastest) ('s) ('s) () ( kbit) (kbits) (kbytes) SGXAB -,-,- -input,7,,79, 7 79,,, SGXA9 -,-,- -input,,,7 7, 7,,, SGXA7 -,-,- -input 99, 9,, 7,,, SGXA -,-,- -input 7, 7,,,,,7 SGXA -,-,- -input,,, 9,9,,7 SGXA -,-,- -input,,9, ,,9 SGSD -,-,- -input,,,, 9,7,, SGSD -,-,- -input,,,7,,, SGSD -,-,- -input 9,,,97 9,, 7,9 Max I/O's Multiplier s (x) 9

12 DN_G_K7_LL Xilinx Kintex-7 Son of Godzilla s Bad Hair Day single Xilinx Kintex-7 QDRII+ and Cost-effective Low Latency Networking! separate GbE LAN/WAN using modules - Customized IP for packet analysis with minimum latency Hosted in a -lane GEN or GEN slot - -lane mechanical - Low profile, short length form factor Fully compatible with our OPTIONAL TCP Offload Engine (TOE/TOE) OPTIONAL FIX board support package (DN_FBSP). Functioning reference design with: - -Gigabit MAC - TCP/IP Offload Engine (TOE) - FIX protocol parser - Tick Filter (optional) - Interface (-lane, GEN) - Memory QDR II+ Controller Controller Xilinx Kintex-7 (FFG7) - 7KT-,-,-L (fastest to slowest) - 7KT-,-,-L - M ASIC gates (ASIC measure) when stuffed with Kintex-7 7KT k flip-flop/-input LUTs (7k total FFs).7 Kbytes total block memory (9, kbit blocks), x multipliers Bulk memory: Mini-uDIMM - 7-bit width (-bit with -bit ECC) -. operation, PC- (single rank) - operation, Mb/s, PC- (single rank) - Addressing/power to support GB - Verilog/VHDL reference design provided (no charge) Optimized controller for lowest latency bulk memory access - Optional RLDRAM Mini-DIMM instead of for ultra low latency QDRII+ SRAM memory: M x (7Mb) - Separate -bit read and write ports - bus operation, DDR (double rate) Fast enough to be clocked at. Eliminates clock synchronization delays between memory and clock SMBus-based thermal management GPS input for precise message time stamping and tracking Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions: Mentor Graphics, SpringSoft Noninvasive debug via register readback: DN_Readbacker -controlled status s - Enough light to make your houseplants happy Cost-effective Low Latency Networking! Kintex-7 Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's Multipliers (x) Blocks (kbits) Memory Total (kbits) Total (kbytes) 7KT -,-,- -input,,,9,,9,,7 7KT -,-,- -input 7,,9, 9,, 7KT -,-,- -input,,97,7,7, 9

13 DN_G_K7_LL_QSFP Xilinx Kintex-7 Daughter of Godzilla s Bad Hair Day single Xilinx Kintex-7 QDRII+ and Q Q socket - ports GbE LAN/WAN using modules OR - port GbE Hosted in a -lane GEN/GEN/GEN slot - -lane mechanical - Low profile, short length form factor - GEN/GEN bridge provided GEN supplied by user Fully compatible with our OPTIONAL TCP Offload Engine (TOE/TOE) OPTIONAL FIX board support package (DN_FBSP). Functioning reference design with: - -Gigabit MAC and GbE MAC - TCP/IP Offload Engine (TOE) - FIX protocol parser - Tick Filter (optional) - Interface (-lane, GEN) - Memory QDR II+ Controller Controller Xilinx Kintex-7 (FFG7) : - 7KT-,-,-L (fastest to slowest) - 7KT-,-,-L - M ASIC gates (ASIC measure) when stuffed with Kintex-7 7KT k flip-flop/-input LUTs (7k total FFs).7 Kbytes total block memory (9, kbit blocks), x multipliers Bulk memory: VLP Mini-uDIMM - 7-bit width (-bit with -bit ECC) -. operation, PC- (single rank) - operation, Mb/s, PC- (single rank) - Addressing/power to support GB - interface compatible with Vivado MIG Optimized controller for lowest latency bulk memory access - Optional RLDRAM Mini-UDIMM instead of for ultra low latency QDRII+ SRAM memory: M x (7Mb) - Separate -bit read and write ports - bus operation, DDR (double rate) Fast enough to be clocked at. Eliminates clock synchronization delays between memory and clock SMBus-based thermal management GPS input for precise message time stamping and tracking Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions Noninvasive debug via register readback: DN_Readbacker Eight -controlled s - Enough light to make your houseplants happy Cost-effective Low Latency Networking! Kintex-7 Speed Grades (slowest to fastest) LUT Size FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Max I/O's Multipliers (x) Blocks (kbits) Memory Total (kbits) Total (kbytes) 7KT -,-,- -input,,,9,,9,,7 7KT -,-,- -input 7,,9, 9,, 7KT -,-,- -input,,97,7,7, 9

14 Alternate Memory: -pin SODIMM SODIMM OPTIONS SODIMM OPTIONS DNSODM_RLDRAM-II SODIMM The DNSODM_RL- DRAM-II is a SODIMM module that can be installed in a -pin DDR SO- DIMM socket. This module contains two RLDRAM II chips in a M x -bit configuration for a total of megabytes. DNSODM_QUADMIC SODIMM The DNSODM_QUAD- MIC is a SODIMM module that can be installed in a -pin DDR SODIMM socket. This module contains four Mictor connectors. Logic analyzers from Tektronix and Agilent can be directly connected to pins to enable direct highspeed observation. DNSODM_INTERCON SODIMM The DNSODM_INTER- CON is a SODIMM compatible with all DDR SO- DIMM slots on Dini Group products. This module provides up to signals on mm headers for access. The signals can be used single-ended or differential. Termination resistors are provided to allow the use of standard IDC cabling DNSODM_SDR SODIMM The DNSODM_SDR is a DDR-to-PC adapter card compatible with Dini Group products with DDR sockets. It allows a standard PC SODIMM (up to MB of SDR memory) to connect to the DDR slot of your Dini Group emulation board. DNSODM_SSRAM SODIMM The DNSODM_SS- RAM is a SODIMM module that can be installed in a -pin DDR SODIMM socket. This module contains two SSRAM chips in a M x configuration for a total of megabytes. DNSODM_RLDRAM SODIMM The DNSODM_RL- DRAM is a SODIMM module that can be installed in a -pin DDR SODIMM socket. This module contains two RLDRAM chips in an M x -bit configuration for a total of megabytes. DNSODM_ SODIMM The DNSODM_ is a SODIMM that can be installed in a -pin DDR SODIMM socket. This module contains two flash chips in a M x configuration for a total of megabytes. DNSODM_SE SODIMM The DNSODM_SE is a SODIMM module compatible with all -pin DIMM slots on Dini Group products. The module contains one Mb flash and two Micron Mb SDRAM chips. An EPROM socket can hold a serial PROM with densities up to Kb. The DNSODM_SE is compatible with all Dini Group products equipped with DDR-SODIMM sockets. DNSODM_SSRAMx SODIMM DNSODM_USB SODIMM DNSODM_DDR SODIMM DNSODM_QDR SODIMM The DNSODM_SSRAMx is a SODIMM module that can be installed in a -pin DDR SODIMM socket. This module contains four SSRAMs chips in a M x configuration. The DNSODM_USB is a SODIMM. Provides a USB OTG physical interface (Standard ULPI). Also provides PCB audio, DIP switches, s, SD card, k serial non-volatile memory. The DNSODM_DDR is a DDR-to-PC7 adapter card compatible with Dini Group products with DDR memory sockets. It allows a standard PC7 SO- DIMM (up to MB) to connect to the SODIMM slot of your Dini Group Emulation board. The DNSODM_ QDR II+ is a SODIMM that can be installed in a -pin SODIMM socket. DNSODM_ SODIMM DNSODM_ SODIMM The DNSODM_MIC- TOR is a SODIMM module that can be installed in a -pin DDR SODIMM socket. This module contains two Mictor connectors and three -pin IDC-type headers. Logic analyzers from Tektronix and Agilent can be directly connected to pins to enable direct high-speed observation. The DNSODM_ is a SODIMM. Provides MB of DRAM memory ( interface arranged as x)

15 IP - TCP Offload (TOE) Overview FIX Data Stream TCP Offload (TOE) is -based IP that receives and transmits /IP/TCP packets on networks. TOE delivers payload, in order, to the user s application with: Input to Output GbE packet latency <us! GbE GbE Module TOE IP User Application Required IP (not included) Phy Xilinx LogicCore -Gigabit MAC Bridge RX TCP State Machine TX TOE User Algorithm Book Manage Fix Parser Trade Decisions Extra TCP/IP packet fields removed No missing Verified by appropriate CRCs and checksums Flow control The purpose is to offload the TCP/IP function from the CPU and perform it directly in -based hardware. TOE dramatically reduces the input to output response time and jitter by eliminating the need for host processor intervention when analyzing packets. This IP is designed to be utilized in -based high frequency, low latency Wall Street trading applications. Input to output packet latency of less than μs can be achieved. Assuming a -byte payload (-byte packet), the theoretical minimum input to output latency is about ns. / ASIC Host Running Linux TCP Offload Engine (TOE) IP for networking applications requiring minimum latency and deterministic latency Supplied as encrypted.ngc (Xilinx) or optional verilog source Integrated bridge (required) provided in encrypted.ngc format Complete simulation models and text fixtures Host CPU NOT involved in payload transfer - % CPU load during middle of TCP session - TCP packets handled by TOE not passed to CPU Full GbE line rate - No pause frames generated CPU required only for High complexity/low importance network features: - Setup/teardown of TCP session - ARP, ping, DHCP, SMTP, et. al. - Linux driver with C source included Layers,,, (link, network, transport, and session) Layers, 7 (presentation, application) is user s responsibility in MTU of bytes CRC validation and checksum validation - CRC validation - IP and TCP checksum validation Reordering of out-of-order packets Nagle algorithm Fast retransmit Congestion avoidance Packet retransmission upon error/lost/out of order packet reception TCP/IP session per instantiated TOE Additional TOEs can be cascaded to support multiple sessions - Limited only by resources Client or server mode Configurable TX and RX replay buffer - KB -> KB Protection Against Wrapped Sequences (PAWS) Configurable port number IPv with future upgrade paths to IPv/IPng - TBD (consult factory) TCP timestamps for congestion avoidance (optional) Configurable timeouts Initially targeted to the DINI Group DN_G_ HXT_LL with Virtex- HXT Cost reduced Kintex-7 version coming in early Q Altera Stratix- in Q Direct interface to the Xilinx Gigabit Media Access Controller (GEMAC) (required). -bit bus interface: - Synchronous FIFO clocked at.mhz - Optional asynchronous FIFO interface with - clocks cycles of added latency 9 9

16 IP - TCP Offload Engine IP - Sessions (TOE) Overview TCP Offload (TOE) is a -based IP that receives and transmits /IP/TCP packets on networks across simultaneous sessions. TOE delivers payload, in order, to the user s application with: Extra TCP/IP packet fields removed No missing Verified by appropriate CRCs and checksums Flow control For Latency Critical, -based Embedded Networking Applications The purpose is to offload the TCP/IP function from the CPU and perform it directly in -based hardware. TOE dramatically reduces the input to output response time and jitter by eliminating the need for host processor intervention when analyzing packets. This IP is designed to be utilized in -based high frequency, low latency Wall Street trading applications. Input to output packet latency of less than μs can be achieved. Assuming a -byte payload (-byte packet), the theoretical minimum input to output latency is about ns. TCP Offload Engine (TOE) IP for networking applications requiring minimum latency and deterministic latency Supplied as encrypted.ngc (Xilinx) or optional verilog source Integrated bridge (required) provided in encrypted.ngc format Complete simulation models and text fixtures Host CPU NOT involved in payload transfer - % CPU load during middle of TCP session - TCP packets handled by TOE not passed to CPU Full GbE line rate - No pause frames generated CPU required only for High complexity/low importance network features: - Setup/teardown of TCP session - ARP, ping, DHCP, SMTP, et. al. - Linux driver with C source included Layers,,, (link, network, transport, and session) Layers, 7 (presentation, application) is user s responsibility in MTU of bytes CRC validation and checksum validation - CRC validation - IP and TCP checksum validation Reordering of out-of-order packets Nagle algorithm Fast retransmit Congestion avoidance Packet retransmission upon error/lost/out of order packet reception TCP/IP session per instantiated TOE Additional TOEs can be cascaded to support multiple sessions - Limited only by resources Client or server mode Configurable TX and RX replay buffer - KB -> KB Protection Against Wrapped Sequences (PAWS) Configurable port number IPv with future upgrade paths to IPv/IPng - TBD (consult factory) TCP timestamps for congestion avoidance (optional) Configurable timeouts Initially targeted to the DINI Group DN_G_ HXT_LL with Virtex- HXT Cost reduced Kintex-7 version coming in early Q Altera Stratix- in Q Direct interface to the Xilinx Gigabit Media Access Controller (GEMAC) (required). -bit bus interface: - Synchronous FIFO clocked at.mhz - Optional asynchronous FIFO interface with - clocks cycles of added latency Does TCP/IP sessions in a single module (each session is a connection to other computer). 9

17 IP - (Gen,,) Slowdown Clock Slowdown DN_Readbacker Configuration Readback Top-Level Functional Diagram Pin Multiplexing Logic D SET Q SET D Q Logic CLR Q DATA_P/N[:] CLR Q DNLVDS_PINMUX_TX DNLVDS_PINMUX_RX clock clock CLK_SS_P/N Overview The Dini Group LVDS IO Pin Multiplexing design (DNLVDS_PINMUX) is intended to ease the strain of prototyping an ASIC design that spans multiple s by providing a low-latency IO pin multiplexing design. A latency of one clock cycle is achievable end-to-end, so the multiplexing essentially becomes invisible to the ASIC design. IO rates are maximized to allow for the highest internal frequency possible. Eye detection training and real-time eye monitoring are implemented inside the receiver module. MMCM System clock CLK Oscillator Noninvasive real time readback of register state - % coverage registers - complete readback/second - Running clock or single step IP block that throttles a PHY Interface to a slower frequency - Easier prototyping of logic - Frequency division by a factor to a maximum of - / ->. GEN (. Gb/s) and GEN (. Gb/s),, or -lanes MMCM - -bit or -bit per lane Signal Interface identical to the Intel PIPE specification - PHY Interface for the PCI Express Architecture (Version.) - No user MAC interface modifications required Support for power management and power state transition - L, Ls, L, L, L - Beacon signaling (L -> L) - Receiver detection Simulation models and example interface code provided. Overview The debug of -based designs is a difficult and time intensive task. Several techniques are available to aid in debug. One technique is to route internal nodes to external I/O pins and then observe those nodes on a logic analyzer or an oscilloscope. Another is to embed a logic analyzer in the. A problem with either approach is that knowledge of which signals to observe is required prior to place/route. Some tools have tricks to partially work around this issue. But by and large, if you want observability, you need to know ahead of time what signals you will want to observe. The DN_Readbacker adds no cost, noninvasive observation to all internal registers. When invoked, the DN_Readbacker tool reads back the register state of the (s), maps the resulting to the netlist, and outputs the result to a.vcd file. The readback can be looped and runs at about cycle/second. The.vcd file can then be analyzed visually using GTKWave or other.vcd file viewer. All s on the board can be read, along with all s in a seamless stack. Noninvasive real time readback of register state - % coverage registers - complete readback/second - Running clock or single step Works on all DINI Group Xilinx-based boards: - Xilinx UltraScale, Virtex-7/Kintex-7, Virtex- Output to standard.vcd file and displayed on GTKWave No RTL support required - Noninvasive observation of all registers - Not necessary to redo synthesis, or place/route 9

18 Virtex Ultrascale DN_G_KU_LL x GbE or x GbE GbE Q Time Sync (RS / RS / RS) GPS RLDRAM M x 7 RLDRAM M x 7 EEProm Rated as LVDS but can be used single-ended at a reduced frequency GTH Flash UltraScale KU/KU/ KU/KU7 (FFVA) -Lane GEN DDR Mx7 PCS-9 photo coming soon RS Config Flash ( Gbit) USB. (Type B) QSH Expansion Card GTH (board to board) USB Q socket - ports GbE LAN/WAN using modules OR - port GbE s sockets for GbE Hosted in a an -lane GEN/GEN/GEN slot - -lane mechanical - Low profile, short length form factor Fully compatible with our TCP Offload Engine (TOE/TOE) FIX board support package (DN_FBSP). Functioning reference design with: - GbE MAC and GbE MAC - TCP/IP Offload Engine (TOE) Up to sessions - FIX protocol parser - Interface (-lane, GEN) - Memory RLDRAM Controller DDR Controller Xilinx Kintex UltraScale (FFVA) - XCKU7-,-,- (fastest to slowest) - XCKU-,-,- - XCKU-,-,- - XCKU-,-,- M ASIC gates (ASIC measure) when stuffed with XCKU7 - k flip-flop/-input LUTs (k total FFs) -, Kbytes total block memory (,7, kbit blocks) -,9 multipliers, 7 x DDR Memory, GB - 7-bit width (-bit with -bit ECC) - operation, PC- with - or faster speed grade - DDR interface compatible with Vivado MIG RLDRAM, M x 7 (MB) - with - or faster speed grade SMBus-based thermal management GPS input for precise message time stamping and tracking - RS, RS, or RS interface Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions: Eight -controlled s - Enough debug s to illuminate a ll Koi pond. Cost-effective Low Latency Networking! Speed Grades (slowest to fastest) FF's Gate Estimate Max (% util) ('s) Practical (% util) ('s) Multipliers (7x) Blocks (kbits) Memory Total (kbits) Total (kbytes) KU7 -,-L,-,-,,9,9,9,7,7, KU -,-L,-,-,,,,7,,, KU -,-L,-,-,,,79,9,,,7 KU -,-L,-,-,,9,,7, 9,, 9

19 Virtex Ultrascale DNVU_F x x x GbE or x GbE GbE - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x // // baset Phy RJ RS USB. (X) (host) x RGMII Q Q. Frequency Synthesizer (Si). Frequency Synthesizer (Si). Frequency Synthesizer (Si) Expansion USB G G G DMA(x) SATA RTC PC- DDR M x 7 Device Bus -lanes (GEN) PCI EXPRESS Cable (GEN) DINAR A Ultrascale Virtex VU/9/ //9 (E9) TMB 7 7 Config -lane GEN TMB GEN Switch (PEX 7) GEN DINAR B Ultrascale Virtex VU/9/ //9 (E9) -lane PCE GEN (Gen) - lanes Marvell MV7 FPU FPU CPU CPU Rated as LVDS but can be used single-ended at a reduced frequency Virtex UltraScale -lane PCE GEN Speed Grades (slowest to fastest) M x DDR Mb Boot Mb NAND Boot FF's 7 7 -lane Gate Estimate Max (% util) ('s) Practical (% util) ('s) photo coming soon -lane GEN Multipliers (7x) PC- DDR M x 7 USB. (sst, type A) SATA x Blocks (kbits) GEN / - lane Expansion Memory Total (kbits) - -lane (GEN/GEN) - x CX XAUI Infiniband - x GbE et al. - x Q GbE - x USB./. A, B, AB - x - x Total (kbytes) VU9 -,-L,-,-,,,,, 7,, 7, VU -,-L,-,-,, 7,,7,, 7,9,7 VU -,-L,-,-,,,7,,, 9,7, VU9 -,-L,-,-,7,,,9 7,, 7, VU -,-L,-,- 9,9,, 7,,,9 Dual Xilinx Virtex UltraScale s (E9 package): - XCVU9-,-,- (fastest to slowest) - XCVU-,-,- - XCVU-,-,- - XCVU9-,-,- - XCVU-,-,- + million ASIC gates (ASIC measure) when stuffed with two XCVU9s Fixed, GB DDR memory bank for each - M x 7-bit (-bit with -bit ECC) - operation, PC- - DDR Verilog reference design provided via Vivado MIG (no charge) - Additional memory can be added using DINAR_SODM on DINAR expansion connector(s): - SODIMM (native), DNSODM_SSRAM (.V version) - DNSODM_QUADMIC (four mictor connectors) - DNSODM_SE (mobile SDRAM) - DNSODM_USB (USB. PHY) - DNSODM_QDRII+, DNSODM_DDR_GB - DNSODM IO (dual Mictor connectors) GTH/GTY low-power transceivers interfaces: - A: - sockets ( GbE) - Q (x GbE or x GbE) - x Serial ATA III (SATA ) - DNSEAM Expansion header: -lane, CX, sockets, USB.,, or s - B: - SuperSpeed USB. (type A connector) - -lane GEN via cables - DNSEAM Expansion header: -lane, CX, sockets, USB.,, or s -lane GEN via PEX7 Marvell MV7 Discovery Innovation Dual CPU - GHz clock - Dual USB. ports (Type B connector) - Dual Serial-ATA II connectors for external hard drives () - Gigabit interface - // GbE (RJ connector) - Sheeva CPU Core (ARM vte compliant) - Out-of-order execution - Single and double-precision IEEE compliant floating point - -bit Thumb instruction set increases code density - DSP instructions boosts performance for signal processing applications - MMU to support virtual memory features - Dual Cache: KB for and instruction, parity protected - L cache: KB unified L cache per CPU (total of MB), ECC protected. - GB external DDR SDRAM - Organized in a M x configuration - ( rate with DDR) - Two RS port for terminal-style observation and LCD control - After configuration, both CPUs dedicated entirely to user application - Linux operating system - Source and examples provided via GPL license (no charge) - ~ seconds to CPU boot Three independent low-skew global clock networks and single fixed clock - High-resolution, user-programmable synthesizers - Silicon Labs Si: khz to 9 - User-configurable via Marvell up RS, USB,, or - Global clocks networks distributed differentially and balanced Flexible customization and stacking via daughter card position - DINARI expansion connector, per - : non-proprietary; readily available; cheap - 7 LVDS pairs + clocks (or single-ended) - TBD on all signals with source synchronous LVDS - Signal voltage set by daughter card (+.V to +.V) - Reset - Supplied power rails (fused): +V (W max), +.V (W max) - Pin multiplexing to/from daughter cards using LVDS (up to x) Fast and Painless configuration USB, cabled,, Stand-alone configuration with USB stick Configuration Error reporting RS port (via USB) for embedded -based SOC up debug - Accessible from all s via separate -signal bus Full support for embedded logic analyzers via interface - ChipScope Hosted via - -lane GEN - -lane GEN/GEN via cable, USB. (on Marvell) - //BASE-T - Standalone Noninvasive debug via register readback: DN_Readbacker -controlled Status s Enough multicolored s to irritate, but not kill, a vampire

20 Specialty -pin SODIMM DNSODM_SSRAM SSRAM: Pipeline or NoBL A [:] DQ [:] ADV / LD BW [A, B, C, D] SSRAM A [:] DQ [:] ADV / LD BW [:] DNSODM_SE Mobile SDRAM, Flash Ck RAS * CAS * WE * address Mobile SDRAM WE CE [:] CEN ZZ OE CLK WE CE [:] CEN ZZ OE Ck M x Mobile SDRAM DQ [7:] BW [E, F, G, H] SSRAM A [:] DQ [:] ADV / LD BW [:] M x WE CE [:] CEN ZZ control address Flash (F) CLK OE A [:] NC (future expansion) M x CS, SI, SO, RST, WP, SCK Data Flash DNSODM_SSRAM_V SSRAM: Pipeline or NoBL, M x 7 +.V for Virtex-7, MB FC IIC SCL,SDA,SA,SA,VDDSPD Serial Cntl[CKEn,Wn,En,Gn,BWxn,ADV,ZZ,LBOn] A[:] DNSODM_SSRAM_V USB. Phy, Flash, NAND Flash Bank only CLK[:] BA Data ( Control) Nand Flash GSZ-xxxV Mb SSRAM M x NBT DQ[:7] To -pin DD SODIMM Data ( Control) Data USB PHY USB. (Mb/s) Header GSZ-xxxV Mb SSRAM M x NBT DQ[:] Data Header Flash Data ( Control) GSZ-xxxV Mb SSRAM M x NBT DQ[:] GSZ-xxxV Mb SSRAM M x NBT DQ[7:] DNSODM_QUADMIC Mictors DNSODM_DDR_FAST DDR: M x DQ [:] Ck Ck DDR M x DDR M x DDR M x DDR M x DDR M x DDR M x DDR M x DDR M x Addr Control (RAS, CAS, WE) 9 9

21 Virtex - 7 (using DINAR_SODM) Virtex - DINAR_SOC RGMII KSZ9RNX // RGMII Transceiver +VDC RJ // Base-T DNSODM_DDR_GB DNSODM_ARMDEBUG ARM Debug and Trace Interfaces ULPI Serial Data USB7 USB. Transceiver LTCCGN Dual RS Transceiver Power Switch USB. Dual DB9 Dual RS- DQ [:] ck ck MT7HM MT7HM Serial Audio Data /IC PCM79ARHBR Stereo Audio CODEC Mic In () Line Out Speaker Out (Stereo) DDR M x MT7HM DDR M x MT7HM DDR M x MT7HM DDR M x MT7HM DINAR Motherboard Header ( pins) SD Bus Clock Inputs Clock Outputs GPIO + OE/DIR.V<->.V Translators (with bypass for.v operation) IPCX SD Card Voltage Translator GP Bus GP Bus GP IIC Bus GP IIC Bus GP Inputs/Outputs SD/SDHC/ SDXC/SDIO Clock Inputs Clock Outputs DDR M x DDR M x 9 ARM MT7HM DDR M x MT7HM DDR M x DQ Controls DQ Address Controls x MT9FG GB ( Gb) NAND Flash x FAP MB (Gb) NOR Flash Addr control (RAS, CAS, WE) ATC IIC Bus KB (Kb) Bus ( Chip Selects) DNSODM_QDRII+ QDRII+: M x C,C* DNSODM IO Mictor, DIP Switch, I/O, +V tolerant,, IC -pin IDC AT KB (Kb) ATDL MB (Mb) Serial Flash NQAE MB (Mb) Serial NOR Flash D (7:) A (9:) CQ,CQ* CK* CK CK* CK DQ[:] WPS BWS [:] DQ[:] RPS* CQ,CQ* C,C* DK[7:] DQ[:] D (7:) A (9:) WPS BWS K K K K [:] Address Register CLK. Gen. Control Logic Address Register CLK. Gen. Control Logic () () Write Add. Decode Write Add. Decode Write Reg M x Array Write Reg M x Array Write Reg M x Array Write Reg M x Array Read Data Reg. Write Reg M x Array 7 Write Reg M x Array Read Data Reg. 7 Write Reg M x Array Write Reg M x Array Read Add. Decode Read Add. Decode M x QDR II+ SSRAM Reg. Reg. Reg. Reg. Address Register Control Logic Reg. Address Register Reg. RPS C C () A (9:) Q CQ CQ [7:] M x QDR II+ SSRAM Control Logic RPS C C () A (9:) Q CQ CQ [7:] CkP EVENTn RSTn A, A SCL SDA +.V Level Trans () (LC) I C Level Translator SCL SDA +.V (+V Tolerant) DIP Switches () External Clock Input I C Header Base-T/Base-T/Base-T Transceiver (.) - RGMII bus interface USB. Transceiver - Device, host, or On-The-Go device (OTG) - ULPI bus interface RS ports - DB9 connector -Bit, Low-Power Stereo Audio Codec (PCM79) - Microphone Bias - Headphone - Digital Speaker Amplifier Secure Digital Card Interface (SDIO) - I/O Voltage translation - Power ma@.v Single channel eternal clock input - Via dual s Single channel clock output - Via dual s Miscellaneous general-purpose I/O (+.V) - bits on -pin. IDC connector ( sets) Intended for - bits on -pin. IDC connector ( sets) Intended for IC - bits on -pin. IDC connector ( sets) Intended for GPIO of any sort ARM NAND Flash - MT9FG - Gb with -bit NOR Flash - FAP - Gb with -bit ATC - IC interface, Kb Bussed on a shared - - AT, Kb - Serial Flash - ATDL, Mb - Serial NOR Flash NQAE 9

22 DINAR Daughter Cards DINAR_SODM Add a -SODIMM memory module to any DINAR expansion connector DINAR_CBL Connect two cards together via a cable DINAR Expansion -bit SODIMM (GB Max) DINAR DINAR pin IDC SEAM SEAM (x) Regulator VTT +V Regulator.V.A DIMM VDD -pin module options are on page - DINAR_OBS +.V +V Power s Linear Reg Linear Reg Linear Reg Linear Reg Linear Reg +V +.V IODELAY Calibration Clock In.V s (X) VCCO_ (+.V) VCCO_ (+.V) VCCO_ (+.V).V DINAR Expansion Clock Out 9 9 Voltage Translate -pin IDC +.V User DIP Switch +.V +.V +.V VCCO_ VCCO_ GPIO GPIO -pin. IDC +.V -pin. IDC +.V Miscellaneous useful interfaces Adjustable I/O voltages via on-board regulators - separate banks individually configurable from +.V to +.V Status s: - Power: +V, +.V, +.V - user-controlled via pin Two Mictor connectors: single-ended signals each Two -pin dual row IDC headers - 9 single-ended signals - +.V Two -pin single row headers - single-ended signals - +.V Differential external clock inputs via s Differential external clock outputs via s -position DIP switch - position with Linear regulator for setting I/O bank voltage - per bank (total of ) 9

23 DINAR Daughter Cards DINAR_FMC-LPC Low pin-count FMC card transposer DINAR_INTERCON Add more -to- Interconnect DINAR 7 7 Converts two -pin, DINAR Expansion connectors into -to- interconnect - 7 pairs of length-matched LVDS or signals single-ended - s indicate status for resets, power rails, and VCC voltages - VccI/O regulators - Topside, Dual -pin, connectors for DINAR_Obs Observation Daughter card LVDS when paired, but can be run single-ended at a reduced frequency DINAR DINAR_K7_FMC-HPC DINAR to FMC HPC (VITA 7.) Active Transposer With Kintex-7 DINAR_HDMI_ETH_USB HDMI Receiver/Transmit with Kintex-7 M x HDMI RX HDMI FMC HIgh Pin Count - position DIP Clk_IN LA HA HB DP Clks Control GPIO Xilinx Kintex-7 7KT/7KT (FBG 9) 7 7 x (Green/Red) DINAR Expansion USB. RS (x) ARM (+.V tolerant) USB. Phy DINAR (x) USB7 Kintex-7 7KT/T/T (FFG7) (x) ADA7 HDMI TX AD7 (input) HDMI HDMI (output) - pin Serial EE clk Expansion // Base-T // BaseT KSZ RGMII Config External Power +V A B + V 9

24 DINAR Daughter Cards DN DINAR_USB_GPIO_SOC DINAR Expansion Card with the Kitchen Sink of SOC Peripherals (Industrial Version) DN_CONNECTOR Stacking transposer for connector CONNECTOR CLK CLK_IN CLK DINAR I C clk S.9 prog oscillator I/O Delay SODIMM ( bits only) DINAR Expansion Card with and OFNI. Flash DN_CONNECTOR_CLK _IN _OUT Converts SEAM connector to connector and bussing via cable between stacked boards Stacks up to boards Compatible with DN connector on the following products: DNV7FA, DNV7FA and DNV7FB. x DINAR cntl RGB (x) pin IDC NAND Flash ( Gb) ONFI. (MT9FG) GPIO (+.V) ARM CLK_IN _ CONNECTOR LVDS LVDS _ CLK_OUT CLK_OUT CLK_OUT CLK_OUT 9 7

25 DNMEG Daughter Cards DNMEG_OBS_III DNMEG_HAAPS EXT_osc smc connector -pin Aux (.v tolerant).v +.v SDIO Connect third-party peripheral boards using the Samtec ASP-- to Dini Group cards using this handi transposer..v.v HPI connector -pin ARM Header (+.v tolerant) -pin -pin IDC GPIO (.v tolerant) MEG-Array Expansion (-pin) Debug Header (Mictor for Logic Analyzer).v I S Audio Codec PCM79.v MIC (L & R) Speaker (L) Speaker (R) MEG Array Virtex- and Stratix- ( diff pairs) Altera Banks - ( diff pairs Rx CLK) or LVCMOS signals I C Interface FETs +.V PSU +.V Power HAPPS (Samtec) IDC Reset Button MAX 7 MAX RS Reset Switch.v +.v SDIO - MicroSD Card Adapter DNMEG_ETHERNET Add multiple high speed connections to Dini Group boards with this adapter. DNMEG_LCDDRIVER The DNMEG_LCDDRIVER board is a converter from LVCMOS to 7x rate LVDS signals with an appropriate pattern for LCD panels. Analog In DC Phono Jack MEG Array. THS9 Diff. Amp xfrmr couple ADC_Clkout DC sel +.V /-bit ADC ADC ADS7 ( bits) or ADS ( bits) () MEG Array ( - pin) RGMII Video DAC -bits ADV RS // Base-T Phy (RTLCL) // Base-T -pin IDC Header Phono Jack -pin SCSI Style -pin IDC 9 9

26 DNMEG Daughter Cards DNMEG_SODIMM_SOCKET The DNMEG_SODIMM_ is a daughter card intended to add four Hynix flash memories and a DDR SODIMM to any expansion slot on an board from The Dini Group. A -pin TSOP socket is used, allowing the flash memories to be programmed by an off-the-shelf flash programmer. The Hynix HYUGg is the target flash device, but connections are provided to allow the use of almost any flash chip in a -pin TSOP package. The interface to all flash memories is easily debugged using a logic analyzer cabled to two Mictor connectors. The two Mictors are connected to all four of the flash memory s address,, clock, and control signals. A wide variety of SODIMMs can be used with this daughter card. MEG - Array Expansion (-pin) Addr 9 Data Control DDR SODIMM (GB Max) Socket (TSOP) Addr Data Control DNMEG_SOCKET The DNMEG_Flashsocket is a daughter card intended to add a single Hynix to any expansion slot on boards from The Dini Group. A -pin TSOP socket is used, allowing the flash memory to be programmed by an off-the-shelf programmer. The Hynix HYUGG is the target flash device. We also provide connections to enable use of almost any chip in a -pin TSOP package. External Clock Input MEG - Array Expansion (-pin) Addr (Control) Data Addr (SDRAM) 7 Control (SDRAM) Clk = LVDS when paired, but can be used single-ended at a reduced frequency Socket (TSOP) -pin SCSI-Style I/O Micron Mobile SDRAM I/O Addr (Control) Addr (SDRAM) Data Control (SDRAM) -pin IDC -pin IDC -pin IDC DNMEG_EXT The DNMEG_EXT riser card is a passive card that allows all signals to pass through. It raises a daughtercard by mm and is also useful for connecting multiple daughtercards. It is compatible with all Dini Group boards and daughtercards with MEG-Array connectors. DNMEG_OBS The DNMEG_Obs Observation Daughtercard is a complete solution for observation of signals on a -pin or -pin FCI MEG-Array connector and is used with the DNK-series, DN7K-series, DN9K- series, and other -based products from The Dini Group. +V +V +.V (A) (A) (A) +V +V +.V Power s +.V Linear Regulator I/O Voltage Control (.V to +.V) VCC_B v v Bank Bank +.V -pin Header Linear Regulator I/O Voltage Control ( Pairs LVDS) VCC_B FCI MEG-array Ball Grid -pin ( Pairs LVDS) -pin Header (." pin spacing) Rocket I/O ( Channel) MGTCLK input (Rx/Tx) clk GCA GCB Samtec ( Rocket I/O channels) GCC V Bank Linear Regulator I/O Voltage Control -pin Header VCC_B ( Pairs LVDS) -pin _clk_out [P,N] ( Pairs LVDS) -pin Header Resistor Select Resistor Select v.

27 DNMEG Daughter Cards DNMEG_VT_ The DNMEG_VT_PCIE allows an additional PCI Express interface to be added to any Dini Group board, including the DN9K. It connects to a base-board using the high-speed MEG- daughter card interface and can also be used standalone. In addition to two -lane cable interfaces, this card is equipped with an SFP, four RX/TX channels via s, and one x DisplayPort Source/Sink. DNMEG_SGX The DNMEG_SGX is a daughter card that enables ASIC or IP designers to prototype logic and memory designs for a fraction of the cost of existing solutions. Of the available high-speed channels, four are connected to SFPs, four to s, and four to SATA connectors. PROM DDR SODIMM (GB Max) Mictor AUX Power connector +V A.V Switcher +.V A +.V Switcher Clock Input CLK_ ByteBlasterII +.V to +.V I/O connector (-pin) Daughter Card to all: } DN DN9 Series Products DN7 Bottom Top connector (-pin) step (From ) -- FX7T SX9T FXT only LXT } LXT. Clock Synth Si KHz to. Clock Synth Si KHz to. Clock Synth Si KHz to = LVDS when paired, but can be used single-ended at reduced frequency 9 9 clkmult clkmult clkmult XCF Config PROM Flash (Mb) EXT_clk DDR Virtex-T LXT/LXT/SXT/ FX7T/SX9T/FXT LXT/LXT (FF) User 's () 7 RS DisplayPort (Source) pairs DisplayPort (Sink) pairs SFP Socket Cable ( - ) Cable Adapter Board Cray/Sun/Intel/HP/et al. Slot (-lane) 9. freq_sel (DDR clock) User clock socket Clock synths (ICS).. optional fixed frequency (not stuffed) 7. or. = Differential, but can be used single-ended at a reduced frequency user 's () Configuration Flash Serial Flash DDR SODIMM (GB Max) 9 9 Stratix II GX SGX9E (FF) (Rx/Tx) Host Peripheral SFP socket SFP socket SFP socket SFP socket RS SATA Interface RS Level Translator DNMEG_AD_DA The DNMEG_AD-DA is intended to be a peripheral daughter card to our ASIC emulation products, but can be used standalone with an inexpensive ATX power supply. It allows designers two DAC channels and two ADC channels for Analog-to-Digital or Digital-to-Analog communication. DNMEG_G_SSRAM Add Gb of SSRAM to Dini Group boards with this adapter. Aux Power +V +V EE DDR SODIMM (GB Max) +.V to +.V I/O connector (-pin) ADC RS 9 AD ADC Clock AD ADC Clock AID Converter -bit MSPS (AD9) ADC AID Converter -bit MSPS (AD9) s () AD Data Serial Flash ( mbit) AD Data Config Virtex LX, LX LX, LX, SX (FF) A Data Channel DAC B Data Digital to Channel Control Analog Converter -bit, MSPS (AD97) DAC Clock 9

28 DNMEG Daughter Cards DNMEG_INTERCON The DNMEG_Intercon is a daughter card that bridges the expansion signals between two -pin MEG-Array connectors, adding 9 pairs of LVDS signals for to interconnect. At a lower frequency, the 9 pairs can be used as signal ended signals. Linear regulators needed to drive the VCCIO voltages are provided, along with several s for power presence and reset activity. DNMEG DIFF The DNMEG_Mictor_Diff daughter card is a solution for connecting your Dini Group board to a differential (read: NON-AMP) Mictor interface. The PCB is routed for maximum differential throughput and the connectors are pinned out to minimize crosstalk between pairs. I/O Bank reference Voltage B_RST +.V Ref VCCO Bank Ref VCCO Bank Ref VCCO Bank +.V B +.V B +.V B -pin MEG-Array connector (P) pin MEG-Array connector (P) T_RST ma -pin MEG-Array connector (P) +V +V +.V - LVDS when paired, but can be used single-ended at reduced frequencies DNMEG_DVI The DNMEG_DVI- provides dual-link input and dual-link output Digital Video Interface (DVI) functionality. External Power (stand alone operation only) DVI Input (Dual-Link). MHZ. MHZ. MHZ Config PROM Si Freq Synth DVI TX Freq Synth Freq Synth DVI TX MGT +V +V SILB SILB clk clk control & config clk clk control & config clk RESET clk control & config Top Bottom (-pin) Config PROM XCF MGT Virtex FX/FX (FF) PPC PPC Rocket I/O 9 9 Santec High Speed Cable (-DP) Base Board Connections UART Rocket I/O 's. Gb/s Rocket I/O (tx/rx) DDR SFP socket SIL7 SIL7 Channel DDR SODIMM LVDS when paired, but can be run single-ended at reduced frequencies. RS Switching Regulator Switching Regulator Switching Regulator Switching Regulator Switching Regulator +.V +.V +.V +.V +.V DVI Output (Dual-Link) DNMEG_VT The DNMEG_VT enables engineers to utilize the Xilinx Virtex-T for high-speed serial interconnect. It is hosted on any Dini Group ASIC Emulation product that has MEG-Array expansion capability but can also be operated in standalone mode with a separate power supply. s for the high-speed MGTs include four channels (Rx/Tx), one x Infiniband connector, four SFP sockets, and four high-speed channels on a connector. Aux Power +V +V EE RS. Clock Synth Si. Clock Synth Si. Clock Synth Si s () Green = Differential when paired, but can be used single ended at reduced frequency = SX9T, FX7T, FXT, LXT, LXT only = Flash Configuration CLK- CLK CLK- CLK- ClK- CLK- Serial ( Mbit) EXT Clock user DDR SODIMM (GB Max) Virtex-T LXT/LXT/SXT SX9T/FX7T/FXT LXT/LXT (FFG) Config Battery + (DDR) CLK- Infiniband (LXT/ SX9T only) +.V to +.V I/O connector (-pin) 9 (bottom) (top) SFP Socket (x) - TX Fault - MOD_DEF - RATE_SEL - LOS SFP Signals not available with LXT, LXT, SXT 9

29 DC DC DDR SODIMM (GB max) 9 9 Virtex- LX (FF7) Virtex- LX (FF7) Virtex- LX (FF7) Virtex- LX (FF7) DDR SODIMM (GB max) DIMM DIMM DIMM DIMM Serial Mb Serial Mb DDR SODIMM (GB max) Virtex- LX (FF7) Virtex- LX (FF7) 9 Virtex- LX (FF7) Virtex- LX (FF7) DDR SODIMM (GB max) DIMM Serial Mb Serial Mb DDR SODIMM (GB max) Virtex- LX (FF7) Virtex- LX (FF7) Virtex- LX (FF7) Virtex- LX (FF7) DDR SODIMM (GB max) DIMM Serial Mb MBV Serial Mb +.V to +.V I/O DC (-pin) Virtex- LX (FF7) 7 Virtex- LX (FF7) Virtex- LX (FF7) Virtex- LX (FF7) 9 9 (-pin) +.V to +.V I/O DC9 9 9 MBH MBH 9 9 DC DC DC7 DC QuickSwitch QuickSwitch MBH Control CY7C up Configuration controller Control MBCLK Reference Clock GCLK GCLK GCLK DC_GCLK DC_GCLK DC_GCLK DC_GCLK SRAM Kb x Flash M x Config LX (FF) Single-Step Clock USB. RS COMPACT CONFIGURATION Reset 9 9 Serial Ports (Tx/Rx) Config PROM LCD Control Panel PCI Clock Synth Si Clock Synth Si External Clock 's Clock Synth Si External Clock 's Clock Synth Si External Clock 's from Daughter Card (DC) from Daughter Card (DC) from Daughter Card (DC) from Daughter Card 9 (DC9) from Daughter Card (DC) from Daughter Card (DC) from Daughter Card 7 (DC7) from Daughter Card (DC) DNMEG Daughter Cards DNMEG_DOUBLE Connect two DNV_FPCIE cards together. Also works for other cards in the V line of Dini Group products. DNMEG_FMC The DNMEG_FMC board is a Mezzanine card. +.V I/O Bank Reference Voltage +V Ref VCCO Bank Ref VCCO Bank Ref VCCO Bank ma External Clock Input +.V +.V +.V +V +.V B B B p p -pin MEG-Array (P) 9 9 -pin IDC Headers (x) 9 9 -pin MEG-Array (P) 9 9 = LVDS when paired, but can be used single-ended at reduced frequencies -pin MEG-Array (P) B_RST T_RST (VCCO regulators set to +.V, for MEG Array Signals) LDO +VADJ Power MEG Array SelectIO Pins Clocking IIC (Level Translators) +VIO (VCCO FOR HB Signals Only) s for Clock Insertion CLK_UP (CM) CLK_DN (MC) Power monitors, daughtercard reset Xilinx Header Headers PG_MC, PSNT_MC PG_CM LA/HA/HB Banks +VADJ HS Serial (DP) Clocking Sideband Power s for Status, Power DNMEG_HSMC Connect High-Speed Mezzanine Card (HSMC) to Dini Group boards with this adapter. (VCCO regulators set to +.V, for MEG Array Signals) LT9A Power MEG Array Bank # Bank # Bank # Bank # IIC IIC (Level Translators) Altera Header Probe Points Probe Points HS Serial LVDS LVDS HSMC # HSMC # Power Power DNMEG_ARM_TILE The DNMEG_ARM_TILE is an intermediate host for an ARM RealView CoreTile. It adds the features and interfaces necessary to make the ARM9 (or ARM) processor useful for prototyping. The combination of the DNMEG_ARM_TILE with the CoreTile can be mounted on an ASIC board from The Dini Group, enabling full-speed system prototyping and debugging of high gate-count ARM-based systems. With a separate power supply, the DNMEG_ARM_TILE/CoreTile combo can also be used standalone. CPLD (XC97) ARM7 / ARM9 / ARM ARM Test Chip ARM Coretile Z Memory Expansion PISMO Y Memory Expansion PISMO Y[:] Y[9:] Misc Control (power, clocks, memory type/sizes, board ID, etc.) HWDATA[:] (quickswitches) HDRZ HDRY HDRX MEMEXPB [:] MEMEXPA [:] GPIO HADDR[:] HDATA[:] HRDATA[:] Bus Control CPLD Config Clocks, Misc control ARM ICE Config ARM ICE Debug (x) AHB 9 Xilinx Spartan XCS (FG9) Addr Data Cntl Addr Data Cntl Addr Data Cntl 7 SDRAM M x (/ MBIT) (AT 9BVD) M x SSRAM (k x ) CY7C D AC97 Audio SoundMAX Codec (ADA) Mouse RS Keyboard CD Audio Line Out Headphone In s for GCC Insertion s for Status, Power (Level Translators) Altera Header Probe Points Probe Points HS Serial DN9 & DN7 Series ASIC Prototyping Boards (to M gates) (-pin) +.V to +.V I/O (-pin) (-pin) (-pin) +.V to +.V I/O +.V to +.V I/O +.V to +.V I/O Clock Mux (-pin) +.V to +.V I/O (-pin) USB-OTG Phy (USB ) Config // Phy (UCS) USB. (mini AB) RJ // base T (-pin) +.V to +.V I/O (-pin) +.V to +.V I/O () EE 9 7

30 SCL SDA TX RX TX RX TX RX ( to ) OOB_TX [:] OOB_RX [:] cntl position Cage x Cage misc OOB signals optional x Cage CPLD DNIOB: High-Speed Serial Interfaces SEAM Expansion DNIOB_CFP DNSEAM_IPASSx Add ipass connection to any Dini Group board with a SEARAY connector. DNIOB_ -lane Socket (GEN - consult factory) DNIOB_QSFP IOB Cable Cable -lanes GEN / GEN (Consult factory for GEN) DNSEAM_CX Add CX connection to any Dini Group board with a SEARAY connector. DNIOB_ DNIOB_ Bank clk Bank clk Bank clk IOB Expansion I C I C I C I C Mux (x ) OOB CPLD (x ) OOB x (cage ) x (cage ) x (cage ) (x ) OOB DNSEAM_ Add an -lane GEN/GEN PCI Express connection to any Dini Group board with a SEARAY connector. DNIOB_INTERCON DNIOB_USB DNSEAM_SFP Expansion card that hosts SFP sockets. Attaches to the SEARAY Expansion connectors on the DN7k, DNVF, DNMEG_VHXT. Adds channels of x/x/x Fibre Channel, //G, XAUI, SATA, Serial RapidI/O (SRIO)

31 D COMPACT config SEAM Expansion Miscellaneous Peripherals DNSEAM_MISC USB. interfaces channels of with connectors I interfaces fixed oscillators with jumper selectable frequencies DN_USB SB o-b) USB to Diligent SMT TDI TMS TCK TDO TDI TDO TMS Xilinx TDI TDO TMS TDI TDO TMS USB to Adapter for in-chassis reconfiguration TDI TDO TMS TCK +V DN-SATA -lane Express to Serial ATA adapter DNSEAM_SFPPLUS SEAM Expansion card with sockets. - GbE Ref Clock External Input 7 -lane SATA ( Gb/s) SATA ( Gb/s) SFP SFP s A B C RJ +.V to +.V I/O RJ +.V to +.V I/O +.V to +.V I/O Q F E // ETHERNET (VSC) connector (-pin) connector (-pin) connector (-pin) ALL s RS // ETHERNET (VSC) (bussed) ALL s Reset DDR SODIMM (GB Max) Mb Mb Mb F Virtex LX (FF7) MB [:] E Virtex LX (FF7) D Virtex LX (FF7) Configuration QL DDR SODIMM (GB Max) Spartan 7 7 MB [:] up Config Control Config RS USB. ( Mb/s) config DDR SODIMM (GB Max) clock config Mb Mb Mb C Virtex LX (FF7) B Virtex LX (FF7) A Virtex LX (FF7) Global Clocks Step QL DDR SODIMM (GB Max) GCLK Clock Synth Si Step 9 9 ( ) GCLK Clock Synth Si CLK_FB (from A) DDR SODIMM (GB Max) DDR SODIMM (GB Max) Xilinx Virtex T LXT, LXT, SXT, SXT, FXT, FX7T GCLK Clock Synth Si EXT (zero delay) Daughtercard D Daughtercard E EXT (zero delay) Daughtercard F MBCLK FBB B FBE E Ref_CLK MHZ Ref Clock External Input -lane SATA ( Gb/s) SATA ( Gb/s) SFP SFP s DN9K-T DN_SATA DNSEAM_ Standard expansion board. A narrower version is available for SEAM_D on DNV7FA. DNUSB_USB USB. TX RX DM DP ID USB. Aux Power +V +V EE RS USB. Prototyping using via s DDR SODIMM (GB Max) (DDR) 9 +.V to +.V I/O (bottom) connector (-pin) (top) USB. Floppy HDD Power +V A Mini - AB V to.v V Good (GRN) PVBUS.V.A Max USB Power Micro - AB. Clock Synth Si. Clock Synth Si. Clock Synth Si s () Green CLK- CLK CLK- CLK- ClK- CLK- Virtex-T LXT/LXT/SXT SX9T/FX7T/FXT LXT/LXT (FFG) CLK- Infiniband (LXT/ SX9T only) SFP Socket (x) - TX Fault - MOD_DEF - RATE_SEL - LOS SFP Signals not available with LXT, LXT, SXT USB. Mini - AB TX RX DM DP ID Micro - AB = Differential when paired, but can be used single ended at reduced frequency = SX9T, FX7T, FXT, LXT, LXT only Serial ( Mbit) EXT Clock Config + ATX Power Supply +V A V Good (GRN) V to.v PVBUS.V.A Max USB Power = Flash Configuration user Battery 9

32 PC- (M x ) (M x ) ( M x ) PC- (M x ) (M x ) ( M x ) PC- PC- PC- PC- (M x ) (M x ) (M x ) (M x ) ( M x ) ( M x ) (M x ) (M x ) ( M x ) ( M x ) Kintex-7 Kintex-7 7KT/7KT/ 7KT/7KT/ 7KT 7KT Kintex-7 (FFG7) (FFG7) 7KT/7KT (FFG9) CFG Bus Kintex-7 Kintex-7 7 7KT/7KT/ 7KT/7KT/ 7KT 7KT CPLD (FFG7) (FFG7) ( M x ) ( M x ) ( M x ) ( M x ) ( M x ) ( M x ) ( M x ) ( M x ) PC- ( M x ) PC- ( M x ) I C PC- PC- Bridge Serial cfg Prog HPCLK (FF) EEProm Clocks (all s) cfg Prog Flash HRCLK Config SYSCLK (all s) -lane (GEN / GEN) SFB Clock (CFG Bus Clocking) DNK7 F Godzilla s Bad Hair Day Block Diagram v. High-Performance Computing Overview DNK7F Cluster The DNK7_F Cluster is a complete, U rack mount acceleration cluster. The standard configuration contains the following: Trenton TSB7 Xeon processor card or similar DNK7_F Kintex 7 cards with 7KT- s per card.. TB Hard Drive This system contains the maximum number of cost-effective that can be reasonably integrated into a U chassis. Power and cooling are the constraining variables. High performance paths between boards enable movement under algorithmic control that is wholly separate from the host processor, enabling based acceleration of whole new classes of -intensive algorithms. In short, the DNK7_F Cluster is a massive number of large, low-cost s integrated with an excellent dual Xeon-based processor host. Overview PC- (M x ) (M x ) (M x ) PC- (M x ) (M x ) (M x ) PC- (M x ) (M x ) PC- (M x ) (M x ) (M x ) PC- (M x ) (M x ) PC- (M x ) (M x ) (M x ) DNK7_F The DNK7_F is a Xilinx Kintex-7 based board optimized for algorithmic acceleration applications requiring s with high-performance local memory. Data movement to/from the grid is accomplished via a fixed -lane, GEN/GEN bridge. Each field Kintex-7 (s - in the block diagram) has five separate M x ( Gb) memories. The Dataflow Manager ( in the block diagram) has six M x memories. Kintex-7 7KT/7KT (FFG9) Kintex-7 7KT/7KT (FFG7) Kintex-7 7KT/7KT (FFG7) CFG Bus DNK7_F CPLD 7 Kintex-7 7KT/7KT (FFG7) Kintex-7 7KT/7KT (FFG7) (GEN/GEN) Fan Out Switch Fan Out Switch Bridge (FF) I C Serial EEProm Flash Config (M x ) (M x ) (M x ) (M x ) (M x ) (M x ) (M x ) (M x ) PC- (M x ) PC- (M x ) PC- PC- cfg cfg Prog Prog HPCLK HRCLK Clocks (all s) SYSCLK (all s) Xeon E-7 (CPU) GB GB GB GB Platform Controller Hub () U Rackmount Chassis containing: - Intel Xeon E-7 or similar processor card - DNK7_F cards each with Xilinx of the largest Kintex 7 s (7KT) -lane (GEN/GEN) s in total, % dedicated to application - Other configurations with different CPU-to- ratios are available - bays for SATA- hard drives Processor card - Intel Xeon E- series or better/similar processors (Sandy Bridge, if available),. GHz Quad-Core, MB shared L cache GB memory ( GB total) Bioinformatics Financial Analytics - Low Latency Analysis - Derivative Calculations LAN // base-t LAN USB USB Video (SandyBridge) A partial list of possible applications includes: HDD Genomic Search Image Processing Signal Processing Radar Up to HDD (SATA ) Options up to GB ( GB max) VGA with standard D-Sub connector //BASE-T ( ports) USB. ( ports total) - ports on front panel - ports on back bracket Supports virtually all Linux distributions DNK7_F HPC Acceleration card - PCI Express (-lane) -based algorithm acceleration peripheral with Kintex-7 s Xilinx Kintex-7 s: 7KT- (FFG7) - 7KT-,-,-, 7KT-,-,-, or 7KT-,-,- Xilinx Kintex-7 : 7KT- (FFG9) - 7KT-,-,- or 7KT-,-,- Scientific Computing Video Compression Encryption/Decryption (Cryptography) 9 -lane (GEN / GEN) SFB Clock (CFG Bus Clocking) PCI Express (-lane) -based algorithm acceleration peripheral with Kintex-7 s - Xilinx Kintex-7 s: 7KT- (FFG7) - Xilinx Kintex-7 : 7KT- (FFG9) Fixed -lane interface and controller - GEN/GEN - Full mastering DMA transmit (host memory -> card) receive (card -> host memory) Xilinx Kintex-7 7KT- total user s - 7, flip-flops per K flips-flops with -input LUT -, x multipliers + -bit accumulator per - 9, Kbit block RAM ( Mbytes) per (or, Kbit blocks) Fully dual-ported Each block RAM configurable as: K x, K x, K x, K x 9 (or ), K x (or ), K x (or ), or x 7 (or ) - Options for the larger 7KT when available. to interconnect is single-ended - Source-synchronous -> frequency: Mb/s per pin when using DDR Config Bus (CFG) connects all Kintex-7 s ( signals) - 9 separate Mb x memories for each field - memories PC- - memories PC- - Each memory has separate address,, and control separate Mb x memories for Dataflow Manager - memories PC- - memories PC- - Each memory has separate address,, and control Two independent low-skew global clock networks differentially distributed and balanced Fast and Painless configuration via - On-board battery for AES bitstream encryption Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions -controlled s - Enough light to use as a -based flashlight

33 Config EE User Expansion Board to Board Cards / Dataflow Top Bottom Spartan - LXT User Dataflow Manager DM Clock Bridge Q -lane (GEN/GEN) - (M x ) Spartan - LX (FGG) MB (upper) MB (lower) Spartan - LX (FGG) - (M x ) ALL s MB Clock - (M x ) Spartan - LX (FGG) Spartan - LX (FGG) - (M x ) - - (M x ) (M x ) Spartan - Spartan - LX LX (FGG) (FGG) Spartan - Spartan - LX LX 9 (FGG) (FGG) - (M x ) - (M x ) - - (M x ) (M x ) Spartan - Spartan - LX LX (FGG) (FGG) Spartan - Spartan - LX LX 7 (FGG) (FGG) - - (M x ) (M x ) High-Performance Computing DNBFC_S Cluster Overview - - (M x ) (M x ) (GEN) BFC_S_ Each line represents serial I/O connections. GB/s per line The DNBFC_S Cluster is a complete U rack mount acceleration cluster. The standard configuration contains the following: Trenton TSB7 Xeon processor card or similar DNBFC_S_ Spartan- cards with LX s per card. TB Hard Drive This system contains the maximum number of cost-effective s that can be reasonably integrated into a U chassis. Power and cooling are the constraining variables. High-performance paths between boards enable movement under algorithmic control that is wholly separate from the host processor, enabling based acceleration of whole new classes of -intensive algorithms. Fan Out Switch Fan Out Switch In short, the DNBFC_S Cluster is a massive number of large, low-cost s integrated with an excellent Xeon-based dual processor host. High-speed serial cables between cards add as much as GB/s throughput within the chassis. QPI Xeon (CPU) Xeon (CPU) GB GB GB GB GB GB Platform Controller Hub () LAN // base-t LAN USB USB Video (XGI) HDD Up to HDD (SATA ) U Rackmount Chassis containing: - Intel Xeon E-7 processor card or similar/better - DNBFC_S_ cards each with Xilinx of the largest Spartan- s (XCSLX) -lane (GEN) s in total, % dedicated to application - Other configurations with different CPU-to- ratios are available - bays for SATA- hard drives Processor card - Intel Xeon E- series or better/similar processors (Sandy Bridge,if available),. GHz Quad-Core, MB shared L cache GB memory ( GB total) - Options up to GB ( GB max) VGA with standard D-Sub connector //BASE-T ( ports) USB. ( ports total) - ports on front panel - ports on back bracket Supports virtually all Linux distributions A partial list of possible applications includes: Bioinformatics Financial Analytics - Low Latency Analysis - Derivative Calculations Genomic Search Image Processing Signal Processing Radar Scientific Computing Video Compression Encryption/Decryption (Cryptography) 9

34 High-Performance Computing DNBFC_S_ - (M x ) - (M x ) Config EE User Expansion Cards Top Spartan - LXT User Dataflow Manager / Bridge Board to Board Dataflow Bottom DM Q -lane (GEN/GEN) - (M x ) Spartan - LX (FGG) Spartan - LX (FGG) - (M x ) Clock ALL s MB Clock MB (upper) MB (lower) - (M x ) Spartan - LX (FGG) Spartan - LX (FGG) - (M x ) DM (M x ) Spartan - LX (FGG) Spartan - LX 9 (FGG) - (M x ) Frequency Synthesizer. - - (M x ) Spartan - LX (FGG) Spartan - LX (FGG) - (M x ) CLK A ALL s - (M x ) Spartan - LX (FGG) Spartan - LX 7 (FGG) - (M x ) Battery Bitstream Encryption - (M x ) Spartan - LX (FGG) Spartan - LX (FGG) - (M x ) Overview Designed for high-performance Computing (HPC) applications, the DNBFC_S_ is a -based peripheral that allows algorithm developers to employ hardware-in-the-loop acceleration utilizing cost-effective Xilinx Spartan- s. Data movement to/from the grid is accomplished via a fixed -lane, GEN/GEN bridge. Each Spartan- has its own M x memory capable of clocked speeds up to ( Mb/s per pin). Two additional M x memories are connected to the USER Dataflow Manager (LXT) for bulk storage. PCI Express (-lane) -based algorithm acceleration peripheral - of the largest Xilinx Spartan- s: SLX-, M x (Gb) - memories ( per ) - Xilinx Spartan- s: SLXT-, M x (Gb) - memories Fixed -lane interface and controller - GEN/GEN - Full mastering DMA transmit (host memory -> card) receive (card -> host memory) Xilinx Spartan- LX- total -, flip-flops per 9K flips-flops with -input LUT -, x multipliers + -bit accumulator per -, Kbit block RAM ( Kbytes) per Fully dual-ported Each block RAM configurable as: - Kx, Kx, Kx, Kx/9, Kx/, or x / - Options for LX-L (lower power) or LX- (higher frequency) Also LXT-,- - Options for LX, LX7, LX, LX (lower cost) to interconnect single-ended - Source-synchronous -> frequency: Mb/s per pin when using DDR Main Bus (MB) connects all Spartan- s ( signals) - 9 Mb x fixed external memory dedicated to each field ( total) Mb x fixed external memories dedicated to USER Dataflow Manager - - is stuffed. V CCINT is set to Extended Performance operating range: With LX-, LXT-: 7 Mbps (. ) -.7 Gb/s maximum rate With LX-, LXT-,LXT-: Mbps ( ) -. Gb/s maximum rate - Full support for memory block controller (MBC) Up to open banks Configurable multi-port interface to fabric - -, -, or -bit bus Easy implementation with Xilinx CORE Generator Expansion via high-speed, low-power transceivers (LXT) -. Gb/s per lane, each direction with - or - (TX and RX) -.7 Gb/s per lane, each direction with - (TX and RX) - lanes ( RX and TX) for daisy chain left - lanes ( RX and TX) for daisy chain right - Board to board communication > GB/s per connector TX > GB/s per connector RX Non-proprietary, off-the-shelf Samtec cable assembly - Off-board daughter cards Three independent low-skew global clock networks differentially distributed and balanced - G: programmable in increments (ICS clock synthesizer) to - G: reference - G: Main Bus (MB) clock Fast and Painless configuration via - On-board battery for AES bitstream encryption - Unique Device DNA identifier for design authentication Full support for embedded logic analyzers via interface - ChipScope and other third-party debug solutions -controller s - Enough for emergency lighting in a ll parking structure 9 7

35 DINI GROUP 79 Draper Ave. La Jolla, CA..9