User manual for MERUS evaluation boards

Transcription

1 UM_8_PL88_9_9 User manual for MERUS evaluation boards About this document Scope and purpose The evaluation board is an evaluation and demonstration board for MA, MAP, MA7, and MA7P proprietary multi-level amplifiers. Intended audience Audio amplifier design engineers Attention: Attention: Please read through this user manual before operating the board. When powering up the board make sure to follow the instructions in the Start Sequence section. Please observe proper ESD handling procedures. Failure to do so may result in damage to components on the board. User Manual Please read the Important Notice and Warnings at the end of this document V. page of 8

2 Table of contents Table of contents About this document... Table of contents... Overview.... Board features and audio performance.... EVK device type... Setup guide.... Connections and interfaces.... Notes to digital audio and analog audio headers... 8 Operating the demonstration board Recommended operating conditions Toggle switches Speaker load GUI Start sequence....6 Analog input configuration (MAxx devices)....7 Digital (IS) input configuration (MAxxP devices)... Measurement methods... EVK schematic... 6 Revision history... 7 User Manual of 8 V.

3 Overview Overview The demonstration board is an evaluation and demonstration board for MERUS audio MA, MAP, MA7, and MA7P amplifiers. It contains a variety of digital/analog input, output and setup/selection features. It also contains two on-board power supply generators ( V and. V buck-converted) so only one external power supply (PVDD) are necessary. The board can be used for evaluating or demonstrating key features/advantages of the MERUS technology: Energy efficiency Power losses at normal user operating conditions (listening levels) Idle power loss Adaptive power management system No output filter components Solution cost and size reduction Audio performance THD performance and audio quality. Board features and audio performance Number of audio channels Audio input format MAxx MAxxP Amplifier gain Supply voltage Max PVDD for MA/MAP Max PVDD for MA7/MA7P Output noise level MAxx MAxxP Dynamic range MAxx MAxxP Idle PVDD=8V x BTL, xbtl+xse, xse Analog Digital (IS) db / configurable 6dB PVDD 8 V 6 V < uvrms(aw) < uvrms(aw) > db >9 db MAxx <6 ma * MAxxP <9 ma * Crosstalk <-8 db Efficiency, full-scale, 8 ohm 9% User Manual of 8 V.

4 Overview Note: Idle consumption is the sum of output stage current and V supply and. V supply current. As all the supplies are tied to PVDD, the efficiency of the buck-converted V and. V should be taken into account when measuring idle current consumption directly from PVDD. Features on the EVK makes it possible to break the V and.v supply lines after the buck converters (see table ). Please refer to the MAxx/P device datasheet for exact current figures.. EVK device type The type of device (MA, MAP, MA7 and MA7P) on the EVK is printed on the top on the device, and also stated on the serial number label placed on the bottom side of the EVK PCB. User Manual of 8 V.

5 Setup guide Setup guide Equipment required for operating and evaluating Single power supply for PVDD. Analog audio source or signal generator with line level output (MAxx) Digital IS audio source (MAxxP) Cables for input and output connectors Audio analyzer with measurement filter. Connections and interfaces Figure Top block view of EVK board Note: For schematic: see Figure on page. User Manual of 8 V.

6 Setup guide Table EVK headers and connectors Name Schem. Ref. Description Comment MSEL JMP Selects in conjunction with MSEL the output configuration (see table ). MSEL JMP Selects in conjunction with MSEL the output configuration (see table ). /CLIP JMP Audio clipping indicator (open drain output), pulled low when clipping occurs. /ERR JMP6 Error indicator (open drain output), pulled low when an error occurs. Default: CH BTL. Jumpered high (H). Default: CH BTL. Jumpered low (L). I/O pin. Do not jumper. I/O pin. Do not jumper. CLK M/S JMP7 Selects clock mode. M=Master clock (non P versions). S= Slave (external) clock (P versions). AD AD JMP9 Selects IC address (see table ). Default: IC address B. Both jumpered low (GND). REG EN_N JMP Enables V and. V supplies. Default: Jumpered. PVDD MEAS JMP Breaks PVDD for PVDD current measurements. V MEAS JMP Breaks V supply for V circuit current measurements. V MEAS JMP Breaks. V supply for. V circuit current measurements. Default: Jumpered. Parallel with JMP6. Default: Jumpered. Default: Jumpered. GND GND JMP Two ground connections. Default: Not jumpered. SCL SDA JMP IC bus serial clock and data. I/O Pin. Do not jumper. PVDD MEAS JMP6 Breaks PVDD for current measurements. Default: Jumpered Parallel with JMP. CH J Channel speaker connection. way screw terminal with positive and negative speaker outputs. Center GND. CH J Channel speaker connection. way screw terminal with positive and negative speaker outputs. Center GND. JACK J6 Single ended, stereo analog audio input. DIGITAL AUDIO J7 IS Digital audio input. NOTE: see section. for setting up. Tip = CH Ring = CH Sleeve = GND I/O pins. Do not jumper. User Manual 6 of 8 V.

7 Setup guide Name Schem. Ref. Description Comment ANALOG AUDIO J9 Balanced analog audio input connector. Also selects JACK input. NOTE: see section. for setting up. PVDD J External power supply POSITIVE terminal. GND J External power supply GND terminal. DIGITAL AUDIO J IS Digital audio input. NOTE: see section. for setting up. OUTA J Direct connection to device output node vsw_a. OUTB J6 Direct connection to device output node vsw_b. OUTB J7 Direct connection to device output node vsw_b. OUTA J8 Direct connection to device output node vsw_a. Jack input = All Jumpered. Balanced input = use pins for balanced analog audio input. NOTE: Should NOT be jumpered for P (digital audio) versions. PVDD : +8 V MAX (MA/-P) PVDD : +6V MAX (MA7/-P). GND. I/O pins. Do not jumper. Output measuring pin. Output measuring pin. Output measuring pin. Output measuring pin. Table Signal configuration (JMP) MSEL MSEL Configuration L L channel parallel bridge tied load (PBTL) L H channels single ended load (SE) and channel bridge tied load (BTL) H L channels bridge tied load (BTL) H H channels single ended load (SE) User Manual 7 of 8 V.

8 Setup guide Table IC address decoding (JMP9) IC device address AD AD 7-bit IC address x L L b x L H b x H L b. Notes to digital audio and analog audio headers When using the Digital Audio Header for using digital IS input stream (MAxxP), the connection scheme should look like as follows (from top to bottom, left side of the header): SCK: Word clock; also known as Bit clock WS: Word select; also known as left right clock (LRCLK) SD: Multiplexed data line containing two digital input stream channels SD: Multiplexed data line containing two digital input stream channels MCLK: Master clock (typically 6 x fs) When using analog input, the board has been set up to initially evaluate with an unbalanced input source (see Analog Audio Header, jumpers connected). However, for full system performance evaluation it is recommended to apply a balanced analog input signal. This can be done by removing the four jumpers from the Analog Input Header and connecting the analog balanced input signal as follows (from top to bottom, left side of the header): ch input ina (+) ch input inb (-) ch input ina (+) ch input inb (-) User Manual 8 of 8 V.

9 Operating the demonstration board Operating the demonstration board. Recommended operating conditions Table Recommended operating conditions PVDD (MA/MAP) PVDD (MA7/MA7P).. Minimum Nominal Maximum Unit 8 6 V V Output peak current (MA/MAP) Output peak current (MA7/MA7P) A A. Toggle switches The board has two toggle switches. The toggle switches have the following functions: Table Switch- Switch- Switch function Function Shutdown/Enable (default set to shutdown ) Mute/Play (default set to mute ). Speaker load The demonstration board is configured as a filterless amplifier. This means that no LC filter is placed between the amplifier outputs and the load. In normal use the amplifier relies on the inherent inductance of the loudspeaker and therefore no extra inductance needed. Inductors for use in series with power resistors are included with the demonstration board. These can be used when making any measurements without a real loudspeaker as the load and having no external low-pass filter in front of the audio analyzer input section. Please note that many audio measurement analyzers do not perform correctly when connected directly to a filterless amplifier output.. GUI The demonstration board is used with GUI PC software to control the MAxx device. The GUI software is included with the demonstration board and runs on Windows PCs. Unzip the file package on your PC in your preferred location. See next section for correct startup sequence incl. start of the GUI. User Manual 9 of 8 V.

10 Operating the demonstration board Figure GUI main window By default the MAxx/P will automatically select the relevant power mode (PM, PM or PM), based on detection of audio level during operation. The selected power mode is indicated by a blue color in the power mode indicator. A set of sliders are available above the power mode indicator. The first slider is used for setting the levels for transitions between PM and PM. When setting the values at higher levels the transition from PM to PM will occur at a higher output power level. The second slider is used in the same way, for transitions between PM and PM. Power Mode Profiles can be selected in the Power Mode Profile Select section. This gives a specific profile to the amplifier for optimization on low idle power consumption, audio performance or EMI. Please refer to the specific device datasheet for more detailed information on Power Mode Profiles. The Digital Audio Processor button is for digital input (IS) use and will be discussed in the start-up section for IS configuration. Note that Digital Audio Processor part of the GUI can only be used in combination with MAxxP devices.. Start sequence Important GUI software revisions: Current GUI software version is 6... Please note that the current GUI only accepts IC address x..6 Analog input configuration (MAxx devices) Follow this (recommended) sequence to start the evk:. Make sure toggle buttons are in shutdown and mute positions.. Connect all cables, including PC by USB cable.. Make sure active analog audio source is connected.. Turn on the PVDD supply. User Manual of 8 V.

11 Operating the demonstration board. Start board by setting toggle switch to enable position. 6. Start the GUI software by running the executable file to monitor device status. 7. Make sure the GUI indicates a valid Device ID and connection status (bottom right GUI). 8. Start playing music by setting toggle switch to play position. 9. Additional optimized settings can be programmed to the device: Hit Load select config file in configs subfolder hit program. Mute and turn off PVDD power supply..7 Digital (IS) input configuration (MAxxP devices) Follow this (recommended) sequence to start the board:. Make sure toggle buttons are in shutdown and mute positions.. Connect all cables, including PC by USB cable.. Connect IS connection to the IS Audio Input header.. Make sure that the clock select jumper is set to Slave mode.. Turn on PVDD power supply. 6. Make sure that the IS Master Clock is present before for enabling the amplifier. 7. Start board by setting toggle switch to enable position. 8. Start the GUI software by running the MA Device GUI 6...exe file. 9. Make sure the GUI indicates a valid Device ID and connection status (bottom right GUI).. Open the Digital Audio Processor in the GUI.. In the DAP window check Digital audio enable and Audio processor enable.. IS setup window will open when clicking IS setup. The correct IS settings should be set here.. Start playing sound by setting toggle switch to play position.. Additional optimized settings can be programmed to the device: Hit Load select config file in configs subfolder hit program. Mute and turn off PVDD power supply. User Manual of 8 V.

12 Operating the demonstration board Figure Digital audio processing window (top) and IS setup window (bottom) User Manual of 8 V.

13 Measurement methods Measurement methods Setting up a reliable measurement configuration for MAxx or MAxxP takes a little bit more effort than linear amplifiers and even regular switching amplifiers. This is mainly because MAxx and MAxxP are filterless amplifiers, which means that it does not require an external (usually expensive and bulky) LC filter to remove switching residuals. The filterless application is enabled by MERUS Audio multilevel technique, which makes sure that the switching residual is orders lower compared to regular switching amplifiers. For more information on the multilevel switching technique, please refer to the datasheet. To obtain reliable measurement results when measuring MAxx or MAxxP devices requires a separate external low-pass filter in front of the input stage of the audio analyzer. Most audio analyzers are bandwidth limited at their input stage, which means that they cannot follow the rapid changes of the amplifiers output stage. This can result in inaccurate and high THD+N measurements. Figure shows the recommended measurement setup. The setup shows a low-pass filter stage (AUX-) in front of the audio analyzer (APX-). In this case the measurement setup has been built around Audio Precision hardware, but this can also be some other audio analyzer hardware. Please note that it is recommended to use both balanced input and output measurement configurations. Note that Figure shows the setup for analog input (MAxx). To use the setup for digital input (MAxxP), simply replace the balanced analog input path with the IS input path. User Manual of 8 V.

14 Measurement methods Figure Recommended measurement setup for analog input (MA). User Manual of 8 V.

15 clk_io C EVK schematic EVK schematic Date: Tuesday, January, 7 Sheet of Size Document Number R ev pcb_evk_v ram ed MAIN - MA7(P) high power EVK. Title Merus Audio ApS, Hoerkaer, 7 Herlev, DENMARK A A HEADER X DIGITAL AUDIO IN. nc nc nc nc nc J6 Jack PCB socket.mm RAPCBH gnd S SN TN T ANALOG AUDIO JACK IN. ANALOG AUDIO IN. JUMPER WHEN IN "ANALOG AUDIO JACK IN". DO NOT JUMPER WHEN IN "DIGITAL AUDIO IN". J9 C uf 6V 8 C uf 6V 8 C uf 6V 8 C uf 6V CONN RECT x extvcc portvcc 6 J7 HEADER X J HEADER X JMP9 JMP clk_io v v DLP-USBH MOD 8 gnd sck 7 miso io 6 io mosi io ssel io C8 uf V 8mmdia USB PROGRAMMING INTERFACE. R K R K C7 uf V 8 C6 uf V 8 C9 nf V 6 C9 uf 6V 6 B B C8 uf 6V 6 C9 uf V 8mmdia C uf V 8 C uf V 8 C8 nf V 6 SW DPDT C uf 6V 6 JMP7 v v nenable v v R7 k SW SHUTDOWN. SW DPDT AVDD CMSER AVSS CREF INA INB INA INB AVSS 6 DVSS SCL AD AD SDA CLKMS CLKIO v JMP6 /ERROR 6 v JMP /CLIP nmute R k R k PVSS R6 k SW v PVSS 6 PVSS PVSS /MUTE /ENABLE CFBN MUTE. v v CFBN 7 v D TVS Diode added. C uf V 8 C7 uf V 8 C,,6,7,, changed from,uf to uf. C,,7,9,,,6,7 changed type and voltage. CFBP CFBP OUTB OUTB 9 vsw_b vsw_b OUTB OUTB 8 C9 uf V 8 C7 uf V 8 C SW and SW: DPDT toggle tied together for true electrical DPDT. MAxxx C PVDD PVDD C to C changed to footprint. PVDD PVDD L_ferr_ to L_ferr_ changed value and footprint to 6. CFAP CFAP C8, C9 changed value and to SMD type. C uf V 8 C uf V 8 OUTA vsw_a OUTA vsw_a C uf V 8 C6 uf V 8 J8 HEADER R86 changed to footprint. OUTA OUTA OHM Changes from Rev _: CFAN CFAN 6 CFAN vsw_a PVSS PVSS C nf V 7 L_ferr_ PVSS PVSS 8 J7 HEADER OHM C nf V DC_BUCK_ vsw_b J Screw terminal.mm p GND 6 EPAD L_ferr_ VIN VOUT DVDD 6 CFGDN 6 CFGDP 6 CGDN 6 CGDP 6 DVSS 9 CFDCN 8 CFDCP 7 CDC 6 DVDD VGDC CGDP CGDN MSEL MSEL DVDD 9 vsw_b U v cfgdn cgdn cgdp v cgdp cgdn v J6 HEADER C nf V L_ferr_ OHM C nf V 68uF V FC p. d. C6 uf 6V 6 C uf 6V 6 J HEADER vsw_a JMP JMP J Screw terminal.mm p CON C7 n V 6 C uf 6V 6 C uf 6V 6 C8 uf 6V 6 L_ferr_ OHM v msel SPEAKERS OUT. Vdd 6 U D D CON D VIN VOUT v TVS CONN RECT x J C EN R86 JMP GND M DC_BUCK_ msel GND J JMP JMP C uf 6V 6 C nf V 6 JMP6 v JMP v SUPPLY INPUT. C uf V 8 C nf V 6 C uf V 8 v v Figure EVK main schematic User Manual of 8 V.

16 AGND 6 PGND 6 EVK schematic SLEEP 8 L Vin VIN SW 9 Vout uh EN EN U TPS67DQCR VOS Rfbt M Cin.uF NC FB Rfbb Rpg k Cout uf AGND PGND PG 7 8k gnd Figure 6 EVK V buck converter schematic SLEEP 8 L_ Vin VIN SW 9 Vout uh EN U_ TPS67DQCR VOS Rfbt_.M Cin_.uF NC FB Rfbb_ Rpg_ k Cout_ uf PG 7 8k gnd Figure 7 EVK V buck converter schematic User Manual 6 of 8 V.

17 Revision history 6 Revision history Document version Date of release Description of changes V Initial release V Updates in content and layout User Manual 7 of 8 V.

18 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition Published by Infineon Technologies AG 876 Munich, Germany 8 Infineon Technologies AG. All Rights Reserved. Do you have a question about this document? erratum@infineon.com Document reference UM_8_PL88_9_9 IMPORTANT NOTICE The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. Before implementation of the product, the recipient of this application note must verify any function and other technical information given herein in the real application. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of noninfringement of intellectual property rights of any third party) with respect to any and all information given in this application note. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( WARNINGS Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.