Getting Started with Reconfigurable Logic (CPLDs and FPGAs)

Transcription

1 Getting Started with Reconfigurable Logic (CPLDs and FPGAs) Prepared By Dr. Hossam Eldin Mostafa Alexandria University, Faculty of Engineering, Alexandria, Egypt Main CPLD Starter Kit Hardware Software Examples Documentation Block diagram of XC9500 series Pin diagrams XC956-PC44 XC956 Datasheet PLCC Socket This page is last updated on st December 00

2 Getting Started with Reconfigurable Logic (CPLDs and FPGAs) What is CPLD A lot of logic devices are housed in CPLD and those connections can be specified by the program. For example, in case of the 7400 IC, 4 circuits of input NAND gate are housed. In case of 7404, 6 circuits of inverter are housed. These are separate IC. Therefore, to compose a circuit, it is necessary to do each wiring among the pins using the printed board. In case of CPLD, it has wiring among the logic in the IC. So, the wiring on the printed board can be made little. The capacity of CPLD is limited. There is limitation on the number of the pins, too. So, don't do excessive expectations. The outline specification of the part of the XC9500 series of Xilinx Inc. is shown below. Parts name XC956-5PC44C XC957-5PC44C XC957-5PC84C XC9508-5PC84C Number of pins 44pin PLCC 44pin PLCC 84pin PLCC 84pin PLCC Specification FB/6macrocells/800gates 4FB/7macrocells/600gates 4FB/7macrocells/600gates 6FB/08macrocells/400gates

3 The point which CPLD is convenient for is the thing about which it is possible to rewrite many time because it is recording the contents of the circuit to the flash memory. In the XC9500 series, rewriting in about 0,000 times is said to be possible. Also, because the pin for the rewriting is preparatory, the contents can be rewritten in the condition to have mounted to the actual circuit if there is wiring (In Circuit Programming). Complex Programmable Logic Devices (CPLD) are another way to extend the density of the simple PLDs. The concept is to have a few PLD blocks or macrocells on a single device with general purpose interconnect in between. Simple logic paths can be implemented within a single block. More sophisticated logic will require multiple blocks and use the general purpose interconnect in between to make these connections. CPLDs are great at handling wide and complex gating at speeds e.g. 5ns which is equivalent to 00MHz. The timing model for CPLDs is easy to calculate so before you even start your design you can calculate your in to output speeds. - Ease of Design: Why use a CPLD CPLDs offer the simplest way to implement design. Once a design has been described, by schematic and/or HDL entry, a designer simply uses CPLD development tools to optimise, fit, and simulate the design. The development tools create a file, which is then used to customise (program) a standard off-the-shelf CPLD with the desired functionality. This provides an instant hardware prototype and allows the debugging process to begin. If modifications are needed, design changes are just entered into the CPLD development tool, and the design can be re-implemented and tested immediately. - Lower Development Costs: CPLDs offer very low development costs. Ease of design, as described above, allows for shorter development cycles. Because CPLDs are re-programmable, designers can easily and very inexpensively change their designs. This allows them to optimise their designs and continues to add new features to continue to enhance their products. CPLD development tools are relatively inexpensive and in the case of Xilinx, are free. Traditionally, designers have had to face large cost penalties such as re-work, scrap, and development time. With CPLDs, designers have flexible solutions thus avoiding many traditional design pitfalls. - More Product Revenue: CPLDs offer very short development cycles, which means your products get to market quicker and begin generating revenue sooner. Because CPLDs are re-programmable, products can be easily modified using ISP over the Internet. This in turn allows you to easily introduce additional features and quickly generate new revenue from them. (This results in an expanded time for revenue). Thousands of designers are already using CPLDs to get to market quicker and then stay in the market longer by continuing to enhance their products even after they have been introduced into the field. CPLDs decrease Time To Market (TTM) and extend Time In Market (TIM). 4- Reduced Board Area: CPLDs offer a high level of integration (large number of system gates per area) and are available in very small form factor packages. This provides the perfect solution for designers of products which must fit into small enclosures or who have a limited amount of circuit board space to implement the logic design. The CoolRunner? CPLDs are available in the latest chip scale packages, e.g. CP56 which has a pin pitch of 0.5mm and is a mere 6mm by 6mm in size so are ideal for small, low power end products. 5- Cost of Ownership: Cost of Ownership can be defined as the amount it costs to maintain, fix, or warranty a product. For instance, if a design change requiring hardware rework must be made to a few prototypes, the cost might be relatively small. However, as the number of units that must be changed increases, the cost can become enormous. Because CPLDs are re-programmable, requiring no hardware rework, it costs much less to make changes to designs implemented using them. Therefore cost of ownership is dramatically reduced. And don't forget the ease or difficulty of design changes can also affect opportunity costs. Engineers who are spending a lot of time fixing old designs could be working on introducing new products and features - ahead of the competition. There are also costs associated with inventory and reliability. PLDs can reduce inventory costs by replacing standard discrete logic devices. Standard logic has a predefined function and in a typical design lots of different types have to be purchased and stocked. If the design is changed then there may be excess stock of superfluous devices. This issue can be alleviated by using PLDs i.e. you only need to stock one device and if your design changes you simply reprogram. By utilising one device instead of many your board reliability will increase by only picking and placing one device instead of many. Reliability can also be increased by using the ultra low power CoolRunner CPLDs i.e. lower heat dissipation and lower power operation leads to decreased Failures In Time (FIT). In 985, a company called Xilinx introduced a completely new idea. The concept was to combine the user control and time to market of PLDs with the densities and cost benefits of gate arrays. A lot of customers liked it - and the FPGA was born. Today Xilinx is still the number one FPGA vendor in the world! An FPGA is a regular structure of logic cells? or modules and interconnect which is under the designer s complete control. This means the user can design, program and make changes to his circuit whenever he wants. And with FPGAs now exceeding the 0 million gate limit (Xilinx Virtex? II is the current record holder), the designer can dream big!

4 CPLD Starter Kit What is included The components listed in the following table are included with the starter kit (The images of the components are shown in the above image) Download the above table in PDF format (kit_components.pdf) or in Exel format (kit_components.xls) What is NOT included

5 The following components are NOT included with the starter kit. - +5v Power Supply - Parallel Port Adaptor OR Parallel Port Male Connector 4- DB5 Male -Female Cable 5- Bread Boards 6- Connecting Wires

6 HARDWARE JTAG Parallel Port Programmer To download the the schematic in PDF format click here jtag.pdf (All the components are included with the starter kit) CPLD Board To download the the schematic in PDF format click here xc956.pdf (All the components are included with the starter kit)

7 Application Board To download the the schematic in PDF format click here application.pdf (Components are NOT included with the starter kit) Whole System

8

9 4 VCC SENSE 5(S) R4 0 D N4004 D N4004 VCC VCC R 5.6K R K R K C n D R5 D D LED (S4) DONE 0 R6 8 9 GND GND 0 UC PROG C C R R8 DIN 5 6 CTRL CLK R5 R0 TMS_IN 9 8 B B DB-5 PARALLEL PORT CONNECTOR FPGA HEADER CPLD HEADER Notes: U 74LS5 U 74HC5 U and U power: VCC pin4 GND pin 7 Xilinx CPLD & FPGA Parallel Port Programmer A A Dr. Hossam Eldin Mostafa ( Alexandria University, Faculty of Engineering, Alexandria, Egypt November 00 jtag.opj R7 D/P TDO UA 0 C 00p UB C 00p 4 U5D 0 UC 0 0 6(D4) R 0 (D0) 5(D) (D) 0 R 0 R4 0 C4 00p 0 R9 0 DIN CCLK TDI TCK 4(D) *PROG TMS 8(D6) (*S7) (S6) UA C5 00p UD 5 6 UB 4 5(GND)

10 4 U XC956 CPLD VCC = 5VDC VCC D D PA0 PA PA PA PA4 PA5 PA6 PA7 VCC C C 9 0 R 4 K 5 9 GSR() PB0 PB PB PB PB4 PB5 PB6 PB7 PC0 PC PC PC PC4 PC5 PC6 PC7 B B PD0 PD PD PD U XC956 CPLD BOARD Dr. Hossam Eldin Mostafa ( A A Alexandria University, Faculty of Engineering, Alexandria, Egypt November 00 xc956.opj VCC VCC VCCIO Programmer_TDO Programmer_TDI Programmer TCK TDO TDI TCK Programmer_TMS TMS GTS() GTS() GCK() GCK() GCK() D LED GND GND GND

11 4 7 SEGMENT MODULE VCC VCC L7 L6 L5 L4 L L L L0 R0 K R9 0 D D D8 D7 D6 D5 D4 D D D a D9 f b LED LED LED LED LED LED LED LED LED e d g c R8 0 R7 0 R6 0 R5 0 R4 0 R 0 R 0 R 0 gf ed cba LED MODULE C VCC VCC C VCC UD R7 0K R6 0K R5 0K R4 0K P P P P0 R 0K R 0K R 0K R0 0K S S S S CLK_OUT R8 UC SW B B.K SW DIP-4 CLOCK GENERATOR MODULE PUSH BUTTONS MODULE DIP SWITCHES MODULE APPLICATION BOARD Dr. Hossam Eldin Mostafa ( Alexandria University, Faculty of Engineering, Alexandria, Egypt November 00 A A application.opj R9 6.8k C p Y M C p

12 XILINX WebPACK Tutorial Prepared by Dr. Hossam Eldin Mostafa Faculty of Engineering, Alexandria University, Alexandria, Egypt. ( The Xilinx Inc. is providing the software tools to design CPLDs and FPGAs.This software is called WebPACK. WebPACK is available free-of-charge by registering. You can download them from the XILINX site As for the WebPACK tool, a new type is released in order. Therefore, the operation is may be a little bit different from the tool which is introduced on this webpage. This section is a step by step approach to your first simple design. The following pages are intended to demonstrate the basic PLD design entry and implementation process. In this example tutorial a simple HEX to seven segment decoder is designed in VHDL. The design is initially targeted at a XC956 CPLD. Example Project In this example(see the left image), we will design a Hex to seven segment decoder. The circuit accepts 4 binary bits as inputs (I I I I0) and produces 7 binary bits as outputs (O6 O5 O4 O O O O0). It is directed to derive a common anode seven segment display. The right image shows the test circuit for this design using XC956, DIP switches modules to generate the inputs and the seven segment module to see the outputs. The pin out os the CPLD is illustrated and will be defined in the VHDL program. You can download the above image in PDF format from decoder.pdf The VHDL file that will be writtrn can be downloaded here decoder.vhd. The whole Webpack project can be downloaded from here decoder.zip Developing the project using WebPACK

13 Start WebPACK ISE Software Select Start > Programs > Xilinx WebPACK > WebPACK Project Navigator. The following window will be displayed. Sources in Project is the window to display a device name, a source module name and so on. Processes for Current Source is the window to display a various function menu. The window on the right( HDL Editor workspace window ) is the window to display a source code. The window most below( Transcript window ) is the window to display the log of the processing elapse Creat a New Project It is recommended that you create the folder which stores files of the project before beginning work. I made a folder which stores the related files of the test project as C:\CPLD_projects\. Select File -> New Project the dialog of the project creation of file is displayed. A Project Name, the place which saves a project, the kind of the device and the language to use and so on are set by this dialog. Click Value of the device and the language to use and choose the contents which fit in from the displayed pull-down menu. Sources in Project of Project Navigator changes when the registration of the project is done. Other device families can be chosen here including FPGAs. Even if the flow is intended to be purely schematic, the schematic diagram will be converted into HDL and synthesised through the chosen synthesis tool.

14 You can change the title of the project by choosing Source -> Properties or double-clicking Making of a source file A source type selection dialog is displayed when choosing Project -> New Source or clicking the

15 Select "VHDL Module" from the displayed item. When using a language except VHDL, select a corresponding language. Type "File Name", and confirm the file saving path of "Location" and click "Next". Type "Entity Name" and "Architecture Name". The ports can be specified by this dialog. However, in this example we specifie them by the description of VHDL from behind. Click "Next" without assigning the ports. This table automatically generates the entity in the decoder VHDL module. Following confirmation screen is displayed. Click "Finish" if there is not mistake in the contents.

16 The window (HDL Editor window) of the source code is displayed in HDL Editor workspace window of Project Navigator Display or non-display of each window can be controlled with the View menu. To spread a source code window, click Project Workspace of the View menu and removes checking. You can expand by clicking, too. To make display a source code window in whole HDL Editor workspace window, click the window maximization button in the upper right like usual window control. The basic part of the format of VHDL is already written in the displayed source code window.

17 This time, you adde the following to entity and architecture to implement the decoder.

18 You can download the VHDL file from decoder.vhd After doing the above-mentioned change, save a file by File -> Save or by the the input and output pins of the CPLD inside the VHDL file. button. The attribute keyword is used to define Syntax check By the following operation, the grammar of the made source file is confirmed. Double-click "Check Syntax" which is displayed in the Process for Current Source window. This has the checking of format (Syntax). If the checking result is to be OK, Check Syntax has a green checking mark. Also, "Done: completed successfully." is displayed in the end of the situation display window.

19 When checking a format without saving a file, the following dialog which shows that a file isn't saved is displayed. It is saved if you click "Yes". I attempt to make an intentional error occur as the example. I delete the last semicolon(;) of the port declaration of entity and I attempt to execute Check Syntax

20 Check Syntax has a red X mark. Also, "Done: failed with exit code: 000." is displayed in the end of the situation display window. The position of the error can be known with the situation display window. ERROR : (VHP 06). C:\CPLD_projects\decoder\decodr.vhd Line. Read symbol ATTRIBUTE, expecting ';'. An error is detected at the th line. When double-clicking, the mark which shows an error on the left side of the source code is displayed. Because the mark shows the line which detected an error. So, check previous lines and so on.

21 Fitting the file which will be written to the CPLD is generated fron the VHDL file using this process. Double-click "Fitter" which is displayed at the Process for Current Source window. The fitting processing begins with this operation.

22 Fit Design has a green checking mark if the fitting result is to be OK. Also, "Done: completed successfully" is displayed in the end of the situation display window. The Confirmation of the Fitting Result In case of complicated circuits, the various data must be confirmed. This time, we confirm the situation of the assigned pin. Double-click Fitter Report which is displayed in the Process for Current Source window. A report window is displayed. There is following figure in it. This figure shows the assignment of the pins. If we did not predefine the inputs and output pins (using the attribute keyword), the tool will selecting pins automatically. So, the design may not look neat.

23 In the Fitter report, the usage of the CPLD resources are listed as shown below Invoking the Programmer Note that the JTAG Parallel Port programmer will work directly on Windows 98. On Windows XP, 00, NT, some drivers may be needed so try to use the programmer on Win98 Operating System. The operation after this is the work to do after connecting a personal computer and CPLD device with the JTAG programmer (You will build this programmer using the components supplied with the kit). Double-click Configure Device (impact) which is displayed at the Process for Current Source window.

24 The window of JTAG Programmer is shown below. When using the parallel port of the PC, it specifies Parallel by Output -> Cable Setup -> Cable Communication Setup. Data is transferred to CPLD if pushing the OK button. When a cable isn't connected, it becomes an error.

25 Select the CPLD (using the left mouse button) and right click the mouse to choose the operation or select Operations from the main menu The first operation is to erase the CPLD It will ask you if you want to override the write protect. Select OK Sometimes due to the parallel cable exessive length or another unknown reasons, the program hangs and does not say that it completes the erasure successfully. Actually, it erases the CPLD successfully. But you should press CTRL + ALT + DEL and end the programmer task and invoks it again by clicking on the impact in the WebPACK project navigator. Select the CPLD and with the mouse right button, choose Blank Check to check if the device has been erased successfully

26 If the devie has been erased, the Device is Blank message will be displayed To program the device, select it with the left mouse button and with the right mouse button, choose Program

27 Unckeck the Erase Before Programmin box(because we have already erased the device). Make sure that Verify box is checked. When you do so, the following dialog will appear informing you that programming the device before erasing it may harm the device. Discard this message and press OK and then press OK on the Programming window. A progress bar appears indicating the progress of the programming.

28 When programming is OK, a Programming Succeded message appears. Now, you can try the program you have just downloaded if you connect the CPLD inputs to the DIP switched and the CPLD outputs to the seven segment,

29 Block diagram of XC9500 series You can jump to the page of the explanation when you click the part where the pointer become the hand. If you want to know more detailed specification, refer to the following PFD file. Blocks An block is composed of input buffer, output buffer, multiplexer for the output control and grounding control and so on. Multiplexer for the output control(oe MUX) controls an output enable or stop. It is controlled by the signal from the macrocell or the signal of the GTS(Global Three-State control) pin. It can always make output '' or '0', too. There are four GTS in XC956 and XC9588 and in case of the other device, they are two. A slew rate control is the one to make the rising and the falling of the output pulse smooth. It is used when suppressing the occurrence of the noise. A grounding control is used when making input/output pin () an earth terminal. In case of the circuit where much noise occurs, it isn't sometimes possible to do noise reducing by the standard earth terminal. At the actual circuit, a pull-up resistor is more connected with the input/output pin. This circuit makes an input/output pin '' condition compulsorily during programming of CPLD to make an influence by the condition of the pin little. This circuit is detached in usualoperation

30 in usual operation. Each input/output pin can handle a 4-mA current. FastCONNECT Switch Matrix FastCONNECT Switch Matrix controls the input signals to the Function Block. All the signals from the input-output port and the signals of the Function Block are connected with FastCONNECT Switch Matrix. The signals which are specified by the program out of these signals are applied to the Function Block. The output signals from the Function Block are applied to the Function Block through the wired AND buffer. This provides additional logic capability and increases the effective logic fan-in of the destination Function Block without any additional timing delay. It is automatically invoked by the development software where applicable. Function Block Function block is composed of the programmable AND array, product term allocator and macrocell. 6 pieces of signals inputted to the Function Block are divided into the true and complement signals by the programmable AND array and become 7 kinds of signals. In Product Term Allocator, it applys the signal with combination of them to the macrocell. A macrocell is composed of one D/T type flip-flop. The signals of set/reset/clock to this flip-flop are supplied by the Product Term Allocator. The output of the logic circuit can be connected with the pin without using a flip-flop, too. need. There are 8 independent macrocells in one Function Block. There are 8 pieces of output in the Function Block and they are connected with FastCONNECT Switch Matrix and blocks. Also, the set/reset signal(gsr : Global Set/Reset) and the clock signal(gck : Global Clocks) are inputted to the Function Block and are used for the condition of the operation of the flip-flop according to PTOE(Product Term Output Enable) signal is output to block from Product Term Allocator. The number of the Function Blocks depends on the device. As for XC956, blocks are mounted, as for XC957, 4 blocks are mounted and as for XC9508, 6 blocks are mounted. It isn't sometimes possible to use all macrocells by the limitation on the number of the pins. For details, confirm pin diagrams. There are few cases which connect all macrocells with the pin actually. Generally, there are macrocells to use only in the logic inside.

31 In-System Programming XC9500 devices are programmed in-system via a standard 4-pin JTAG(Joint Test Action Group) protocol. The devices fully support IEEE 49. boundary-scan(jtag). Because it is equipped with the pin for independent JTAG, the program can be changed as it mounted CPLD on the printed board. While programing, all input ports in the block are set to the 'H' level. The wires to use in JTAG are the following four. Each use is shown below. TMS(Test Mode Select): This signal is decoded by the TAP controller to control test operations. TCK(Test Clock): This clock drives the test logic for all devices on boundary-scan chain. TDI(Test Data In): This signal is used to transmit serial test instructions and data. TDO(Read Data): Read back data from the target system is read at this pin.

32 Pin diagrams ( XC956-PC44/XC957-PC44 ) The figure on the left is the top view of CPLD of 44 pins. The following item is used to know the position of the pin. *The direction of the printed name. *A corner in the upper left is shaved. A pin numbering is counterclockwise given from the center of the line in the topside. Note is necessary to the pin arrangement by the Function Block and the macrocell because it a little irregular-ly. In case of XC956-PC44, the macrocells which corresponds to the input/output pins are 4 macrocells in the 6 macrocells. In case of XC957-PC44, they are 4 macrocells in the 7 macrocells. The macrocells which don't correspond to the input/output pins can be used only in the logic circuits inside. The pins colored purple are pins for JTAG. Pin Diagram of XC956-5PC44C FB : Function Block number Pin number FB Macrocell Pin number FB Macrocell GND GCK GCK GCK TDO 9 8 GND 0 GND VccIO.V/5V 9 0 4

33 VccINT 5V GTS VccINT 5V GTS GSR 6 9 TCK TMS TDI Pin Diagram of XC957-5PC44C FB : Function Block number GTS VccINT 5V GTS 40 8 GSR 9 9 TCK TMS TDI VccIO.V/5V GND 0 GND 7 9 TDO GCK GCK GCK GND Macrocell FB Pin number Macrocell FB Pin number

34 VccINT 5V

35 9 XC956 In-System Programmable CPLD December 4, 998 (Version 5.0) * Product Specification Features 5 ns pin-to-pin logic delays on all pins f CNT to 00 MHz 6 macrocells with 800 usable gates Up to 4 user pins 5 V in-system programmable (ISP) - Endurance of 0,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 6V8 Function Block - 90 product terms drive any or all of 8 macrocells within Function Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std 49. boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 4 ma outputs. V or 5 V capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 44-pin VQFP, and 48-pin CSP packages Description The XC956 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of two 6V8 Function Blocks, providing 800 usable gates with propagation delays of 5 ns. See Figure for the architecture overview. Power Management Power dissipation can be reduced in the XC956 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: I CC (ma) = MC HP (.7) + MC LP (0.9) + MC (0.006 ma/mhz) f Where: MC HP = Macrocells in high-performance mode MC LP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure shows a typical calculation for the XC956 device. Typical I CC (ma) (50) (0) High Performance Low Power 0 50 Clock Frequency (MHz) Figure : Typical I CC vs. Frequency For XC (8) (50) X590 December 4, 998 (Version 5.0)

36 XC956 In-System Programmable CPLD JTAG Port JTAG Controller In-System Programming Controller 8 6 Function Block Macrocells to 8 Blocks FastCONNECT Switch Matrix 8 6 Function Block Macrocells to 8 /GCK /GSR /GTS X599 Figure : XC956 Architecture Note: Function Block outputs (indicated by the bold line) drive the Blocks directly December 4, 998 (Version 5.0)

37 XC956 In-System Programmable CPLD Absolute Maximum Ratings Symbol Parameter Value Units V CC Supply voltage relative to GND -0.5 to 7.0 V V IN DC input voltage relative to GND -0.5 to V CC V V TS Voltage applied to -state output with respect to GND -0.5 to V CC V T STG Storage temperature -65 to +50 C T SOL Max soldering temperature (0 /6 in =.5 mm) +60 C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Symbol Parameter Min Max Units V CCINT Supply voltage for internal logic and input buffer V (4.5) (5.5) V CCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.5 (5.5) V Supply voltage for output drivers for. V operation.0.6 V V IL Low-level input voltage V V IH High-level input voltage.0 V CCINT +0.5 V V O Output voltage 0 V CCIO V Note. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol Parameter Min Max Units t DR Data Retention 0 - Years N PE Program/Erase Cycles 0,000 - Cycles December 4, 998 (Version 5.0)

38 XC956 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 5 V operation I OH = -4.0 ma.4 V V CC = Min Output high voltage for. V operation I OH = -. ma V CC = Min.4 V V OL Output low voltage for 5 V operation I OL = 4 ma 0.5 V V CC = Min Output low voltage for. V operation I OL = 0 ma 0.4 V V CC = Min I IL Input leakage current V CC = Max ±0.0 µa V IN = GND or V CC I IH high-z leakage current V CC = Max ±0.0 µa V IN = GND or V CC C IN capacitance V IN = GND f =.0 MHz 0.0 pf I CC Operating Supply Current V I = GND, No load ma 0 (Typ) (low power mode, active) f =.0 MHz AC Characteristics Symbol Parameter XC956-5 XC956-6 XC956-7 XC956-0 XC956-5 Units Min Max Min Max Min Max Min Max Min Max t PD to output valid ns t SU setup time before GCK ns t H hold time after GCK ns t CO GCK to output valid ns f CNT 6-bit counter frequency MHz f SYSTEM Multiple FB internal operating frequency MHz t PSU setup time before p-term clock input ns t PH hold time after p-term clock input ns t PCO P-term clock to output valid ns t OE GTS to output valid ns t OD GTS to output disable ns t POE Product term OE to output enabled ns t POD Product term OE to output disabled ns t WLH GCK pulse width (High or Low) ns Note:. f CNT is the fastest 6-bit counter frequency available. f CNT is also the Export Control Maximum flip-flop toggle rate, f TOG.. f SYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. 4 December 4, 998 (Version 5.0)

39 XC956 In-System Programmable CPLD V TEST Device Output R Output Type V CCIO 5.0 V. V V TEST 5.0 V. V R 60 Ω 60 Ω R 0 Ω 60 Ω C L 5 pf 5 pf R C L X5906 Figure : AC Load Circuit Internal Timing Parameters Symbol Parameter Note:. t PTA is multiplied by the span of the function as defined in the family data sheet. XC956-5 XC956-6 XC956-7 XC956-0 XC956-5 Units Min Max Min Max Min Max Min Max Min Max Buffer Delays t IN Input buffer delay ns t GCK GCK buffer delay ns t GSR GSR buffer delay ns t GTS GTS buffer delay ns t OUT Output buffer delay ns t EN Output buffer enable/disable delay ns Product Term Control Delays t PTCK Product term clock delay ns t PTSR Product term set/reset delay ns t PTTS Product term -state delay ns Internal Register and Combinatorial delays t PDI Combinatorial logic propagation delay ns t SUI Register setup time ns t HI Register hold time ns t COI Register clock to output valid time ns t AOI Register async. S/R to output delay ns t RAI Register async. S/R recovery before clock ns t LOGI Internal logic delay ns t LOGILP Internal low power logic delay ns Feedback Delays t F FastCONNECT matrix feeback delay ns Time Adders t PTA Incremental Product Term Allocator delay ns t SLEW Slew-rate limited delay ns December 4, 998 (Version 5.0) 5

40 XC956 In-System Programmable CPLD XC956 Pins Function Block Macrocell PC44 VQ44 CS48 BScan Order XC956 Global, JTAG and Power Pins Notes Function Block Macrocell PC44 VQ44 CS48 BScan Order 40 D D7 5 4 C E B7 99 [] 4 6 E6 45 [] C E B6 9 [] F6 9 [] 6 8 A G7 6 [] 7 7 A7 87 [] 7 8 G6 8 9 C F B G A F4 4 7 B G4 4 8 A 7 7 E 8 8 B 69 9 F B G C F C E D E Note: [] Global control pin Note: [] Global control pin Pin Type PC44 VQ44 CS48 /GCK 5 4 B7 /GCK 6 44 B6 /GCK 7 A7 /GTS 4 6 E6 /GTS 40 4 F6 /GSR 9 G7 TCK 7 A TDI 5 9 B TDO 0 4 G TMS 6 0 A V CCINT 5 V,4 5,5 C,F7 V CCIO. V/5 V 6 G GND,0, 7,4,5 A5, D, F No Connects C4, D, D4, E4 Notes 6 December 4, 998 (Version 5.0)

41 XC956 In-System Programmable CPLD Ordering Information XC956-5 PC 44 C Device Type Speed Temperature Range Number of Pins Package Type Speed Options -5 5 ns pin-to-pin delay -0 0 ns pin-to-pin delay ns pin-to-pin delay -6 6 ns pin-to-pin delay -5 5 ns pin-to-pin delay Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) VQ44 44-Pin Thin Quad Pack (VQFP) CS48 48-Pin Chip Scale Package (CSP) Temperature Options C = Commercial (0 C to +70 C) I = Industrial ( 40 C to +85 C) Component Availability Pins Type C = Commercial (0 C to +70 C), I = Industrial ( 40 C to +85 C) Revision Control Plastic PLCC Plastic VQFP Plastic CSP Code PC44 VQ44 CS48 5 C,I C,I - 0 C,I C,I C XC956 7 C,I C,I C 6 C C - 5 C C C Date Reason 6//98 Revise datasheet to reflect new CSP package pinouts & ordering code. //98 Revise datasheet to reflect new AC characteristics and Internal Timing Parameters. /04/98 Revise datasheet to remove PCI compliancy statement and remove t LF. December 4, 998 (Version 5.0) 7

42 PLCC socket PLCC socket is used to mount CPLD device on the printed board. PLCC is the abbreviation of "Plastic Leaded Chip Carrier". There are lead pins to connect a printed board with the bottom of the socket. Because it is 0. inches in the pin interval, it is possible to mount on the universal printed board, too. To know the direction of the socket, you see from the top and you make a diagonal corner the upper left. The center of the line in the topside is the st pin. I think that you can find the mark of the triangle which shows the st pin inside the socket which puts CPLD. As for the size of the socket, 44 pins are about mm x mm and 84 pins are about 7 mm x 7mm. The figure on the left shows a pin diagram of the bottom view for 44 pins. It is necessary to be careful so as not to make a mistake because there are many numbers of the pins. The figure below shows a pin diagram of the bottom view for 84 pins.

43 Method of removing a device A thin screwdriver can be used to remove CPLD device from the PLCC socket. There are ditches for removing at the corner of PLCC socket. Put the tip of the screwdriver in the ditch, and make the top lift a device and remove it. Do alternately with the side of the opposite angle and lift slowly. Because there is possibility to give the damage to the device when handling violently, remove it carefully.