Lead- Free Package Options Available! Input Bus. Description

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1 Lead- Free Package Options Available! isplsi 064VE.V In-System Programmable High Density SuperFAST PLD Features SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC 000 PLD Gates 64 and Pin Versions, Four Dedicated Inputs 64 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 00% Functional, JEDEC and Pinout Compatible with isplsi 064V Devices.V LOW VOLTAGE 064 ARCHITECTURE Interfaces with Standard 5V TTL Devices HIGH-PERFORMANCE E CMOS TECHNOLOGY fmax 80MHz Maximum Operating Frequency tpd.5ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE.V In-System Programmability (ISP ) Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping 00% IEEE 49. BOUNDARY SCAN TESTABLE THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAs Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity LEAD-FREE PACKAGE OPTIONS Functional Block Diagram A0 A A A Description GLB B7 B6 B5 B4 Global Routing Pool (GRP) Logic Array D Q D Q D Q D Q A4 A5 A6 A7 B B B B0 09A/064V The isplsi 064VE is a High Density Programmable Logic Device available in 64 and -pin versions. The device contains 64 Registers, four Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 064VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 00% IEEE 49. Boundary Scan Testable. The isplsi 064VE offers non-volatile reprogrammability of the logic, as well as the interconnect, to provide truly reconfigurable systems. The basic unit of logic on the isplsi 064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A B7 (see Figure ). There are a total of 6 GLBs in the isplsi 064VE device. Each GLB is made up of four macrocells. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Copyright 004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 974, U.S.A. August 004 Tel. (50) ; -800-LATTICE; FAX (50) ; 064ve_09

2 Functional Block Diagram Figure. isplsi 064VE Functional Block Diagram (64- and - Versions) GOE 0 GOE Generic Logic Blocks (GLBs) Generic Logic Blocks (GLBs) Megablock Megablock B7 B6 B5 B4 B7 B6 B5 B A0 A A A Global Routing Pool (GRP) B B B B A0 A A A Global Routing Pool (GRP) B B B B TDI/IN 0 TMS/IN A4 A5 A6 A7 TCK/IN TDO/IN TDI/IN 0 TDO/IN A4 A5 A6 A7 GOE0/IN TMS/IN RESET CLK 0 CLK CLK CLK 0 CLK CLK Y0 Y Y 09B/064VE GOE/Y0 RESET/Y TCK/Y 09B/064VE.IO The VE contains 64 cells, while the - version contains cells. Each cell is directly connected to an pin and can be individually programmed to be a combinatorial input, output or bi-directional pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4 ma or sink 8 ma. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5-Volt signal levels to support mixed-voltage systems. Eight GLBs, or 6 cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of or 6 universal cells by two or one ORPs. Each isplsi 064VE device contains two Megablocks. Y, Y) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the isplsi 064VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 064VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0,

3 Absolute Maximum Ratings Supply Voltage V cc to +5.4V Input Voltage Applied to +5.6V Off-State Output Voltage Applied to +5.6V Storage Temperature to 50 C Case Temp. with Power Applied to 5 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER MIN. MAX. UNITS VIL VIH Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial T A 0 C to + 70 C T A -40 C to + 85 C.0.0 V 0.5 SS.0.6 V.6 V 0.8 V 5.5 V Table -0005/064V Capacitance (TA5 C, f.0 MHz) C C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS Dedicated Input Capacitance 8 pf V.V, V 0.0V Capacitance 6 pf V.V, V 0.0V CC C Clock and Global Output Enable Capacitance 0 pf V.V, V 0.0V CC Y CC IN Table -0006/064VE Erase Reprogram Specifications PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 0000 Cycles Table -0008/064VE

4 Switching Test Conditions Input Pulse Levels to.0v Figure. Test Load Input Rise and Fall Time Input Timing Reference Levels.5 ns 0% to 90%.5V +.V Output Timing Reference Levels Output Load -state levels are measured 0.5V from steady-state active level. Output Load Conditions (see Figure ).5V See Figure Table -000/064VE Device Output R R CL* Test Point TEST CONDITION R R CL A 6Ω 48Ω 5pF B C Active High Active Low Active High to Z at V OH-0.5V Active Low to Z at V OL+0.5V 48Ω 5pF 6Ω 48Ω 5pF 48Ω 5pF 6Ω 48Ω 5pF Table -0004/064V *CL includes Test Fixture and Probe Capacitance. 0A/064V DC Electrical Characteristics SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS, 4 ICC Over Recommended Operating Conditions PARAMETER CONDITION MIN. TYP. MAX. UNITS Output Low Voltage I OL 8 ma 0.4 V Output High Voltage I OH -4 ma.4 V Input or Low Leakage Current 0V V V (Max.) -0 µa Input or High Leakage Current Input Low Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IN 0V V IN VIL 0V V IN VIL V CC.V, V OUT 0.5V V IL 0.0V, V IH.0V f MHz CLOCK. One output at a time for a maximum duration of one second. V OUT 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested.. Measured using four 6-bit counters.. Typical values are at V CC.V and T A 5 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC IL (V CC 0.)V V IN V V V 5.5V CC IN CC µa µa µa µa ma ma Table -0007/064VE 4

5 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd A Data Propagation Delay ns fmax A Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback( tsu + tco) 8 MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass..0 ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass.5.5 ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu 9 GLB Reg. Setup Time before Clock ns tco A 0 GLB Reg. Clock to Output Delay. 4.5 ns th GLB Reg. Hold Time after Clock ns tr A Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High.6.5 ns twl 9 External Synchronous Clock Pulse Duration, Low.6.5 ns. Unless noted otherwise, all parameters use a GRP load of four, 0 PTXOR path, ORP and Y0 clock.. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section. Table -000A/064VE v.0.0 5

6 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd A Data Propagation Delay ns fmax A Clock Frequency with Internal Feedback 5 00 MHz fmax (Ext.) 4 Clock Frequency with External Feedback ( tsu + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle 4 00 MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu 9 GLB Reg. Setup Time before Clock ns tco A 0 GLB Reg. Clock to Output Delay ns th GLB Reg. Hold Time after Clock ns tr A Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns. Unless noted otherwise, all parameters use a GRP load of four, 0 PTXOR path, ORP and Y0 clock.. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section. Table -000B/064VE v.0.0 6

7 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio 0 Input Buffer Delay ns tdin Dedicated Input Delay 0.8. ns GRP tgrp GRP Delay ns GLB t4ptbpc 4 Product Term Bypass Path Delay (Combinatorial)..4 ns t4ptbpr 4 4 Product Term Bypass Path Delay (Registered).6.9 ns tptxor 5 Product Term/XOR Path Delay..9 ns t0ptxor 6 0 Product Term/XOR Path Delay..9 ns txoradj 7 XOR Adjacent Path Delay..9 ns tgbp 8 GLB Register Bypass Delay ns tgsu 9 GLB Register Setup Time before Clock 0.6. ns tgh 0 GLB Register Hold Time after Clock.7.8 ns tgco GLB Register Clock to Output Delay ns tgro GLB Register Reset to Output Delay ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to Cell Delay.9.9 ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay..5 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay..5 ns tsl 9 Output Slew Limited Delay Adder.8.0 ns toen 40 Cell OE to Output Enabled..0 ns todis 4 Cell OE to Output Disabled..0 ns tgoe 4 Global Output Enable..0 ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/ 44 Clock Delay, Y or Y to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros..5.6 ns Table -006A/064VE v.0.0 7

8 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio 0 Input Buffer Delay ns tdin Dedicated Input Delay.7.5 ns GRP tgrp GRP Delay..8 ns GLB t4ptbpc 4 Product Term Bypass Path Delay (Combinatorial).7 5. ns t4ptbpr 4 4 Product Term Bypass Path Delay (Registered) ns tptxor 5 Product Term/XOR Path Delay ns t0ptxor 6 0 Product Term/XOR Path Delay ns txoradj 7 XOR Adjacent Path Delay ns tgbp 8 GLB Register Bypass Delay ns tgsu 9 GLB Register Setup Time before Clock..7 ns tgh 0 GLB Register Hold Time after Clock ns tgco GLB Register Clock to Output Delay ns tgro GLB Register Reset to Output Delay.. ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to Cell Delay ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay.5.7 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.6.6 ns tsl 9 Output Slew Limited Delay Adder.0.0 ns toen 40 Cell OE to Output Enabled.4.4 ns todis 4 Cell OE to Output Disabled.4.4 ns tgoe 4 Global Output Enable ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/ 44 Clock Delay, Y or Y to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros ns Table -006B/064VE v.0.0 8

9 isplsi 064VE Timing Model Cell GRP GLB ORP Cell Feedback Ded. In Pin (Input) Reset # Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #0 # #4 #8 #45 0 PT XOR Delays #5, 6, 7 Comb 4 PT Bypass # GLB Reg Delay D Q RST #9, 0,, #7 ORP Delay #6 #8, 9 Pin (Output) Control PTs #, 4, 5 RE OE CK #40, 4 Y0,, #4, 44 GOE 0, #4 049/064 Derivations of tsu, th and tco from the Product Term Clock tsu.ns Logic + Reg su - Clock (min) (tio + tgrp + t0ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#0 + # + #6) + (#9) - (#0 + # + #5) ( ) + (0.6) - ( ) th tco.ns 6.ns Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t0ptxor) (#0 + # + #5) + (#0) - (#0 + # + #6) ( ) + (.7) - ( ) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#0 + # + #5) + (#) + (#6 + #8) ( ) + (0.) + (. +.) Note: Calculations are based on timing specifications for the isplsi 064VE-80L. Table -004/064VE 9

10 Power Consumption Power consumption in the isplsi 064VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure shows the relationship between power and operating speed. Figure. Typical Device Power Consumption vs fmax isplsi 064VE ICC (ma) fmax (MHz) Notes: Configuration of four 6-bit counters Typical current at.v, 5 C ICC can be estimated for the isplsi 064VE using the following equation: ICC(mA) 8 + (# of PTs * 0.67) + (# of Nets * Fmax * ) Where: # of PTs Number of Product Terms used in design # of nets Number of Signals used in device Max freq Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions (.V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 07/064VE 0

11 64- Signal Descriptions Signal Name Description RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE Global Output Enable input pins. Y0, Y, Y Dedicated Clock Input These clock inputs are connected to one of the clock inputs of all the GLBs in the device. Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input This pin performs two functions. () When is logic low, it functions as a serial data input pin to load programming data into the device. When is high, it functions as a dedicated input pin. TCK/IN Input This pin performs two functions. () When is logic low, it functions as a clock pin for the Boundary Scan state machine. () When is high, it functions as a dedicated input pin. TMS/IN Input This pin performs two functions. () When is logic low, it functions as a mode control pin for the Boundary Scan state machine. () When is high, it functions as a dedicated input pin. TDO/IN Output/Input This pin performs two functions. () When is logic low, it functions as an output pin to read serial shift register data. () When is high, it functions as a dedicated input pin. Ground () Vcc NC No Connect Input/Output Pins These are the general purpose pins used by the logic array.. NC pins are not to be connected to any active signals, or. - Signal Descriptions Signal Name GOE 0/IN GOE /Y0 RESET/Y Description This pin performs one of two functions. It can be programmed to function as a Global Output Enable pin or a Dedicated Input pin. This pin performs one of two functions. () It can be programmed to function as a GLobal Output Enable or a Dedicated Clock input. () This clock input is connected to one of the clock inputs of all GLBs on the device. This pin performs two functions: () Active Low (0) Reset pin which resets all of the registers in the device. () When active low (0), it functions as a dedicated clock input. Input Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input This pin performs two functions. () When is logic low, it functions as a serial data input pin to load programming data into the device. () When is high, it functions as a dedicated input pin. TMS/IN Input This pin performs two functions. () When is logic low, it functions as a mode control pin for the Boundary Scan state machine. () When is high, it functions as a dedicated input pin. TDO/IN Output/Input This pin performs two functions. () When is logic low, it functions as an output pin to read serial shift register data. () When is high, it functions as a dedicated input pin. TCK/Y Input This pin performs two functions. () When is logic low, it functions as a clock pin for the Boundary Scan state machine. () When is high, it functions as a dedicated clock input. Ground () Vcc NC No Connect Input/Output pins These are the general purpose pins used by the logic array.. NC pins are not to be connected to any active signals, or.

12 64- Signal Locations Signal - Signal Locations 00-Ball cabga 00-Pin TQFP RESET D GOE 0, GOE F9, E 6, Y0, Y, Y E, F6, F8 0, 65, 60 E5 5 TDI/IN 0 F 6 TCK/IN G0 59 TMS/IN J5 7 TDO/IN B6 87 B7, F, G9, K6 4, 9, 6, 86 A5, E, F0, J4, 6, 6, 89 NC A6, A8, C, C4, D, D6, D8, E7, E9, E0, F4, G, G5, H7, H8, K, K5 4, 9,, 5,, 8, 44, 50, 54, 64, 66, 7, 75, 8, 88, 94, 00. NC pins are not to be connected to any active signals, or. Signal 44-Pin TQFP 44-Pin PLCC GOE 0/ IN 40 GOE /Y0 5 RESET/ Y TDI/IN TMS/IN 0 6 TDO/IN 8 4 TCK/Y 7 7, 9, 6, 8, 4 NC. NC pins are or. not to be connected to any active signals, Locations Signal cabga TQFP TQFP PLCC 0 G F E4 9 7 H G 9 5 J H K J K H 9 7 J 0 8 G4 9 H K H F J K H K G J K J K J J H H G G D0 67 E F C D9 7 7 B0 7 8 C A B A C B D C A C E B A4 9 5 C5 9 5 A 95 5 D B A B A 58 B 59 B 60 C 5 6 C 6 6 D4 7 6 D 8

13 Signal Configuration isplsi 064VE 00-Ball cabga Signal Diagram (0.8mm Ball Pitch/0.0 x 0.0mm Body Size) A 9 4 NC NC A B TDO/ IN B C NC NC 60 6 C D 6 NC NC 44 RESET NC D E NC NC NC 48 Y0 GOE E F GOE Y Y NC TDI/ IN 0 F G TCK/ IN NC 0 NC 4 0 G H 9 8 NC NC H J TMS/ IN 8 5 J K NC NC 4 isplsi 064VE Bottom View K 00-BGA/064VE NCs are not to be connected to any active signals, or. Note: Ball A indicator dot on top side of package.

14 Pin Configuration isplsi 064VE 00-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/4.0 x 4.0mm Body Size) NC NC NC TDO/IN NC NC NC Y0 RESET GOE TDI/IN 0 0 NC NC isplsi 064VE Top View NC NC 5 4 NC Y NC GOE 0 Y TCK/IN NC NC 4 5 TMS/IN NC NC 0 4 NC. NC pins are not to be connected to any active signals, or. 00 TQFP/064VE 4

15 Pin Configuration isplsi 064VE 44-Pin PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size) TMS/IN GOE/Y0 TDI/IN 0 RESET/Y TCK/Y GOE 0/IN TMS/IN GOE/Y isplsi 064VE Top View RESET/Y TCK/Y TDI/IN TDO/IN TDO/IN GOE 0/IN isplsi 064VE Top View PLCC/064VE Pin Configuration isplsi 064VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/0.0 x 0.0mm Body Size) 44 TQFP/064VE 5

16 Part Number Description isplsi 064VE XXX X XXXXX X Device Family Device Number Speed MHz fmax MHz fmax 5 5 MHz fmax MHz fmax Grade Blank Commercial I Industrial Package T00 00-Pin TQFP TN00 Lead-Free 00-Pin TQFP B00 00-Ball cabga T44 44-Pin TQFP TN44 Lead-Free 44-Pin TQFP J44 44-Pin PLCC Power L Low isplsi 064VE Ordering Information Conventional Packaging FAMILY isplsi isplsi fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi 064VE-80LT00 00-Pin TQFP isplsi 064VE-80LB00 00-Ball cabga 80.5 isplsi 064VE-80LT44 44-Pin TQFP isplsi 064VE-00LT00 00-Pin TQFP isplsi 064VE-00LB00 00-Ball cabga isplsi 064VE-00LJ44 44-Pin PLCC isplsi 064VE-00LT44 44-Pin TQFP isplsi 064VE-5LT00 00-Pin TQFP isplsi 064VE-5LB00 00-Ball cabga isplsi 064VE-5LJ44 44-Pin PLCC isplsi 064VE-5LT44 44-Pin TQFP COMMERCIAL isplsi 064VE-00LT00 isplsi 064VE-00LB00 isplsi 064VE-00LJ44 isplsi 064VE-00LT44 INDUSTRIAL 00-Pin TQFP 00-Ball cabga 44-Pin PLCC 44-Pin TQFP FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi 064VE-5LT00I 00-Pin TQFP isplsi 064VE-5LT44I 44-Pin TQFP Table -004A/064VE Table -004B/064VE 6

17 isplsi 064VE Ordering Information (Cont.) Lead-Free Packaging FAMILY isplsi fmax (MHz) tpd (ns) s COMMERCIAL ORDERING NUMBER PACKAGE isplsi 064VE-80LTN00 Lead-Free 00-Pin TQFP 80.5 isplsi 064VE-80LTN44 Lead-Free 44-Pin TQFP isplsi 064VE-00LTN00 Lead-Free 00-Pin TQFP isplsi 064VE-00LTN44 Lead-Free 44-Pin TQFP isplsi 064VE-5LTN00 Lead-Free 00-Pin TQFP isplsi 064VE-5LTN44 Lead-Free 44-Pin TQFP isplsi 064VE-00LTN00 Lead-Free 00-Pin TQFP 00 0 isplsi 064VE-00LTN44 Lead-Free 44-Pin TQFP INDUSTRIAL FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi isplsi 064VE-5LTN00I Lead-Free 00-Pin TQFP isplsi 064VE-5LTN44I Lead-Free 44-Pin TQFP 7