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1 CPLD Development Platform ST105 Learning Material Ver. 1.1 An ISO 9001 : 2000 company 94, Electronic Complex, Pardesipura Indore India Tel : Fax : e mail : info@scientech.bz Websites:

2 Scientech Technologies Pvt. Ltd. 2

3 CPLD Development Platform ST105 Table of Contents 1. Overview 4 2. Features 5 3. Technical Specifications 6 4. Functional Description 7 5. Block Diagram 8 6. XC95108PC84 Pin Details 8 7. CPLD Functional Block Details Connector Details CPLD Architecture Xilinx Web Pack Introduction designing in Xilinx ISE 8.1i Web Pack Sample Codes VLSI Design Cycle Frequently Asked Questions Appendix Warranty List of Accessories 70 Scientech Technologies Pvt. Ltd. 3

4 Overview The ST105 CPLD Development Board featuring the Xilinx CPLD XC95108PC84 circuit board provides an inexpensive and expandable platform to design and implement digital circuits of all kinds Scientech Technologies Pvt. Ltd. 4

5 Features Explanation of System Architecture CPLD (Xilinx XC95108PC84) Development Board. 108 macro cells with 2400 usable gates, 84 users I/O pins. Xilinx ISE 8.1i Web packs Development Software CD. Sample Code for Board Testing & Lab work. Operational Manual for reference. Functional Explanation of Development Boards Detachable 54 I/Os for easy to experiment. 16 DIP Switches for Logic Inputs. 16 LED Outputs for Logic Outputs. 6 Digit 7-Segment Multiplexed Display. Pushbutton switches for Pulse. ST105 can also be used as an XC95108PC84 programmer. Scientech Technologies Pvt. Ltd. 5

6 Xilinx Family: Device Density: Configuration Methods: Technical Specifications : CPLD : XC95108 : Package: PC84 : 108 macro cells. : 2400 usable gates Number of I/O's : 84Nos : JTAG Interface (Boundary Scan) Peripheral interface : includes, RS232 interface. On board : +5V supply to CPLD & other hardware circuit. On board : Crystal 8MHz. 60 pin, : Header connector for external I/O's I/O Details : : 16 Logic Inputs : 16 Logic Outputs : 6 Digit 7-Segment Multiplexed Display : 4 Pulsed input. Power Supply : VAC, 50,60Hz Experiments which can be performed : 1. Basic Digital Logic 2. Multiplexer 3. De-multiplexer 4. Counter 5. Register 6. Encoder 7. Decoder 8. CPU 9. Memory 10. Address Decoder 11. Traffic Light Controller Design using HDL. 12. Design Bank Token Display 13. Serial Interface bit LED Flasher & many more Scientech Technologies Pvt. Ltd. 6

7 ST105 Functional Description The ST105 has been designed specifically to work with Xilinx ISE CAD tools, including the free WebPack tools available from the Xilinx website. The low-cost, standard expansion connectors allow new peripheral boards, including wire-wrap or manually soldered boards, to be quickly designed and used. The ST105 board ships with a power supply and programming cable, so designs can be implemented immediately without the need for any additional hardware. The ST105 board has been designed to offer an unembellished, low-cost system for designers who need a flexible platform to gain exposure to the XC9500 CPLD device family, or for those who need to rapidly prototype CPLD-based designs. The ST105 board provides only the essential supporting devices for the XC9500 CPLD device and routes all available CPLD signals to standard expansion connectors. Included on the board are 5V DC regulators, a JTAG configuration circuit that uses a standard parallel cable for programming. pl g. ltin su on -c hik w. ww Figure 1 Scientech Technologies Pvt. Ltd. 7

8 Block Diagram XC95108PC84 Pin Details Figure 2 DIP Switch CPLD Pin Number DIP1 1 DIP2 2 DIP3 3 DIP4 4 DIP5 11 DIP6 7 DIP7 6 DIP8 5 DIP9 13 DIP10 71 DIP11 72 DIP12 75 DIP13 82 DIP14 81 DIP15 80 DIP16 79 LED Output CPLD Pin Number LED1 14 LED2 15 LED3 17 LED 4 18 LED5 19 LED6 20 Scientech Technologies Pvt. Ltd. 8

9 LED7 21 LED8 23 LED9 24 LED10 25 LED11 26 LED12 31 LED13 57 LED14 58 LED15 61 LED16 62 Display Output CPLD Pin Number a or 0 70 b or 1 32 c or 2 33 d or 3 34 e or 4 35 f or 5 36 g or 6 37 DP 39 C1 63 C2 65 C3 66 C4 67 C5 68 C6 69 Pushbutton Input CPLD Pin Number SW1 41 SW2 40 SW4 43 SW5 44 Serial Port Details CPLD Pin Number Tx1 45 Rx1 47 JTAG CPLD Pin Number TMS 29 TCK 30 TDI 28 TDO 59 Scientech Technologies Pvt. Ltd. 9

10 CPLD Functional Block Details Functional Block PC84 Pin No. Functional Block PC84 Pin No GND 49 GND GND JTAG - TDO GND VCC_IO 22 VCC_IO GND JTAG - TDI JTAG - TMS JTAG - TCK VCC_INT VCC_INT VCC_INT GND Scientech Technologies Pvt. Ltd. 10

11 Connector Details Global Clock CPLD Pin Number GCK Pin IO Details 60 Pin Connector IO Details Connector 1 Ground 2 Ground 3 DIP1 4 DIP2 5 DIP3 6 DIP4 7 DIP5 8 DIP6 9 DIP7 10 DIP8 11 DIP9 12 DIP10 13 DIP11 14 DIP12 15 DIP13 16 DIP14 17 DIP15 18 DIP16 19 LED1 20 LED2 21 LED3 22 LED4 23 LED5 24 LED6 25 LED7 26 LED8 27 LED9 28 LED10 29 LED11 30 LED12 31 LED13 32 LED14 33 LED15 34 LED16 35 C1 36 C2 37 C3 38 C4 39 C5 40 C6 41 A 42 B 43 C 44 D 45 E 46 F 47 G 48 DP 49 SW2 50 SW1 51 SW4 52 SW5 53 TX1 54 NC 55 RX1 56 NC 57 NC 58 NC 59 Ground 60 Ground Scientech Technologies Pvt. Ltd. 11

12 CPLD Architecture Complex Programmable Logic Devices (CPLD) : Since their introduction years ago, programmable logic devices such as the 16V8 and 22V10 have been very flexible workhorses of digital design. As IC technology advanced, there was naturally great interest in creating larger PLD architectures to take advantage of increased chip density. The question is, why didn't manufacturers just scale the existing architectures? For example, if DRAM densities increased by a factor of 64 over the last 10 years, why couldn't manufacturers scale the 16V8 to create a "128V64"? Such a device would have 64 input pins, 64 I/O pins, and some number of 128-variable product terms (say, 8) for each of its 128 logic macrocells. It could combine the functions of a larger collection of 16V8s and offer terrific performance and flexibility in using any input in any output function. A 128V64 would be very flexible, but it would not have very good performance. Unlike the 16V8, which has 32 inputs (16 signals and their complements) per AND term, this device would have 256. Due to capacitive effects, leakage currents, and so on, such a large wired-and structure would be at least eight times slower than the 16V8's AND array. General CPLD architecture Figure 3 Worse from a manufacturer's point of view, a 128V64 would not make very costeffective use of chip area. It would use about 64 times the chip area of a l6v8, but provide the same number of inputs and outputs as only eight I6V8s. That is for n times as much logic (in terms of inputs, outputs and AND terms), the 128V64 uses n 2 as much chip area. In terms of efficiency of silicon use, a clever designer would be better off partitioning a desired function into eight 16V8s, if such a partitioning were possible. This is where the idea of complex programmable logic devices (CPLDs) came from. As shown in the Figure 3, a CPLD is just a collection of individual LDs on a single chip, accompanied by a programmable interconnection structure that allows the PLDs to be hooked up to each other on-chip in the same way that a clever designer might do Scientech Technologies Pvt. Ltd. 12

13 with discrete PLDs off-chip. Here, the chip area for n times as much logic is only n times the area of a single PLD plus the area of the programmable interconnect structure. Different manufacturers have taken many different approaches to the general architecture shown in the figure Areas in which they differ include the individual PLDs (AND array and macrocells), the input/output blocks, and the programmable interconnect. We'll discuss each of these areas in the rest of this section, using the Xilinx 9500-series CPLD architecture as a representative example. 1.1 Xilinx XC9500 CPLD Family : The Xilinx XC9500 series is a family of CPLDs with a similar architecture but varying numbers of external input/output (I/O) pins and internal PLDs (which Xilinx calls function blocks FBs). As we'll see later, each internal PLD has 36 inputs and 18 macrocells and outputs and might be called a "36V18." As shown in Table below, devices in the family are named according to the number of macrocells they contain. The smallest has 2 FBs and 36 macrocells, and the largest has 16 FBs and 288 macrocells. Another important feature of this and most CPLD families is that a given chip, such as the XC95108, is available in several different packages. This is important not only to accommodate different manufacturing practices but also to provide some choice and potential savings in the number of external I/O pins provided. In most applications, it is not necessary for all internal signals of a state machine or subsystem to be visible to and used by the rest of the system. So, even though the XC95108 has 108 internal macrocells, the outputs of at most 69 of them can be connected externally in the 84-pin-PLCC version of the device. In fact, many of the 69 I/O pins would typically be used for inputs, in which case even fewer outputs would be visible externally. That's OK; the remaining macrocell outputs are still quite usable internally, since they can be hooked up internally through the CPLD's programmable interconnect. Macro-cells whose outputs are usable only internally are sometimes called buried macrocells. Figure 4 Scientech Technologies Pvt. Ltd. 13

14 Another important dimension of the above table is the horizontal one. All but two of the packages support at least two different devices in the same package and, as it turns out, with compatible pinouts. This is a life-saver in making last-minute design changes. For example, suppose you were to target a design to an XC9572 in an 84-pin PLCC. You might find that the 69 I/O pins of the device are quite adequate. You would like to use the XC9572 for its low cost, but you might be a little nervous if your initial design used 68 out of the 72 available internal macrocells (I know that I would be!). Based on the above table, it is quit clear you can always move up to the XC95108 in the same package and pick up another 36 macrocells. Figure 5 is a block diagram of the internal architecture of a typical XC9500-family CPLD. Each external I/O pin can be used as an input, an output, or a bidirectional pin according to the device's programming, as discussed later. The pins at the bottom of the figure can also be used for special purposes. Any of three pins can be used as "global clocks" (GCK); as we'll see later, each macro-cell can be programmed to use a selected clock input. One pin can be used as a "global set/reset" (GSR); again, each macrocell can programmably use this signal as an asynchronous preset or clear. Finally, two or four pins (depending on device) can be used as "global three-state controls" (GTS); one of these signals can be selected in each macrocell to outputenable the corresponding output driver when the macrocell's output is hooked up to an external I/O pin. Architecture of Xilinx 9500-family CPLDs Figure 5 Only four FBs are shown in the figure, but the XC9500 architecture scales to accommodate 16 FBs in the XC Regardless of the specific family member, Scientech Technologies Pvt. Ltd. 14

15 each FB programmably receives 36 signals from the switch matrix. The inputs to the switch matrix are the 18 macrocell outputs from each of the FBs and the external inputs from the I/O pins. We'll say more about how the switch matrix hooks things up in Section 1.4. Each FB also has 18 outputs that run "under" the switch matrix as drawn in Figure 6-38 and connect to the I/O blocks. These are merely the output-enable signals for the I/O-block output drivers; they're used when the FB macrocell's output is hooked up to an external I/O pin. 1.2 Function-Block Architecture : The basic structure of an XC9500 FB is shown in Figure 6 The programmable AND array has just 90 product terms. Compared to 16V8- and 22V10-style PLDs, the XC9500 and most CPLD macrocells have fewer AND terms per macrocell where the 16V8 has 8 and the 22V10 has 8-16, the XC9500 has only 5. However, this is not all that bad, because of product-term allocation. Architecture of function block (FB) Figure 6 XC9500 product-term allocator and macrocell Figure 7 Scientech Technologies Pvt. Ltd. 15

16 The XC9500 and other CPLDs have product-term allocators that allow a macrocell's unused product terms to be used by other nearby macrocells in the same FB. Figure 7 is a logic diagram of the XC9500 product-term allocator and macrocell. In this figure, the rectangular boxes labeled S1-S8 are programmable signal-steering elements that connect their input to one of their two or three outputs. The trapezoidal boxes labeled M1-M5 are programmable multiplexers that connect one of their two to four inputs to their output. The five AND gates associated with the macrocell appear on the left hand side of the figure Each one is connected to a signal-steering box whose top output connects the product term to the macrocell's main OR gate G4. Considering just this, only five product terms are available per macrocell. However, the top, sixth input of G4 connects to another OR gate G3 that receives product term from the macrocell's above and below the current one. Any of the macrocell's product terms that are not otherwise used can steered through S1-S5 to be combined in an OR gate G1 whose output can eventually be steered to the macrocell above or below by 38. Before steering these product terms may be combined with product terms from below or above through S6, 37, and G2. Thus, product terms can be "daisy-chained" through successive macrocells to create larger sums of products. In principle, all 90 product terms in the FB could be combined and steered to one macrocell, although that would leave 17 out of the FB's 18 macrocells with no product terms at all. One Way : In a given XC9500 macrocell, you wouldn't normally steer daisy-chained product terms back in the direction from which they came. For example, if product terms are arriving at S6 from above, we can use them locally by having S6 steer them to G3, or S6 can steer them to G2. In the latter case, S8 should steer the output of G2 down to the lower macrocell; there's no point in steering the product terms back up to the upper macrocell. In fact, if S6 and S8 in this macrocell were steering product terms up, and S7 and S8 the macrocell above were steering product terms down, we would have a nasty loop. Besides depriving other macrocells of product terms, daisy-chaining terms has an additional price. A small additional delay is incurred for each "hop" made by steered product terms. This delay can be minimized by careful allocation of product-termhungry macrocells so they are adjacent to macrocells with low product-term requirements. For example, a macrocell can make use of 13 product terms with only one extra hop delay if it is positioned between two macrocells that use only one product term each. The third, middle choice for each of the steering boxes S1-S5 is to use the product term for a "special function." The special functions are flip-flop clock, set, and reset; XOR control; and output enable. Most of these special functions are not normally used. Getting closer to the heart of the macrocell, OR gate G4 forms a sum-of-products expression using all selected product terms and feeds it into XOR gate G5. The other input of G5 can be 0, 1, or a product term, as selected by multiplexer U1. Setting this Scientech Technologies Pvt. Ltd. 16

17 input to 1 inverts G4's sum-of-products expression, so the macrocell can be configured to use either polarity of minimized logic equations. Setting this input to a product term is useful in the design of counters. The product term is arranged to be 1 when the lower-order counter bits are 1 and counting is enabled, and the output of G4 is arranged to be the current value of the counter bit; thus, the counter bit is complemented as required. The macrocell's flip-flop FF1 can be programmed to behave either as a D flip-flop or as a T flip-flop with enable; the latter is also useful in some styles of counter realization. Multiplexer M4 selects the flip-flop's clock input from one of four sources the CPLD's three global clock inputs or a product term. This last choice is a not used in synchronous design methodologies, except in well-defined synchronization applications. The flip-flop also has asynchronous set and reset inputs with input source controlled by multiplexers M2 and M5. In most applications, set or reset would be connected to the CPLD's global set/reset input and would be used only system initialization. However, these inputs can also be used to access an S & latch in which the CLK input is not used, or, if you're very careful, you can use CLK and S or R in synchronization applications. A final multiplexer M3 selects either the flip-flop output or its data input be used as the macrocell output, OUT. This signal is sent to the switch matrix where it can be used by any other macrocell. It is also sent to the I/O blocks' along with a product term selected by S5 that can be used as the output-enable signal PTOE if needed. 1.3 Input/Output-Block Architecture : The structure of the XC9500 I/O block (1OB) is shown in Figure 8 There are seven, count them, seven choices of output-enable signals for the three-state driver buffer. It can be always on, always off, controlled by the product term PTOE from the corresponding macrocell, or controlled by any of up to four global output enables. The global output enables are selectable as active-high or active-low versions of the external GTS pins. The XC9500's IOB is a good example of an important trend in CPLD and FPGA I/O architectures providing many "analog" controls in addition to "logic" ones like output enables. Three different analog controls are provided: Slew-rate control. The rise and fall time of the output signals can be set to be fast or slow. The fast setting provides the fastest possible propagation delay, while the slow setting helps to control transmission-line ringing and system noise at the expense of a small additional delay. Pull-up resistor. When enabled, the pull-up resistor prevents output pins from floating as the CPLD is powered up. This is useful if the outputs are used to drive active-low enable inputs of other logic that is not supposed to be enabled during power up. User-programmable ground. This feature actually reallocates an I/O pin to be a ground pin, not a signal pin at all. This is useful in high-speed, high-slew-rate Scientech Technologies Pvt. Ltd. 17

18 applications. Extra ground pins are needed to handle the high dynamic currents that flow when multiple outputs switch simultaneously. In addition to these features, the XC9500 family provides compatibility with both 5-V and 3.3-V external devices. The input buffer and the internal logic run from a 5-V power supply (VCCINT)- Depending on the operating voltage to external devices, the output driver uses either a 5-V or a 3.3-V supply Notice that the pull-up resistor pulls to the I/O supply voltage, VCCIO. DIODES D1 and D2 are used to clamp voltages above V CCINT or below ground that can occur due to transmission-line ringing. XC9500 I/O Block Figure 8 Scientech Technologies Pvt. Ltd. 18

19 1.4 Switch Matrix : Theoretically, a CPLD's programmable interconnect should allow any internal PLD output or external input pin to be connected to any internal PLD input. Likewise, it should allow any internal PLD output to connect to any external output pin. But if you think about this, you'll see that we're back to the same n 2 problem that we would have in building a 128V64. The case of a typical Xilinx XC9500 family member, the XC95108, shown in Figure 9 There are 108 internal macrocell outputs and 108 external-pin inputs, a total of 216 signals which should be connected as inputs to the switch matrix. Since the XC95108 has 6 FBs with 36 inputs each, the switch matrix should have (coincidentally) 216 outputs, each of which is a 216-input multiplexer driving one input of an FB's AND array. A switch matrix such as the one shown in the figure can be built in a chip as a rectangular structure, with a column for each input, a row for each output, and a pass transistor (or transmission gate) at each cross point to control whether a given input is connected to a given output. But this is still a big structure 216 rows and 216 columns in the example. With today's high-density IC technology, the problem is not so much size but speed. Having a large number of transistors connected to each row or column makes for high capacitance, which makes for slow speed. Therefore, CPLD manufacturers look for ways to reduce the size of the switch matrix. For example, we can observe in Figure 10 that not every switch-matrix input must be connectable to every output. We only need every input to be connectable to some input of each FB, since any FB input can connect to any AND gate within the FB's AND array. Then again, the requirement is not quite as simple as we just stated. Suppose that the switch-matrix output for FB input i(0< i <35) is created by a simple 8-input multiplexer whose inputs are switch-matrix inputs 8i through 8i + 7. There are many interconnection patterns that cannot be accommodated by such a switch matrix. For example, connecting switch-matrix inputs 0-35 to the same FB would not be possible. As soon as switch-matrix input 0 is connected to FB input 0, switch-matrix inputs 1-7 are blocked. Thus, the switch-matrix connectivity requirement must be stated more broadly: For each FB, any combination of switch-matrix inputs must be connectable to some combination of the FB's inputs. Scientech Technologies Pvt. Ltd. 19

20 XC95108 Switch matrix requirements Figure 9 A typical CPLD switch matrix is a compromise between the minimal multiplexer scheme and a full, non-blocking cross-point array. With anything less a non-blocking cross point array, the problem of allocating input-output connections in the switch matrix is nontrivial. For each different CPLD-based design, a set of switch-matrix connections must be found by fitter software provided to the designer by the CPLDs manufacturer. Finding a complete set of connections through a sparse switch matrix is one of those ATP-complete problems that you hear about in computer science. In lay terms, that mean that for some designs, the fitter software may have to run a lot longer than you care to wait to find out whether there is a solution. If the switch matrix has too few cross-points, as in our minimal multiplexer example, even the best fitter software running forever will not be able to find a complete set of connections for some designs. Thus, the design of a CPLD s switch matrix is a compromise between chip performance (speed, area, cost) and fitter-software capabilities. The fitter software usually determines not only the final connections through the switch matrix, but also the assignment of CPLD inputs and outputs to FBs, macrocells, and external pins, and of buried logic to FBs and macrocells. These assignments interact in turn with both the switch-matrix-connection and product-term allocation problems. The solutions to these problems are the secrets of CPLD chip and software design, and are not typically disclosed by CPLD manufacturers. Pin Locking : Another important issue in CPLD chip and software design is pin locking. In most CPLD applications, it s OK to let the fitter software pick any pins that it likes for the device s external input and output signals. However, once the design is complete and a PCB has been fabricated, the designer would like to lock down the pin assignments so they remain the same even if small (or large) changes are made to the design for bug-fixing purposes. This spares everyone the time, expense, and hassle of reworking or redesigning and re-fabricating the PCB. Scientech Technologies Pvt. Ltd. 20

21 Locked pin assignments are typically specified in a file that is read by the fitter software. With early CPLDs and FPGAs, locking down pins before making a small change did not guarantee success the fitter would throw up its hands and complain that it was too constrained. If you unlocked the pins, the fitter could find a new allocation that worked, but it might be completely scrambled from the original. These problems were not necessarily the fault of the fitter software; the CPLDs and FPGAs simply did not have rich enough internal connectivity to support frequent design changes under the constraint of pin locking. The device manufacturers have learned from this experience and improved their internal device architectures to accommodate frequent design changes. For example, some devices contain an output switch matrix that guarantees that any internal macrocell signal can be connected to any external I/O pin. Overview : XILINX Web Pack Introduction This document is intended to assist new entry-level users of the Xilinx ISE/Web Pack software. It uses simple logic circuits to illustrate the various CAD tools in the ISE environment. This document should be referenced while the reader has access to a computer running the Xilinx tools, so that all procedures can be performed as the document proceeds. Background : Over the past several generations, engineers have created Computer Aided Design (CAD) tools to assist in all aspects of modern design. From architectural design, to mechanical engineering, to circuit design, CAD tools have revolutionized the way in which engineers work. Since the 1960 s, CAD tools have been used in digital circuit design to capture a virtual copy of a circuit on a computer, and then to simulate the circuit so that various behaviors could be investigated and modified before the circuit was actually built. Since their inception, CAD tools have been continuously evolving. Modern tools allow very precise simulations (down the Pico second), they allow circuits to be automatically synthesized from an easily written high-level definition, and they allow designs to be reformatted so they can be implemented in a variety of technologies. Starting in the 1980 s, digital engineers could use powerful new technologies to implement complex digital systems on a single chip, right on the desktop. These chips, called Field Programmable Gate Arrays (or FPGAs), and the software used to program them, has revolutionized digital design and ushered in a new class of CAD tools. FPGA CAD software typically includes schematic capture, simulation, implementation, and device programming tools. All of these tools can be started from a single navigator tool that coordinates the files and processes associated with a given design project. The navigator shows all source files, all CAD tools that can be used with the source files, and any output or status messages and files that result from running a given tool. The remainder of the document presents the Xilinx tools, staring with the Project Navigator. Scientech Technologies Pvt. Ltd. 21

22 CDA Tool General Design Flow Figure 10 Scientech Technologies Pvt. Ltd. 22

23 Designing in Xilinx ISE 8.1i Web pack Step 1 : Open the Xilinx software, the following window will appear. Figure 11 Scientech Technologies Pvt. Ltd. 23

24 Step 2 : Go to file menu New Project Click on the New Project Figure 12 Scientech Technologies Pvt. Ltd. 24

25 Step 3 : New Project Wizard will appear Figure 13 give project location and project name of your choice and select the type of Top Level Source for the Project and then click on Next Figure 14 Scientech Technologies Pvt. Ltd. 25

26 Step 4 : Select the Family, Device and Package of the chip. Family : XC9500 CPLDs Device : XC95108 Package : PC84 Then click Next Figure 14 Scientech Technologies Pvt. Ltd. 26

27 Step 5 : New Project Wizard- Create New Source Window will appear click on New Source. Figure 16 Scientech Technologies Pvt. Ltd. 27

28 Step 6 : New Project Wizard Select Source Type select the Source type and give the name to the source then click Next Figure 17 Figure 18 Scientech Technologies Pvt. Ltd. 28

29 Step 7 : New Source Wizard- Define Module. Enter the entity used in design and then click Next. Figure 19 Figure 20 Scientech Technologies Pvt. Ltd. 29

30 New Source Wizard Summary will appear click Finish. Figure 21 Again New Project Wizard- Create New Source window appear click Next Figure 22 Scientech Technologies Pvt. Ltd. 30

31 Step 8 : New Project Wizard Add Existing Sources window will appear. Any existing Source can be added to the project from here. Click on Add Source and add the source from its location. To skip adding any existing source just click on Next. New Project Wizard Project summary will appear click Finish Figure 23 Figure 24 Scientech Technologies Pvt. Ltd. 31

32 Step 9 : Next window appearing will be Figure 25 Close the Design summary by clicking on the 2 nd cross button, shown above close Figure 26 Scientech Technologies Pvt. Ltd. 32

33 Step 10 : Next appearing window should be the below one. If it did not appear then double click on the design file in the source window shown in blue below. This is the source code window and design coding is done in this window. We have taken a small example of two inputs AND gate. Figure 27 Write the design code in the source window below the begin keyword given in blue. For the entity selected earlier we have given the code for two inputs AND gate as Follows : c<=a and b ; As shown in the figure below: Scientech Technologies Pvt. Ltd. 33

34 Then save the source file. Figure 28 Scientech Technologies Pvt. Ltd. 34

35 Step 11 : Now we have to assign the pins on the hardware with the design. So click on the + sign button of the Processes window User Constraints shown in the left and then double click on the Assign Package Pins. As shown in the figure below. Figure 29 Next window appearing will be Project Navigator. In this window the Project Navigator shows the requirement to add an implementation constraint file (UCF) to the Project. Click Yes Scientech Technologies Pvt. Ltd. 35

36 Next appearing Window will be Xilinx PACE Figure 30 Figure 31 Scientech Technologies Pvt. Ltd. 36

37 Step 12 : Now in the Design Object List window give the pin assignments. CPLD pin number are given in the manual. For example, in here as we are designing an AND gate. We will assign the two inputs a and b on DIP switches I1 and I2 and output C on LED D1. Given pin assignments for DIP I1 - p 1 DIP I2 - p 2 LED D1- p14 The pin numbers p1, p2 and p14 are to be entered in the LOC table. After assignment you will see three blue dashes on the device architecture as shown in the window above. These three dashes indicate the assignment of the entity on the device. Now save the file and close the window. (See figure below) Figure 32 Scientech Technologies Pvt. Ltd. 37

38 Step 13 : After closing the above window the next window will be again the Xilinx source code window. Figure 33 Now right click on the Configure Device Impact of the Generate Programming File of the Processes window and then click on the properties. Now change the settings in the properties window. Figure 34 Scientech Technologies Pvt. Ltd. 38

39 Set the properties as shown in the window below and then click Apply and then click OK. Port to be used LPT1 (PC), Baud rate Auto and Configuration Mode Slave Serial. Figure 35 Step 14 : Now double click on the Configure Device Impact. The CAD tool will generate the.jed file for the design to be burned on the device. The process will take some time depending on the design size. Wait for the next window shown below: Figure 36 Scientech Technologies Pvt. Ltd. 39

40 Step 15 : Select the Configure Devices using Boundary Scan (JTAG) in the above window and click Finish. Before doing this check the JTAG cable is connected to the PC and the ST105 JTAG connector and power supply to ST105 is turned ON. Now JTAG chain will be automatically initialized. As shown below: Figure 37 Now we have to add the device as shown in the window appearing. Select the.jed file and click Open Next window appearing will be as follows : Figure 38 Scientech Technologies Pvt. Ltd. 40

41 Figure 39 Step 16 : Now right click on the device and click Program.. And before doing this ensure all connections and setting on the board are correct. JTAG is plugged; Power Supply to the board is On Next window appearing will be as follows : Figure 40 Scientech Technologies Pvt. Ltd. 41

42 Apply the default settings on the window then click on Apply and then click on OK. Next window appearing will be: Figure 41 As the programming completes Program Successful message appears in the end in blue. If Program Failed in red appears then check the hardware settings and all other connections and reprogram the device. Scientech Technologies Pvt. Ltd. 42

43 Sample Code 1 - Multiplexer 4 :1 Verilog HDL Code Sample Codes module Mux_4_1(sel,mux_in,mux_out); input [1:0] sel; input [3:0] mux_in; output mux_out; reg mux_out; always@(sel or mux_in) begin end endmodule case (sel) 2'b00 : mux_out <= mux_in[0]; 2'b01 : mux_out <= mux_in[1]; 2'b10 : mux_out <= mux_in[2]; 2'b11 : mux_out <= mux_in[3]; endcase User Constraints File (UCF) of MUX 4:1 for CPLD XC95108PC84- NET mux_in<0> LOC=P1; # DIP 1 NET mux_in<1> LOC=P2; # DIP 2 NET mux_in<2> LOC=P3; # DIP 3 NET mux_in<3> LOC=P4; # DIP 4 NET sel<1> LOC=p13; # DIP 9 NET sel<0> LOC=P71; # DIP 10 NET mux_out LOC=P14; # LED 1 RTL Schematic : Scientech Technologies Pvt. Ltd. 43

44 Sample Code 2 - LED Flasher : Verilog HDL code - module LED_Flasher(clock,sel,leds,rst); output [15:0]leds; reg [15:0]leds; reg [3:0]counter; input clock; input rst; // 8 MHz system clock // External reset // Output rate select input [2:0]sel; reg div256; reg [3:0]cnt1; // Div by 13 reg [7:0]cnt2; // Div by 2 to 256 reg [5:0]cnt3; // Div by 8 wire clk_out; assign clk_out = cnt3[5]; always@(posedge clock or negedge rst) begin if (!rst) begin cnt1 <= 8'b0; end else if (cnt1 == 4'b1100) // Div by 13 begin cnt1 <= 4'b0000; end else begin cnt1 <= cnt1 + 1; end end always@(negedge cnt1[3] or negedge rst) begin if (!rst) cnt2 <= 8'b0; // Div by 2 to 256 based on sel input else cnt2 <= cnt2 + 1; end always@(negedge cnt1[3] or negedge rst) begin if(!rst) div256 <= 1'b0; Scientech Technologies Pvt. Ltd. 44

45 else begin case (sel) 3'b000 : div256 <= cnt2[0]; //3 8.4 KHz {cnt2[0] div bt 2}*8*13 = 208 3'b001 : div256 <= cnt2[1]; // 19.2 KHz {cnt2[0] div bt 4}*8*13 = 416 3'b010 : div256 <= cnt2[2]; // 9.6 KHz {cnt2[0] div bt 8}*8*13 = 832 3'b011 : div256 <= cnt2[3]; // 4.8 KHz {cnt2[0] div bt 16}*8*13=1664 3'b100 : div256 <= cnt2[4]; // 2.4 KHz {cnt2[0] div bt 32}*8*13 = 'b101 : div256 <= cnt2[5]; // 1.2 KHz {cnt2[0] div bt 64}*8*13 = 'b110 : div256 <= cnt2[6]; // 600 Hz {cnt2[0] div bt 128}*8*13 = default: div256 <= cnt2[7]; // 300 Hz {cnt2[0] div bt 256}*8*13 = endcase end end always@(posedge div256 or negedge rst) begin if (!rst) cnt3 <= 3'b0; // div by 8 else cnt3 <= cnt3 + 1; end always@(posedge clk_out or negedge rst) begin if(!rst) begin counter <= 4'b0; end else begin counter <= counter +1; end end always@(counter) begin case (counter) 4'b0000 : leds <= 16'b ; 4'b0001 : leds <= 16'b ; 4'b0010 : leds <= 16'b ; 4'b0011 : leds <= 16'b ; 4'b0100 : leds <= 16'b ; 4'b0101 : leds <= 16'b ; 4'b0110 : leds <= 16'b ; 4'b0111 : leds <= 16'b ; Scientech Technologies Pvt. Ltd. 45

46 endcase end endmodule 4'b1000 : leds <= 16'b ; 4'b1001 : leds <= 16'b ; 4'b1010 : leds <= 16'b ; 4'b1011 : leds <= 16'b ; 4'b1100 : leds <= 16'b ; 4'b1101 : leds <= 16'b ; 4'b1110 : leds <= 16'b ; 4'b1111 : leds <= 16'b ; default : leds <= 16'b ; User Constraints File (UCF) of LED Flasher for CPLD XC95108PC84- NET rst LOC=P1; # DIP 1 NET sel<2> LOC=P2; # DIP 2 NET sel<1> LOC=P3; # DIP 3 NET sel<0> LOC=P4; # DIP 4 NET clock LOC=P9; # SYSTEM CLOCK NET leds<0> LOC=P14; # LED1 NET leds<1> LOC=P15; # LED2 NET leds<2> LOC=P17; # LED3 NET leds<3> LOC=P18; # LED4 NET leds<4> LOC=P19; # LED5 NET leds<5> LOC=P20; # LED6 NET leds<6> LOC=P21; # LED7 NET leds<7> LOC=P23; # LED8 NET leds<8> LOC=P24; # LED9 NET leds<9> LOC=P25; # LED10 NET leds<10> LOC=P26; # LED11 NET leds<11> LOC=P31; # LED12 NET leds<12> LOC=P57; # LED13 NET leds<13> LOC=P58; # LED14 NET leds<14> LOC=P61; # LED15 NET leds<15> LOC=P62; # LED16 RTL Schematic : Scientech Technologies Pvt. Ltd. 46

47 Sample Code 3 - AND GATE Verilog HDL code module and_gate(a,b,c); input a; input b; output c; wire c; assign c = a & b; endmodule User Constraints File (UCF) of AND GATE for CPLD XC95108PC84- NET a LOC=P1; # DIP1 NET b LOC=P2; # DIP2 NET c LOC=P14; # LED1 RTL Schematic Sample Code 4 - COUNTER_Seven_Segment_display VHDL Code - library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity sevenseg_dis is port(reset: in std_logic; Clk : in std_logic; Segment : out std_logic_vector(6 downto 0); Base1 : out std_logic_vector(3 downto 0) ); end sevenseg_dis; Scientech Technologies Pvt. Ltd. 47

48 architecture sevenseg_dis_arch of sevenseg_dis is signal Counter:std_logic_vector(24 downto 0); signal Decoder:std_logic_vector(1 downto 0); signal Bts:std_logic_vector(3 downto 0); signal Enable:std_logic; begin Decoder <= Counter(14 downto 13) ; Enable <= Counter(12) ; Bts <= Counter(24 downto 21) ; -- Set the ON and OFF Frequency process(clk,reset) begin if (Reset='1')then Counter <= (others =>'0') ; elsif Clk'event and clk = '1' then Counter <=Counter +'1'; end if; end process; process(decoder,enable) begin if (Enable='1')then Base1 <= (others=>'0') ; else case Decoder is when "00" => Base1 <= "0001" ; when "01" => Base1 <= "0010" ; when "10" => Base1 <= "0100" ; when "11" => Base1 <= "1000" ; when others =>Base1 <= "1111" ; end case; end if; end process; process (Bts) begin case Bts is - - Binary to 7-segment when "0000" => Segment <= " " ; --0 when "0001" => Segment <= " " ; --1 when "0010" => Segment <= " " ; --2 when "0011" => Segment <= " " ; --3 when "0100" => Segment <= " " ; --4 when "0101" => Segment <= " " ; --5 when "0110" => Segment <= " " ; --6 when "0111" => Segment <= " " ; Make the Transistors ON and OFF Scientech Technologies Pvt. Ltd. 48

49 when "1000" => Segment <= " " ; --8 when "1001" => Segment <= " " ; --9 when "1010" => Segment <= " " ; --A when "1011" => Segment <= " " ; --B when "1100" => Segment <= " " ; --C when "1101" => Segment <= " " ; --D when "1110" => Segment <= " " ; --E when "1111" => Segment <= " " ; --F when others => Segment <= " " ; --Blank end case; end process; end sevenseg_dis_arch; User Constraints File (UCF) of Counter-seven-segment for CPLD XC95108PC84- NET reset LOC = p1; # DIP1 NET clk LOC = p9; # SYSTEM CLOCK NET segment<0> LOC = p70; # a NET segment<1> LOC = p32; # b NET segment<2> LOC = p33; # c NET segment<3> LOC = p34; # d NET segment<4> LOC = p35; # e NET segment<5> LOC = p36; # f NET segment<6> LOC = p37; # g NET base1<0> LOC = p63; # c1 NET base1<1> LOC = p65; # c2 NET base1<2> LOC = p66; # c3 NET base1<3> LOC = p67; # c4 RTL Schematic : Note : Clk is system clock, Reset is Power ON Reset, base1 used to drive transistors, Segment is seven bit vector applied to Seven segments of LED Display Scientech Technologies Pvt. Ltd. 49

50 Sample Code 5 : DE-MULTIPLEXER Verilog HDL code - module de_mux_1_4(sel,mux_in,mux_out); input [1:0] sel; input mux_in; output [3:0]mux_out; reg [3:0]mux_out; always@(sel or mux_in) begin case (sel) 2'b00 : mux_out[0] <= mux_in; 2'b01 : mux_out[1] <= mux_in; 2'b10 : mux_out[2] <= mux_in; 2'b11 : mux_out[3] <= mux_in; endcase end endmodule User Constraints File (UCF) of DE-MULTIPLEXER for CPLD XC95108PC84 : NET sel<1> LOC=P1; # DIP 1 NET sel<0> LOC=P2; # DIP 2 NET mux_in LOC=P3; # DIP 3 NET mux_out<0> LOC=P14; # LED 1 NET mux_out<1> LOC=P15; # LED 2 NET mux_out<2> LOC=P17; # LED 3 NET mux_out<3> LOC=P18; # LED 4 RTL Schematic Scientech Technologies Pvt. Ltd. 50

51 Sample Code 6 - ENCODER Octal to binary : Verilog HDL Code : module octal_to_binary_encoder(oct_in,bin_out,display,tran_in); input [7:0] oct_in; output [2:0] bin_out; output [6:0]display; output [5:0]tran_in; reg [2:0] bin_out; reg [6:0]display; reg [5:0]tran_in; always@(oct_in) begin case(oct_in) 8'b : begin display <= 7'b ; bin_out <= 3'b000; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b001; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b010; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b011; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b100; tran_in <= 6'b100000; end 8'b : Scientech Technologies Pvt. Ltd. 51

52 begin display <= 7'b ; bin_out <= 3'b101; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b110; tran_in <= 6'b100000; end 8'b : begin display <= 7'b ; bin_out <= 3'b111; tran_in <= 6'b100000; end default : begin display <= 7'b ; bin_out <= 3'b000; tran_in <= 6'b111111; end endcase end endmodule User Constraints File (UCF) of ENCODER for CPLD XC95108PC84- NET oct_in<7> LOC=P1; # DIP 1 NET oct_in<6> LOC=P2; # DIP 2 NET oct_in<5> LOC=P3; # DIP 3 NET oct_in<4> LOC=P4; # DIP 4 NET oct_in<3> LOC=P11; # DIP 5 NET oct_in<2> LOC=P7; # DIP 6 NET oct_in<1> LOC=P6; # DIP 7 NET oct_in<0> LOC=P5; # DIP 8 NET bin_out<0> LOC=P14; # LED1 NET bin_out<1> LOC=P15; # LED2 NET bin_out<2> LOC=P17; # LED3 NET display<0> LOC=P70; # a NET display<1> LOC=P32; # b NET display<2> LOC=P33; # c NET display<3> LOC=P34; # d NET display<4> LOC=P35; # e NET display<5> LOC=P36; # f Scientech Technologies Pvt. Ltd. 52

53 NET display<6> LOC=P37; # g NET tran_in<0> LOC=P63; # c1 NET tran_in<1> LOC=P65; # c2 NET tran_in<2> LOC=P66; # c3 NET tran_in<3> LOC=P67; # c4 NET tran_in<4> LOC=P68; # c5 NET tran_in<5> LOC=P69; # c6 RTL Schematic : Sample Code 7 - Decoder BCD to Seven Segment Verilog HDL Code : module bcd_seven_seg(bcd_in,seven_seg,tran_in); input [3:0] bcd_in; output [5:0]tran_in; output [6:0] seven_seg; reg [6:0] seven_seg; reg [5:0]tran_in; always@(bcd_in) begin case(bcd_in) 4'b0000 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0001 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0010 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0011 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0100 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0101 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0110 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b0111 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1000 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1001 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1010 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1011 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1100 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1101 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end Scientech Technologies Pvt. Ltd. 53

54 4'b1110 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end 4'b1111 : begin seven_seg <= 7'b ;tran_in <= 6'b100000; end endcase end endmodule User Constraints File (UCF) of DECODER for CPLD XC95108PC84 : NET bcd_in<3> LOC=P1; # DIP 1 NET bcd_in<2> LOC=P2; # DIP 2 NET bcd_in<1> LOC=P3; # DIP 2 NET bcd_in<0> LOC=P4; # DIP 2 NET seven_seg<0> LOC=P70; # a NET seven_seg<1> LOC=P32; # b NET seven_seg<2> LOC=P33; # c NET seven_seg<3> LOC=P34; # d NET seven_seg<4> LOC=P35; # e NET seven_seg<5> LOC=P36; # f NET seven_seg<6> LOC=P37; # g NET tran_in<0> LOC = P63; # c1 NET tran_in<1> LOC = P65; #c2 NET tran_in<2> LOC = P66; #c3 NET tran_in<3> LOC = P67; #c4 NET tran_in<4> LOC = P68; #c5 NET tran_in<5> LOC = P69; #c6 RTL Schematic : Scientech Technologies Pvt. Ltd. 54

55 Sample Code 8 - Bank Token Display : Verilog HDL Code : module bank_token(number_in,token_out,tran_in); input [9:0] number_in; output [6:0]token_out; output [5:0]tran_in; reg [6:0]token_out; reg [5:0]tran_in; always@(number_in) begin case(number_in) 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end 10'b : begin token_out <= 7'b ; tran_in <= 6'b111111; end default : begin token_out <= 7'b ; tran_in <= 6'b111111; end endcase end endmodule User Constraints File (UCF) of Bank Token Display for CPLD XC95108PC84- NET number_in<9> LOC=P1; # DIP 1 NET number_in<8> LOC=P2; # DIP 2 NET number_in<7> LOC=P3; # DIP 3 NET number_in<6> LOC=P4; # DIP 4 NET number_in<5> LOC=P11; # DIP 5 NET number_in<4> LOC=P7; # DIP 6 NET number_in<3> LOC=P6; # DIP 7 NET number_in<2> LOC=P5; # DIP 8 NET number_in<1> LOC=P13; # DIP 9 NET number_in<0> LOC=P71; # DIP 10 NET token_out<0> LOC=P70; # a NET token_out<1> LOC=P32; # b NET token_out<2> LOC=P33; # c NET token_out<3> LOC=P34; # d NET token_out<4> LOC=P35; # e NET token_out<5> LOC=P36; # f Scientech Technologies Pvt. Ltd. 55

56 NET token_out<6> LOC=P37; # g NET tran_in<0> LOC = P63; # c1 NET tran_in<1> LOC = P65; # c2 NET tran_in<2> LOC = P66; # c3 NET tran_in<3> LOC = P67; # c4 NET tran_in<4> LOC = P68; # c5 NET tran_in<5> LOC = P69; # c6 RTL Schematic : Scientech Technologies Pvt. Ltd. 56

57 VLSI Design Cycle A typical design flow for designing of VLSI circuits is shown below. 1. Specifications The design cycle starts with the specifications, which describe the functionality, interface and the architecture of the design that has to be designed. Timing diagrams of the interfaces (inputs and outputs) are also specified, which is a part of the specification. 2. Block diagram and waveform analysis Block diagram representation of designs makes easier understanding of design. The top-level block diagram of the design represents interfacing signals as per the specifications. The design is also further split into smaller blocks according to the functionality with the inputs and outputs names of the internal blocks specified. Timing diagram for all the internal blocks are drawn after the internal block division, which is helpful in analyzing and designing the blocks. 3. Behavioral description Describes the basic functionality of the design and its internal blocks, helpful in analyzing the design's verification and implementation issues. Basically it is described through HDL or with software languages like C or C++. Scientech Technologies Pvt. Ltd. 57

58 4. Register Transfer level (RTl) description The divided internal blocks are represented with basic components like registers, multiplexers, decoders etc., in accordance to functionality. Logic reduction of the design and synthesis issues is taken into consideration while doing the RTL description. It is especially helpful in larger and high speed designs. If the target device of the design to be implemented is a PLO, RTl has to be described according to the architecture of the PLO, which makes the design efficient in area and speed wise. 5. Design Entry The representation of the RTL description to CAD/EOA tools is known as design entry. The design entry can be through HDL (Hardware description Language) or schematic or FSM (Finite State Machines). As schematic and FSM entry takes longer time to represent larger designs, HDL entry takes precedence in design entry than the others. HDI description offers the following advantages : a. Easy representation of larger and smaller designs which makes designing process faster. b. Fully technology-independent. c. Easier and faster verification of design. Design Flow : Scientech Technologies Pvt. Ltd. 58

59 6. Functional verification Functional verification is done to check only the functionality of the design. Usually it is done before synthesis so the delays of the gates and interconnects are not taken into consideration. In case of verification failure, the process has to start again from RTL description. Verification of design is done through HDL simulators. 7. Synthesis It is the process of converting a high level description of the design into an optimized gate level representation, given standard cell libraries and design constraints. From the synthesis process the design becomes fully technology dependent, as the standard cell libraries characteristics varies from vendor to vendor. Standard cell libraries have the gate level primitives like AND, OR, NOR, NAND gates. In case of PLDs synthesis process the synthesizer generates netlist file. In case of XILINX, the synthesizer generates Xilinx Net Format (XNF) file that uses Xilinx primitives. 8. Logical verification Logical verification is done with unit delay gates and interconnects, usually done after synthesis. 9. Implementation The process of implementing the design for a specific target device is known as Implementation. The Implementation flow is device or vendor specific. In case of Xilinx, the flow engine runs following steps for implementation. a. Translation : At this process, the flow engine merges all the netlist inputs generated during synthesis and the whole design is translated according to the device architecture. b. Map (FPGA only) : The flow engine maps the translated design into the components in the Xilinx FPGA. c. Place and Route (FPGA only) : The flow engine places and routes the mapped design at this process. d. Fit (CPLD only) : The Flow engine launches the CPLD fitter to minimize and collapse the design's combinatorial logic, to make the design to fit into the available resources of the device. Fitting is done after translation. Scientech Technologies Pvt. Ltd. 59