GBT-SCA Slow Control Adapter ASIC. LHCb Upgrade Electronics meeting 12 June 2014

Transcription

1 GBT-SCA Slow Control Adapter ASIC LHCb Upgrade Electronics meeting 12 June 2014

2 Design Team Core Digital Logic: Christian Paillard, Alessandro Caratelli e-port interface: ADC: DAC: Sandro Bonacini icsparkling IP block Xavier Llopart (Medipix IP block) Chip Assembly: Christian Palliard, Rui F. Oliveira AOB: Kostas Kloukinas, Paolo Moreira 12 June 14 2

3 SCA in the GBT system 12 June 14 3

4 The GBT System Embedded Electronics Control Room Optical Link A Single Link for: Readout (DAQ) High speed unidirectional (up-link) Trigger data (up-link) Timing Trigger and Control (TTC) Clock reference and synchronous control (down-link) Custom ASICs in the detectors: Radiation Tolerant: Total dose & Single Event Upsets Commercial components in the control room FPGAs used to implement multi-way transceivers Trigger decisions and control (down-link) Low and fixed latency Experiment control (SC/DCS/ECS) Modest bandwidth (bidirectional link) 12 June 14 Alessandro.Caratelli@cern.ch 4

5 GBT-SCA front-end interconnects ASIC dedicated to slow control functions. System Upgrades for SLHC detectors. Replacement for the CCU & DCU ASICs CCU: Communication Control Unit FE ASICs e-port e-port Data Timing e-port e-port e-port GBTX GBT on FPGA Slow Control DAQ Timing and Trigger DCU: Detector Control Unit in CMS). e-port e-port Flexible to match the needs of different Front-End systems. User busses and I/O for Control and monitoring e-port Technology: CMOS 130nm using radiation tolerant techniques. e-port GBT-SCA Embedded electronics Control room 12 June 14 5

6 The Slow Control Adapter ASIC Dual redundant e-ports for GBTX e-links. Network Controller Arbiter 16 I 2 C masters (7bit/10bit addressing) 1 JTAG master controller 1 SPI master (with 8 slave select) 32 General purpose digital I/O lines individually programmable as input / output / interrupt input 31 Analog inputs multiplexed in a 1 bit single slope integrative ADC 4 independent analog output (8 bits resolution) Auxiliary I2C port for testability I2C Master x 16 SPI Master JTAG Master General purpose I/O Interrupts ADC Calibration Logic Temperature control DAC x 4 E-FUSES ADC Interface DAC Interface Network Controller Single event upset counter RX FIFO TX FIFO RX FIFO TX FIFO Arbiter Config E- PORT E- PORT (Auxiliary) Config Auxiliary I2C Port Clock and reset control logic RX TX RX TX SERDES SERDES clock RX TX clock RX TX Figure 1. The SCA top level block diagram 12 June 14 Alessandro.Caratelli@cern.ch 6

7 Communication architecture 12 June 14 7

8 Communication Architecture The Three Communication Layers of the SCA: GBT-link Layer Connects the GBT ASIC to the Control Room electronics via a point-to-point, bidirectional, 4.8Gbps, optical link using a special, SEU robust, transport protocol. The transport protocol is totally transparent to the user data. e-link Layer Connects to the SCA ASIC via a point-to-point, bi-directional, 80Mbps link, using a packet oriented transport protocol (HDLC protocol). Data packets are encapsulated by the GBT-link protocol. Channel Layer Connects to the Front-End ASICs via bi-directional links. SCA on-chip peripherals are also Channel Blocks. Channel Blocks are controlled via a command driven protocol. The Channel Protocol Commands are encapsulated by the e-link protocol. 12 June 14 Alessandro.Caratelli@cern.ch 8

9 GBT-link Packet Format Fixed packet length: 120bits Packet transmission rate: 1/25ns Data transmission rate: 4.8 Gbps Fixed bandwidth allocation: Trigger path: 640 Mbps Control path: 160 Mbps 1 internal e-link (for GBT management) 1 external e-link (for GBT-SCA chip) 40 MHz DDR (80 Mbps) Data path: 2.56 Gbps Mbps Mbps Mbps 4 bits 2 bits 2 bits 80 bits 32 bits H IC EC EC FEC Data flow: Symmetrical, Bi-directional data transmission. Transmission of GBT-packets is continuous. Data from e-link ports are muxed/demuxed in the GBT-link stream. GBT data path is unaware of the e-link transfer protocol. 12 June 14 Alessandro.Caratelli@cern.ch 9

10 HDLC Packet Format 6 bits 8 bits 8 bits 16 n bits 16 bits 6 bits HDLC packet structure: SOF Address Control DATA FCS EOF HDLC Packet: SOF/EOF: Frame delimiter character. Address: Packet destination address. Control: Indicates the type of the data packet. FCS: Frame Check Sequence for transmission error detection. (G(x) = x 16 + x 12 + x 5 + 1) Uses bit-stuffing techniques in order to achieve symbol synchronization. The frame delimiter contains 6 consecutive ones; Any sequence of 5 ones in the stream is stuffed with one following zero at the transmitter side Any sequence of more than 6 ones is considered to be frame abort or channel idle signalling Bi-directional operation. Each received command packet get acknowledged or rejected by the SCA 12 June 14 Alessandro.Caratelli@cern.ch 10

11 SCA Packet Formats 6 bits 8 bits 8 bits 16 n bits 16 bits 6 bits HDLC packet : SOF Address Control DATA FCS EOF SCA up-link packet structure: SCA down-link packet structure: TR# CH# CMD LEN Data TR# CH# ERR LEN Data 8 bits 8 bits 8 bits 8 bits 16 n bits SCA Packet: CH#: Specifies the SCA Channel interface to be addressed TR#: Incremental identification number for each transmitted command. CMD: Is a command code that specifies the request. The operation can refer to a specific internal register of the channel or a front-end ASIC destination address. In this case an address field follows the command. ERR: In case of an error has encountered, return an error otherwise returns 0x00. LEN: Is a field that specifies the DATA field length. DATA: Is an optional variable length field upon LEN value. 12 June 14 Alessandro.Caratelli@cern.ch 11

12 Channel Commands At the reception of any request packet, the SCA replies with an acknowledge packet The acknowledge packet include information of the status of the operation and eventually the data value required. Each command can be directed to a specific channel interface. Upon reception of a command, the channel performs the required operation on its interface. The command field and the data content of a given packet is interpreted differently according to the channel to which it is addressed. Each channel type has a specific set of valid commands. Channels receiving an invalid command do not execute any action and the error condition is reported to the user. Enable/Disable command for each channel When not enabled, the interface core is kept in Power Down Mode to reduce power consumption. At the enable, the channel interface get reset. 12 June 14 Alessandro.Caratelli@cern.ch 12

13 Implementation 12 June 14 13

14 e-link & e-port Block Diagram e-port e-link RX FIFO RX control RXCLK SCA Network Controller ATLANTIC Bus TX FIFO TX control PHY RXDATA TXDATA Clk 40 MHz RESET e-port implementation for the GBT-SCA e-link interface: electrical, bi-directional chip-to-chip interconnect at 80Mbps. HDLC (High Level Data Link Control) packet oriented communication protocol. Special commands: CONNECT, RESET, TEST (loopback) Acknowledge transactions using the HDLC protocol mechanism (packet numbering). 12 June 14 14

15 Dual Redundant e-ports The GBT-SCA is equipped with a Primary and a Secondary e-port to be connected with two adjacent GBTX chips for redundancy Only one e-port is needed for operation and can be active at a time Data from the inactive e-port is discarded Switching between ports is command driven. (HDLC CONNECT command) Clock activity or noise on the differential input of the inactive link is discarded Upon start up, the user application software should send a CONNECT command to activate the Primary e-port from the Primary e-link. To switch to the Secondary e-port a CONNECT command should be send through the Secondary e-link. Figure 2. GBT-SCA to GBTX connectivity Figure 3. Logical view of HDLC e-ports 14/05/2014 GBT-SCA Design review 15

16 Physical Layer (electrical) SLVS (Scalable Low Voltage Standard) JEDEC standard: JESD8-13 Differential voltage based signaling protocol. Voltage levels compatible with deep submicron processes. Low Power, Low EMI Line impedance: 100 Ohm Differential mode: 400 mv Common mode: 0.2V V 0.2V 200mV 200mV 12 June 14 Alessandro.Caratelli@cern.ch 16

17 Auxiliary I2C port Auxiliary I2C port for testability Allows direct access to Network Controller by-passing the e-ports. Receive SCA commands and returns replies Hardwired Test Enable pin Possibility to use as an expansion port 14/05/2014 GBT-SCA Design review 17

18 wishbone interface comm. control The SPI channel Synchronous bit oriented serial link. Full duplex synchronous serial data transfer Configurable single transaction length up to 128 bits RW Configurable communication speed from 156KHz to 20MHz settable with 128 possible values Asynchronous reset signal with configurable pulse length Acknowledge packet to report the end of the communication Supported working modes: (0,0) (0,1) (1,0) (1,1). Possibility to invert the logical level of the output signals during the inactivity time. K MOSI MISO /SS <7:0 Config. registers Figure 5. The SPI channel scheme 14/05/2014 GBT-SCA Design review 18

19 reset wishbone interface comm. control The JTAG channel 128 bit shift registers to hold the TDO/TDI and TMS bit-streams Protocol implemented in software Configurable single transaction length up to 128 bits RW Configurable communication speed from 156KHz to 20MHz settable with 128 possible values Asynchronous reset signal with configurable pulse length Acknowledge packet to report the end of the communication Possibility to invert the TCK edge synchronously to which the transmitted bits on the TDO and TMS lines are latched Possibility to invert the TCK edge synchronously to which the received bits on the TDI line are evaluated. Possibility to invert the logical level of the output signals during the inactivity time. TCK TMS TDO TDI ARST Config. registers Figure 6. The JTAG channel scheme 14/05/2014 GBT-SCA Design review 19

20 wishbone interface The I 2 C channels 16 independent I 2 C master channels Concurrent operation of all 16 channels Support is limited to single bus master topologies. 7-bit and 10-bit addressing modes. Single-byte and Multi-byte transfer modes. Read-Modify-Write mode that allows for AND, OR, XOR logic operations with a Mask register. Programmable transfer rate from 100Kbps to 1Mbps. Power Down mode per channel I2C protocol state machine Command buffer Config. registers Figure 4. I2C channel block diagram 14/05/2014 GBT-SCA Design review 20

21 wishbone interface The GPIO channel 32 general-purpose I/O signals. All general-purpose I/O signals are bidirectional having individually programmable direction. All general-purpose I/O signals can be three-stated. General-purpose I/O signals programmed as inputs can cause interrupt requests. General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock. Alternative input reference clock signal from external interface. Power Down mode Int. clk Interrupt controller General purpose I/O (x32) Ext. clk Figure 7 - The GPIO channel 14/05/2014 GBT-SCA Design review 21

22 wishbone interface The DAC channel 4 independent Digital to analog converters. The single DAC is an IP Block from MEDIPIX team 8 DAC 1 Analog output 1 Voltage output: 0.0V 1.0V 8 bit resolution 8 DAC 2 Analog output 2 8 DAC 3 Analog output 3 8 DAC 4 Analog output 4 Figure 8 The DAC channel 14/05/2014 GBT-SCA Design review 22

23 ADC channel 12-bit ADC (LSB = 244 µv) Single -slope architecture Input range: GND < Vin < 1 V Single supply voltage: VDD = 1.5 V System clock frequency: 40 MHz Max. conversion rate 3.5 KHz Max conversion time 600 μsec Operating temperature: -30 C to +80 C 32 Multiplexed Input channels 1 channel occupied by an on chip Temp sensor All channels feature a switchable 10 μα current source to support Pt sensors. Power consumption 1.2V (420uW analog part ) Power Down mode Automatic Offset cancelation & Gain correction Pre-calibration at production testing phase ANALOG E-fuses bank E-fuses bank E-fuses bank E-fuses bank E-fuses bank E-fuses read logic DIGITAL ADC Control logic Calibration logic Supervising logic + Wishbone interface Figure 9. The ADC channel scheme 14/05/2014 GBT-SCA Design review 23

24 Layout E-Fuses DAC ADC calib. logic Prompt ADC analog JTAG channel SPI channel Network controller E-Link I2C channels GPIO channel 3.6 x 3.6 mm 12 June 14 Alessandro.Caratelli@cern.ch 24

25 Packaging (draft) Package Type: LFBGA Low Profile Fine Pitch BGA (Chip Scale Package) Ball Pitch: 0.8 mm Size: 12 x 12 mm Height: mm Pin count: 196 Preliminary pinout Manufacturers: ASE via IMEC NOVAPACK N M L K J I H G F E D <0> <1> RESET_B _ rx_sd link_clk tx_sd rx_sd _aux link_clk _aux tx_sd _aux link_aux _disable _ auxport TestEn _ <2> <1> Fuse Program Pulse _ <5> <4> <3> <8> <7> <6> <11> <10> <9> <14> <13> <12> <17> <16> <15> <20> <19> <18> <23> <22> <21> <26> <25> <24> Pad_ resout DAC_ou t_ <28> <27> Rx_sd pwr3 n 3 AGND AGND AGND AGND AVDD AVDD AVDD AVDD link_clk_ n tx_sd _n Rx_sd aux_n link_clk _aux_n tx_sd aux_n SPI_ miso _ SPI_ mosi _ SPI_ss _ <0> SPI_ss _ <1> SPI_ss _ <2> SPI_ss _ <3> SPI_ss _ <4> SPI_ss _ <5> SPI_ss _ <6> AGND AGND AGND AGND AVDD AVDD AVDD AVDD DVSS DVSS AGND AGND AVDD AVDD DVDD DVSS DVSS DVSS DVSS DVDD DVDD DVDD DVSS DVSS DVSS DVSS DVDD DVDD DVDD GND GND GND GND VDD VDD VDD GND GND GND GND VDD VDD VDD GND GND GND GND VDD VDD VDD _ <13> _ <13> _ <9> _ <9> _ <5> _ <5> DAC_ou t_ <2> DAC_ou t_ <0> <29> _ <14> _ <14> _ <12> _ <12> _ <8> _ <8> _ <4> _ <4> DAC_ou t_ <3> DAC_ou t_ <1> <30> _ <15> _ <15> _ <11> _ <1> _ <7> _ <7> _ <3> _ <3> JTAG_ reset _ TDO _ TDI _ TCK _ TMS <10> _ <10> _ <6> _ <6> _ <2> _ <2> N M L K J I H G F E D C auxport _ SPI_ clk _ SPI_ss _ <7> <4> <7> <10> <13> <16> <19> <22> <25> <28> _ <1> _ <0> C B auxport _ <0> <2> <5> <8> <11> <14> <17> <20> <23> <26> <29> _ <1> _ <0> B A _ EXTCLK <1> <3> <6> <9> <12> <15> <18> <21> <24> <27> <30> <31> A TOP WIEW 12 June 14 Alessandro.Caratelli@cern.ch 25

26 Final Verifications Functional simulation at the top level Post Layout simulations Simulation with SEU injection Ultrasim Mixed-Signal simulations SCA emulation on FPGA Protocol tests with commercial devices 12 June 14 26

27 SCA packet gener. FPGA test bench 1/2 Software FPGA test firmware Low level func. to handle GBT- SCA communication Low level func. to handle slaves Drivers + USB bluster + interface etc. USB control logic Transf. control flags SCA send packet SCA rec packet I2C0 data Comm. control Comm. control E-Port Master E-Port Master SCA logic Testing software: Start random transaction on random channels Whait with time-out replies from the SCA logic Compare data received on slave interfaces with the expected behaviour respect sent requests Write operation log and error log Test passed when no errors are encountered I2Cn data GPIO data SPI data JTAG data Slaves Configure Test System config. I2C Slave x4 I2C Slave x4 I2C I2C Slave Slave x4 x4 Parallel I/O ctrl SPI Slave Multimode JTAG slave 14/05/2014 GBT-SCA Design review 27

28 SCA packet gener. JTAG test with commercial hardware Software FPGA test firmware Low level func. to handle GBT- SCA communication Low level func. to handle slaves Drivers + USB bluster + interface etc. USB control logic Transf. control flags SCA send packet SCA rec packet I2C0 data Comm. control Comm. control E-Port Master E-Port Master SCA logic Program en external commercial FPGA through the GBT-SCA emulated on an other FPGA: Read FPGA configuration file (ISE output file containing series of directives for JTAG interface to program the target Xilinx FPGA) Find the target FPGA in the JTAG chain Generate corresponding commands in SCA format Send the commands to the GBT-SCA emulated in the main FPGA Write error log of unsuccessful operations I2Cn data GPIO data SPI data JTAG data Slaves Configure Test System config. I2C Slave x4 I2C Slave x4 I2C Slave x4 Parallel I/O ctrl SPI Slave Multimode I2C interface SPI interface JTAG interface 14/05/2014 GBT-SCA Design review 28

29 FPGA test bench 2/2 FPGA test firmware Nios II Processor Handle shell interface E-port drivers Slaves drivers Handle communication with SCA Real-time verification of concurrent operations performed by the SCA Report Operation information and identified errors Comm. control Comm. control E-Port Master E-Port Master I2C Slave x4 I2C Slave x4 I2C I2C Slave Slave x4 x4 SCA logic Drivers and USB bluster Command line interface JTAG port Timer banks SDRAM controller PLL Parallel I/O ctrl SPI Slave Multimode JTAG slave 12 June 14 29

30 Specifications Documentation: Users Manual document (draft) Table of commands 12 June 14 30

31 Status & Planning Design Readiness review on 14/5/2014 Suggestions for design verifications Minor design modifications (suppression of external biasing resistor) Design Status Ready for submission Participate on the GBT-chipset engineering run scheduled for this month (June 2014) Estimated TAT: 4-5 months Yield a few hundred SCA chips Test Bench Preparation 12 June 14 Alessandro.Caratelli@cern.ch 31

32 Thank you 12 June 14 32