Beyond Moore. Beyond Programmable Logic.

Transcription

1 Beyond Moore Beyond Programmable Logic Steve Trimberger Xilinx Research FPL 30 August 2012

2 Beyond Moore Beyond Programmable Logic

3 Agenda What is happening in semiconductor technology? Moore s Law More than Moore Less than Moore? What is happening at Xilinx? How Xilinx is dealing with the latest in semiconductor technology Technology and product trends The latest round of devices and technologies It is not just logic anymore What will happen next? Page 3

4 Part 1 Is Moore s Law Ending? Page 4

5 Miles (thousands) Miles (x1000) Part 1 Is Moore s Law Ending? Railroad Track Goetz, Transvision 8/2004 Page 5

6 Nothing New: Power Challenge Multi-Core Source: Intel Page 6

7 Nothing New: I/O Bandwidth Gap Multi-Gigabit Transceivers Source: Xilinx, Inc Page 7

8 Nothing New: Productivity Gap Team Design IP Re-Use ESL Design Flow SoC Platforms The main message in 2011 remains Cost (of design) is the greatest threat to continuation of the semiconductor roadmap ITRS 2011 Source: SEMATECH Page 8

9 Moore s Law: The Technology Pipeline Page 9

10 Industry Debates Variability and Reliability Page 10

11 Industry Debates Cost Page 11

12 Moore s Law Today We still get more transistors! Must trade performance for power savings Dennard scaling ended around 2000 Slow growth of I/O pins I/O bandwidth requirements drive high-speed serial Less area improvement with each new node Lithography limitations restrict layout Quantized transistor sizes with FinFETs Process complexity and limited suppliers drive up wafer pricing and delay production price reductions We still get more transistors! Page 12

13 Part 2 What Is Xilinx Doing? Page 13

14 Expanding Programmable Technology Leadership Committed to be First to Process Nodes Pioneering 3-D IC Technology Leading Edge Processing Systems Programmable Analog/Mixed Signal System to IC Tools, IP, and Ecosystem From Programmable Logic to Programmable Systems Integration Page 14

15 FPGA Capacity Trend Looking Up Largest Xilinx FPGA Page 15

16 FPGA Performance Trend Looking Up Page 16

17 µw/op = (W / LC MHz) FPGA Energy Trend Looking Up Page 17

18 High-k Metal Gate Transistor in 28nm HPL Process HKMG: - introduced by Intel at 45nm - available at 28nm from top foundries > 25x lower gate oxide leakage > 30% lower switching power > 30% higher drive current or > 5x lower source-drain leakage Source: Challenges and Innovations in Nano-CMOS Transistor Scaling, Tahir Ghani, Intel, Oct 2009 Page 18

19 Virtex-5 Artix-7 Kintex-7 Virtex-6 Virtex-7 Ground Breaking Capacity Gains at 28nm World s First 2 Million Logic Cell FPGA Logic Cells 2,000K Over 2x capacity increase over Spartan-6 and Virtex-6 FPGAs Family Capacity Range 8K 350K LCs 70K 480K LCs 330K 2M LCs 1,000K Dramatic Capacity Increases 800K 760K 8K 2M LCs; the widest capacity range offered in a single unified product family Larger densities enable higher performance More calculations/clock cycle by utilizing parallelism inherent in FPGAs Page K 400K 200K 480K 332K 350K Spartan-6 150K 65nm 40/45nm 28nm

20 SSI Technology Harnesses Proven Technology in a Unique Way 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice Microbumps Silicon Interposer Package Substrate Through-Silicon Vias C4 Bumps BGA Balls Through-silicon Side-by-Side Microbumps Passive Silicon Die Interposer Vias Layout (TSV) (65nm Generation) Bridge Minimal Access power to heat power flux / ground / issues ground / IOs / IOs to C4 bumps Minimal Access 4 conventional to design logic metal tool regions flow layers impact connect Coarse Leverages micro bumps pitch, ubiquitous low & TSVs density image aids sensor manufacturability micro-bump No transistors technology means low risk and no Etch TSV induced process performance (not laser drilled) degradation Page 20

21 BW / Watt Cost 25D: Crossing the Chasm 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice 28nm FPGA Slice Package Substrate Very high bandwidth, low capacitance interconnections Known Good Die packaged Large die yield opportunity 100x Stacked Silicon Interconnect 10x SerDes & Standard I/O 1x 10x 100x 1,000x Total Die-to-Die Connections Capacity

22 Virtex 2000T: Homogeneous 3D 4-layer metal Si interposer with TSV 4 FPGA sub-die in package >10,000 inter-die connections 2 Million Logic Cells 68 Billion Transistors Page 22

23 Virtex-7 HT: Heterogeneous 3D Top View Cross Section TSVs 28G SerDes 28G FPGA FPGA FPGA 28G Fabric Interface 13G FPGA 13G Passive Interposer 13G FPGA 13G Yield optimized Noise isolation 13G FPGA 13G 28G transceiver process optimized for performance 28G SerDes Passive Interposer FPGA logic process optimized for power 28Tb/s ~3X Monolithic 16 x 28G Transceivers 72 x 13G Transceivers 650 GPIO

24 3D: The Next Frontier What is inside? How high can we go? What is on top? High performance chip on on top for thermal and TSV process availability Bottom die supports power TSV s for top die (Swiss cheese) in older technology (TSV friendly) Floor-planning critical: Top die Bottom die Package substrate Thermal concerns (stacked thermal flux) Package lid TSV keep out zones in bottom die to avoid stressinduced performance impact Microbumps TSVs C4 balls BGA package balls TSV-Induced Device Stress What about user-defined stacks?

25 Cost Beyond Moore with SSIT Break the exponential cost of large die Break through pin limitations for higher bandwidth and lower power No more compromises for high-performance vs low power for very high-speed I/O Capacity Source: ITRS Page 25

26 Nothing New: Productivity Gap Source: SEMATECH Page 26

27 Hardware and Software Programmability Page 27

28 Xilinx Technology Evolution 3DIC SoC FPGA Programmable Logic Devices Enables Programmable Logic ALL Programmable Devices Enables Programmable Systems Integration Page 28

29 The Zynq Processor+FPGA SoC Complete ARM -based Processing System Dual ARM Cortex -A9 MPCore, up to 1GHz Supports multiple operating systems Fully autonomous to the programmable logic Processing System Memory Interfaces 7 Series Programmable Logic Tightly Integrated Programmable Logic Used to extend processing system High performance AXI based interface Common Peripherals ARM Dual Cortex-A9 MPCore System Common Peripherals Custom Peripherals Scalable density and performance: 30K-350K LCs Common Accelerators Custom Accelerators Flexible Array of I/O Wide range of external multi-standard I/O High performance integrated serial transceivers Analog-to-Digital converter inputs Software & Hardware Programmable Page 29

30 Embedded Design Flow Using Zynq-7000 Industry-Leading Tools Xilinx SDK ARM Ecosystem Many Sources of SW IP Standardized around AMBA-AXI Xilinx, ARM libraries 3rd Parties Software Developer Programming Integrate IP System Architect Custom IP Xilinx IP Hardware Designer Design Integrate IP Industry-Leading Tools C-Gates / AutoESL System Generator VHDL/Verilog Many Sources of HW IP Standardized around AXI 3rd Parties Partner IP Test Test Debug Debug Page 30

31 Virtex-5 Zynq Artix-7 Kintex-7 Virtex-6 Virtex-7 Ground Breaking Capacity Gains at 28nm World s First 2 Million Logic Cell FPGA Logic Cells 2,000K Over 2x capacity increase over Spartan-6 and Virtex-6 FPGAs Family Capacity Range 8K 350K LCs 70K 480K LCs 330K 2M LCs 1,000K Dramatic Capacity Increases 800K 760K 8K 2M LCs; the widest capacity range offered in a single unified product family Larger densities enable higher performance More calculations/clock cycle by utilizing parallelism inherent in FPGAs Page K 400K 200K 480K 332K 350K Spartan-6 150K 65nm 40/45nm 28nm

32 Agile Mixed-Signal Integration Flexible general purpose analog interface Integrated with all 7 series FPGAs and Zynq Supports broad range of applications From simple monitoring to complex signal processing Embedded temperature and supply sensors Enhance reliability, security and safety Page 32

33 Build better systems with fewer chips faster Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Page 33

34 Total Power Power (W) Power Total Power Reduction Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity 50% FPGA Power Savings 50-70% System-Level Power Savings 5 Key FPGA Power Innovations 16 Zynq Enabled Low Power Optimized & Simpler HPL Re-architected Transceivers Multi-mode I/O Control Intelligent Clock Gating Voltage Scaling/Power Binning FPGA DSP Processor Multi-chip Zynq High Density Zynq Zynq Low Density Zynq Transceiver Power 80 SSIT Enabled Low Power I/O Power Dynamic Power 60% 30% 25% Backplane FPGA Line FPGA Max Static Power 65% 20 0 Client FPGA Client FPGA Multi-chip Virtex Virtex-7 Page 34

35 Programmable Components Systems Logic Microprocessors I/O Analog/Mixed Signal It is ALL PROGRAMMABLE Page 35

36 Enabling the Next Decade of ALL PROGRAMMABLE Devices Accelerating Integration up to 4X IP & System-centric integration with fast verification Vivado next generation design system 1X RTL to Bit-stream with iterative approach Fast, hierarchical and deterministic closure automation w/ ECO Accelerating Implementation 1X up to 4X Page 36

37 Maximizing Design Reuse Scalable IP Across Families Plug and Play IP Targeted Design Platforms Vivado Design Environment High-Level Synthesis Xilinx Best-in-class Support Architecture Enabled IP Portability Leveraging Standards for IP Reuse AXI4 (data) AXI Interconnect Block AXI4 AXI DDR3 Mem Ctrl Processor AXI4 Lite DMA AXI4 Streaming TEMAC AXI4 AXI Interconnect Block AXI4 Lite AXI4 Lite AXI4 Lite Timer IntCtrl Flash Int Dramatically Reduce Time to Access, Reuse & Integrate World Class IP Page 37

38 Vivado: More Turns per Day, Ease-of-Use and Reuse Scalable IP Across Families Plug and Play IP Targeted Design Platforms Vivado Design Environment High-Level Synthesis Xilinx Best-in-class Support Vivado RTL->Bits Vivado Design Environment Vivado Run Time ISE Vivado Design Size Next Gen Architecture for Run-time, Memory Utilization & QoR Unified, streamlined, built for reuse U/I based on PlanAhead Simplified use models tailored to different user profiles Industry standard formats Hierarchical flows Easy IP packaging and reuse Page 38

39 More Turns per Day with High-Level Synthesis Scalable IP Across Families Plug and Play IP Targeted Design Platforms Vivado Design Environment High-Level Synthesis Xilinx Best-in-class Support 2-5X Step Function in Design Productivity vs RTL C-based High-Level Synthesis Time spent achieving design Functional correctness Time spent verifying Implementation tools did Not insert errors RTL RTL RTL AutoESL C RTL Functional Verification Tools Validation Optical flow video example Input C Simulation Time RTL Simulation Time Improvement 10 frames of video data 10 seconds ~2 days* ~12,000X *RTL Simulations performed using ModelSim Page 39

40 Recent Innovation and Investment Timeline PlanAhead, SIRF SSIT AMS, AccelChip 28nm HPL Rodin, Targeted Design Platforms, FMC EPP, AXI, Plug & Play IP, PowerLite AutoESL Omiino, Modelware, Sarance Projects Began Investments Enable Innovation and Deliver Value 7-Series Vivado Zynq-7000 Stacked Silicon Interconnect Agile Mixed Signal C/C++ High Level Synthesis Projects Delivered MatLab/Simulink, LabView IP-based Design PlanAhead with ISE Flow ISE Improvements TDPs Page 40

41 Xilinx Technology Evolution 3DIC SoC FPGA Programmable Logic Devices Enables Programmable Logic ALL Programmable Devices Enables Programmable Systems Integration Page 41

42 The Road Ahead Programmable logic is not only about programmable logic We are still gaining tremendous benefit from scaling And we have additional technologies we can use Page We are still looking up

43 What Xilinx Makes Possible: ALL PROGRAMMABLE ALL Programmable Electronic Systems ALL Programmable Technologies ALL Programmable Devices Page 43