Content Addressable Memory (1A) Young Won Lim 6/1/16
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1 Content Addressable Memory (1A)
2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice.
3 Address is used as an index to a data array k-bit Address Read Write Input n-bit Data Memory Unit 2 k words n-bit per word Output n-bit Data index 2 4 words k-bit Address n-bit data
4 MM Address Decoder n-bit data k-bit Address Address Decoder en.wikipedia.org 4
5 Cache : Storing a partial copy of MM Main Memory MM Address data (MM Address, Data) pair
6 : two components MM Address Data Cache Memory Tag Cache Directory Data Cache Array 6
7 Accessing : Address Matching MM Address Data from CPU Address Hit to / from CPU Match Cache Memory Tag Memory Cache Directory Data Cache Array 7
8 CAM (Content Addressable Memory) Interface DIN[M:] WR_ADDR[logN:] DATA_MASK[M:] CMP_DIN[M:] CMP_DATA_MASK[M:] CLK EN WE MATCH_ADDR[J:] MULTIPLE_MATCH SINGLE_MATCH BUSY READ_WARNING Xilinx CAM xapp1151_param_cam.pdf 8
9 CAM Read Operation Search a key Search Data DIN[M:] MATCH_ADDR[J:] MULTIPLE_MATCH SINGLE_MATCH CAM Address CLK EN WE CAM Address Search Data match? Search Data xapp1151_param_cam.pdf 9
10 Write Operation Write Data CAM Address DIN[M:] WR_ADDR[logN:] 1 CLK EN WE CAM Address Search Data write xapp1151_param_cam.pdf 1
11 Simultaneous Write Data CAM Address Search Data DIN[M:] WR_ADDR[logN:] DATA_MASK[M:] CMP_DIN[M:] CMP_DATA_MASK[M:] MATCH_ADDR[J:] MULTIPLE_MATCH SINGLE_MATCH CAM Address 1 CLK EN WE BUSY READ_WARNING EN=1 simultaneous write/read Simultaneous Read/Write Simultaneous write and search operations With an to warn the user of possible collision Read warning flag: The data applied to the CAM for a read Matches the data that is currently being written into the CAM By unfinished write operation xapp1151_param_cam.pdf 11
12 Ternary Mode Cache Address DIN[M:] WR_ADDR[logN:] DATA_MASK[M:] CMP_DIN[M:] CMP_DATA_MASK[M:] MATCH_ADDR[J:] MULTIPLE_MATCH SINGLE_MATCH 1 CLK EN WE BUSY READ_WARNING EN=1 simultaneous write/read DIN[M:] Data in Bus The data to be written into The data read from the CAM Simultaneous read/write mode CMP_DIN for the read operation Standard Ternary mode DIN DATA_MASK X 1 1 X CMP_DIN[M:] Compare Data In Bus Simultaneous read/write The data read from the CAM Ternary mode One of the two buses To determine the bit value During read operation xapp1151_param_cam.pdf 12
13 SRAM Cell bit bit_b word CMOS VLSI Design 4 th ed, Weste 13
14 SRAM Bit Cell RTL Model S Q R = 1 READ op = WRITE op en.wikipedia.org 14
15 SRAM Bit Cell Read & Write Operations S Q 1 Input x x S Q R xb R 1 = 1 READ op = WRITE op HOLD S= Q=old Q Input x=1 SET S=1 Q=1 R= Q=old Q R= Q= Input x= RESET S= Q= en.wikipedia.org R=1 Q=1 15
16 1T CAM Cell bit bit_b word match CMOS VLSI Design 4 th ed, Weste 16
17 SRAM Bit Cell RTL Model match 17
18 CAM Bit Cell RTL Model ' match S Q read / write R match = 1 READ op = WRITE op 18
19 CAM Bit Cell RTL Model Operations S Q x S Q R match_out xb R match_out 1 = 1 READ op = WRITE op HOLD S= Q=old Q Input x=1 SET S=1 Q=1 R= Q=old Q R= Q= Input x= RESET S= Q= R=1 Q=1 19
20 2x2 CAM Bit Cell RTL Model Ain1 Ain CAM Address match match match match r/w 2
21 Diagram for a with 2 lines 4-bit word A1 A D3 D2 D1 D match match match match r/w R/W O3 O2 O1 O Main Memory MM Address 1 11 data 8 AB AB 21
22 CAM (Content Addressable Memory) 22
23 CAM (Content Addressable Memory) 23
24 CAM (Content Addressable Memory) 24
25 SRAM Bit Cell RTL Model match_in out match_out 25
26 CAM Bit Cell RTL Model match_in S Q R match_out = 1 READ op = WRITE op ' match_in match_out read / write 26
27 CAM Bit Cell RTL Model Operations match_in match_in S Q x S Q R match_out 1 = 1 READ op xb R = WRITE op match_out HOLD S= Q=old Q Input x=1 SET S=1 Q=1 R= Q=old Q R= Q= Input x= RESET S= Q= R=1 Q=1 27
28 2x2 CAM Bit Cell RTL Model Ain1 Ain match_in out match_in out match_out match_out match_in out match_in out match_out match_out r/w Aout1 Aout 28
29 References [1] [2] [3] [4] [5] [6] [7] [8] Digital Systems, Hill, Peterson, 1987
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