Cache Memory. Young Won Lim 5/31/16

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2 Copyright (c) Young W. Lim. Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.2 or any later version published by the Free Software Foundation; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the section entitled "GNU Free Documentation License". Please send corrections (or suggestions) to youngwlim@hotmail.com. This document was produced by using OpenOffice.

3 Address is used as an index to a data array k-bit Address Read Write Input n-bit Data Memory Unit 2 k words n-bit per word Output n-bit Data index 2 4 words k-bit Address n-bit data Memory 3

4 MM Address Decoder n-bit data k-bit Address Address Decoder en.wikipedia.org Memory 4

5 Cache : Storing a partial copy of MM Main Memory MM Address data (MM Address, Data) pair Memory 5

6 : two components MM Address Data Cache Memory Tag Cache Directory Data Cache Array Memory 6

7 Accessing : Address Matching MM Address Data from CPU Address Hit to / from CPU Match Cache Memory Tag Memory Cache Directory Data Cache Array Memory 7

8 CAM (Content Addressable Memory) Interface DIN[M:0] WR_ADDR[logN:0] DATA_MASK[M:0] CMP_DIN[M:0] CMP_DATA_MASK[M:0] CLK EN WE MATCH_ADDR[J:0] MULTIPLE_MATCH SINGLE_MATCH BUSY READ_WARNING Xilinx CAM xapp1151_param_cam.pdf 8

9 CAM Read Operation Search a key Search Data DIN[M:0] MATCH_ADDR[J:0] MULTIPLE_MATCH SINGLE_MATCH CAM Address 0 0 CLK EN WE CAM Address Search Data match? Search Data xapp1151_param_cam.pdf 9

10 Write Operation Write Data CAM Address DIN[M:0] WR_ADDR[logN:0] 0 1 CLK EN WE CAM Address Search Data write xapp1151_param_cam.pdf 10

11 Simultaneous Read / Write Write Data CAM Address Search Data DIN[M:0] WR_ADDR[logN:0] DATA_MASK[M:0] CMP_DIN[M:0] CMP_DATA_MASK[M:0] MATCH_ADDR[J:0] MULTIPLE_MATCH SINGLE_MATCH CAM Address 1 CLK EN WE BUSY READ_WARNING EN=1 simultaneous write/read Simultaneous Read/Write Simultaneous write and search operations With an to warn the user of possible collision Read warning flag: The data applied to the CAM for a read Matches the data that is currently being written into the CAM By unfinished write operation xapp1151_param_cam.pdf 11

12 Ternary Mode Cache Address DIN[M:0] WR_ADDR[logN:0] DATA_MASK[M:0] CMP_DIN[M:0] CMP_DATA_MASK[M:0] MATCH_ADDR[J:0] MULTIPLE_MATCH SINGLE_MATCH 1 CLK EN WE BUSY READ_WARNING EN=1 simultaneous write/read DIN[M:0] Data in Bus The data to be written into The data read from the CAM Simultaneous read/write mode CMP_DIN for the read operation Standard Ternary mode DIN DATA_MASK X 1 1 X CMP_DIN[M:0] Compare Data In Bus Simultaneous read/write The data read from the CAM Ternary mode One of the two buses To determine the bit value During read operation xapp1151_param_cam.pdf 12

13 SRAM Cell bit bit_b word CMOS VLSI Design 4 th ed, Weste 13

14 SRAM Bit Cell RTL Model S Q R Read / Write = 1 READ op Read / Write Read / Write = 0 WRITE op en.wikipedia.org Read / Write 14

15 SRAM Bit Cell Read & Write Operations 0 S Q 1 Input x x S Q 0 0 R xb R 0 1 Read / Write = 1 READ op Read / Write = 0 WRITE op HOLD S=0 Q=old Q Input x=1 SET S=1 Q=1 R=0 Q=old Q R=0 Q=0 Input x=0 RESET S=0 Q=0 en.wikipedia.org R=1 Q=1 15

16 10T CAM Cell bit bit_b word match CMOS VLSI Design 4 th ed, Weste 16

17 SRAM Bit Cell RTL Model match Read / Write 17

18 CAM Bit Cell RTL Model ' match S Q read / write R match Read / Write = 1 READ op Read / Write = 0 WRITE op Read / Write 18

19 CAM Bit Cell RTL Model Read / Write Operations 0 S Q x S Q 0 R match_out xb R match_out Read / Write = 1 READ op 0 Read / Write = 0 WRITE op HOLD S=0 Q=old Q Input x=1 SET S=1 Q=1 R=0 Q=old Q R=0 Q=0 Input x=0 RESET S=0 Q=0 R=1 Q=1 19

20 2x2 CAM Bit Cell RTL Model Ain1 Ain0 CAM Address Read / Write match Read / Write match match match Read / Write Read / Write r/w 20

21 Diagram for a with 2 lines 4-bit word A1 A0 D3 D2 D1 D0 Read / Write match Read / Write match Read / Write match Read / Write match r/w R/W O3 O2 O1 O0 Main Memory MM Address data 08 AB AB 21

22 Cache Organization 8 sets 1-way 1 line / set 4 sets 2-way 2 lines / set 2 sets 4-way 4 lines / set 1 set 8-way 8 lines / set 22

23 Direct Mapping Cache Memory Main Memory 8 sets 1-way 1 line / set The main memory blocks in the same set share one cache block 23

24 2-Way Set Associative Mapping Cache Memory Main Memory 4 sets 2-way 2 lines / set The main memory blocks in the same set share two cache blocks 24

25 4-way Set Associative Mapping Cache Memory Main Memory 2 sets 4-way 4 line / set The main memory blocks in the same set share four cache blocks 25

26 Fully Associative Mapping Cache Memory Main Memory 1 sets 8-way 8 line / set The main memory blocks in the one and the only set share the entire cache blocks 26

27 Tag Field tag set block 8 sets 1-way 1 line / set 4 sets 2-way 2 lines / set 2 sets 4-way 4 lines / set 1 set 8-way 8 lines / set 27

28 Cache Mapping Method (set-view) 8 sets 1-way 1 line / set 4 sets 2-way 2 lines / set 2 sets 4-way 4 lines / set 1 set 8-way 8 lines / set 28

29 Cache Mapping Method (set-view) 8 sets 1-way 1 line / set 4 sets 2-way 2 lines / set 2 sets 4-way 4 lines / set 1 set 8-way 8 lines / set 29

30 Cache Mapping Method (way-view) 8 sets 1-way 1 line / set 4 sets 2-way 2 lines / set 2 sets 4-way 4 lines / set 1 set 8-way 8 lines / set 30

31 Direct Mapping 8 sets 1-way 1 line / set C 31

32 2-Way Set Associative Mapping 4 sets 2-way 2 lines / set C C 32

33 4-way Set Associative Mapping 2 sets 4-way 4 line / set C C C C 33

34 Fully Associative Mapping 1 sets 8-way 8 line / set C C C C C 34

35 CAM (Content Addressable Memory) 35

36 CAM (Content Addressable Memory) 36

37 CAM (Content Addressable Memory) 37

38 CAM (Content Addressable Memory) 38

39 SRAM Bit Cell RTL Model match_in out match_out Read / Write 39

40 CAM Bit Cell RTL Model match_in S Q R match_out Read / Write = 1 READ op Read / Write = 0 WRITE op Read / Write ' match_in match_out read / write 40

41 CAM Bit Cell RTL Model Read / Write Operations match_in match_in 0 S Q x S Q 0 0 R match_out 0 1 Read / Write = 1 READ op xb R 0 Read / Write = 0 WRITE op 0 match_out HOLD S=0 Q=old Q Input x=1 SET S=1 Q=1 R=0 Q=old Q R=0 Q=0 Input x=0 RESET S=0 Q=0 R=1 Q=1 41

42 2x2 CAM Bit Cell RTL Model Ain1 Ain0 match_in out match_in out match_out match_out Read / Write Read / Write match_in out match_in out match_out match_out Read / Write Read / Write r/w Aout1 Aout0 42

43 References [1] [2] [3] [4] [5] [6] [7] [8] Digital Systems, Hill, Peterson, 1987