Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method
|
|
- Piers Eaton
- 6 years ago
- Views:
Transcription
1 Fault Testing of CMOS Integrated Circuits Using Signature Analysis Method Prof. R.H. Khade 1 and Mr. Swapnil Gourkar 2 1 Associate Professor, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel, Mumbai University 2 Lecturer, Department of Electronics Engineering, Pillai Institute of Information Technology, New Panvel, Mumbai University ABSTRACT Moore s law states that the number of transistors in integrated circuits doubles every 18 months. Increasing complexity of digital system over the past decade has made it essential to increase the awareness of need of fault testing and diagnosis. With the increase in complexity of the digital system, a test simulation along with diagnosis has become an important issue in VLSI testing. In this paper, a signature analysis method is presented for testing of CMOS integrated circuits. Keywords: VLSI, CMOS, Testing, Signature 1. INTRODUCTION There has been a continuous pressure on VLSI chip manufacturing industry to increase the manufacturing yield. Integrated circuit manufacturers are constantly trying to decrease the number of faulty parts they produce. The reliability of System-on-Chips must be ensured to a certain extent since a single fault is likely to make the whole chip useless. Therefore, fault diagnosis and fault repairing techniques are gaining importance these days. A manufacturer may be able to improve the circuit design or the manufacturing process by analyzing the parts that fail production tests and determining the cause of failure for each part. Detection of fault and the type of fault present in a circuit is known as fault diagnosis. With the growth of technology and advent of reconfigurable circuits like FPGAs, PLAs, PLDs etc. testing only for faulty chip is not adequate [1]. Fault location may be required to identify and then replace or discard the faulty sub-circuit. It can also be used to analyze the defect causing the faulty behavior. Fault diagnosis is executed upon manufactured chips, which are found to be faulty in order to identify the position and types of the faults present in them [2]. 2. HISTORICAL BACKGROUND Current measurement based testing of electronics components has always been an integral part of the testing since the birth of semiconductor industry. It is used to detect gross shorts and is generally referred to as static I DD test. The present form of quiescent current (I DDQ ) measurement based testing for CMOS VLSI, known as I DDQ testing, was first publicly proposed in 1981 [1] and then formulated in [2] and [4] for the detection of bridging faults. Around the same time, researchers at IBM also proposed the monitoring of switching current to detect transient failures (noise related failures) in memory devices [5]. 3. TESTING OF THE CHIPS Fault simulation is the process of simulating a circuit with a given set of test patterns and a set of faults, and comparing the response of the circuit with each fault to that of the fault-free circuit. INPUT PATTERN CIRCUIT UNDER TEST OUTPUT RESPONSE CORRECT RESPONSE COMPARATOR TEST RESULT Figure 1 Test set up for testing a circuit If the response does not match, the fault is considered detected by the given set of test patterns. Figure 1 illustrates the basic principle of digital testing. Input patterns called test vectors are applied to the inputs of the circuit. The response Volume 2, Issue 5, May 2013 Page 73
2 of the circuit is compared with the expected response. The circuit is considered good if the responses match, else the circuit is faulty. The quality of the tested circuit depends upon the thoroughness of the test vectors. 4. IDDQ TESTING I DDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state powersupply current. I DDQ stands for quiescent power-supply current. Today, the majority of ICs are manufactured using complementary metal oxide semiconductor (CMOS) technology. In steady state, when all switching transients are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current in a defect-free CMOS circuit is negligible (on the order of few nano amperes). However, in case of a defect such as gate-oxide short or short between two metal lines, a conduction path from power-supply (V DD ) to ground (GND) is formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of magnitude higher than the fault-free leakage current. Thus, by monitoring the power-supply current, one may distinguish between faulty and fault-free circuit [3]. The steady state or quiescent current (I DDQ ) testing of CMOS integrated circuits is known to be very efficient for improving test quality [8]. The test methodology based on the observation of the quiescent current on power supply lines allows a good coverage of physical defects such as gate-oxide shorts, floating gates and bridging faults. These defects are neither well modelled by the classical fault models, nor detectable by conventional logic tests. In addition, I DDQ testing can be used as a reliability predictor due to its ability to detect defects that do not yet involve faulty circuit behaviour, but could be transformed into functional failures at an early stage of circuit life. Thus, I DDQ testing became a powerful complement to the conventional logic testing. Under the fault conditions, the normal values of I DDQ may be increased, decreased or generally distorted. Thus, fault detection can be accomplished by monitoring the Iddq current fluctuations using a current sensing circuit. In report, a simple built-in current sensor (BICS) is presented, which provides a digital output for supply current monitoring and testing in circuits. BICS is inserted in series with the power supply or the ground of the Circuit under test (CUT) to detect abnormal I DDQ current in the integrated circuit [6] as shown in Figure 2. Figure 2 Block diagram of I DDQ testing. Irrespective of all the advantages of I DDQ testing, there are some problems in using this method. Since the normal I DDQ is very low, measurements must be precise. Also, setting I DDQ threshold on bad devices can be hard. In case of open faults, the I DDQ becomes very small making it difficult to measure and compare with the threshold. To overcome all the problems occurring in the I DDQ testing a signature analysis method is used. 4. SIGNATURE ANALYSIS METHOD Signature analysis uses statistical inference techniques to deduce possible failure mechanisms with limited failure analysis. The goal of signature analysis (SA) is to significantly reduce the amount of failure analysis (FA) that a laboratory must perform. The knowledge obtained from prior comprehensive FA is used to assign a confidence level to Volume 2, Issue 5, May 2013 Page 74
3 the failure mechanism of an IC with a similar failure mode. In addition, SA can be used to determine the number of ICs that must be comprehensively analyzed to obtain a certain degree of confidence for a specific failure mechanism. The most powerful aspect of this method is the ability to implement it for single failures, making it useful for field returns, qualification failures, and other one of a kind failures. Another important benefit of this method is the ability to use a low degree of belief with any number of signatures that are not well known or rely entirely on expert opinion. This method obviously requires a standard set of failure mechanisms as well as a standard set of terms and definitions for failure analysis. This SA method has the ability to be incorporated into an automated IC diagnosis process that uses defect models and classes for site localization in addition to failure mechanism determination. Improved models and diagnosis procedures will help reduce the amount of testing and physical failure analysis necessary to determine a signature for the failure mechanism and its location. Signature analysis is potentially a powerful method for reducing the level of work and improving the efficiency of an FA laboratory. While this method may reduce the level of work in a different manner than other signature analysis methodologies, it is more flexible and provides structure to the FA process. In this paper, signature analysis method is used to detect the faults in integrated circuits. For this, we first find the signature of the circuit and compare it with the actual output of the circuit using software simulation. Then by enabling different faults in the circuit we are going to obtain different simulation results. The simulation results corresponding to different faults are stored and these results are then compared with the signature of the circuit. Figure 3 Circuit to obtain the signature of integrated circuits Figure 3 shows the circuit diagram used to test any NMOS or PMOS combinational circuit. Initially no input is applied to the combinational circuit to be tested. NMOS is initially off & capacitor has no charge stored in it. Now input is given to the NMOS so it turns ON. Then the current direction is V DD -NMOS-C-V DD. Now capacitor is charged to value V DD. Then input to NMOS is made low & it turns OFF. Now capacitor is charged but it does not have any path to get discharged. When input is given to the combinational circuit, it turns ON & capacitor gets a path to discharge. The capacitor then discharges through the circuit. The time required for the capacitor depends on various parameters of the NMOS & PMOS in the circuit. This time period is then compared with the time period obtained in the simulation results. Using the circuit shown in fig.(4), we can find the signature of an inverter IC which is then compared with the simulated results of the fault free IC. Figure 4 Circuit for finding the signature of the inverter IC Volume 2, Issue 5, May 2013 Page 75
4 Figure 5 Signature of a fault-free inverter IC Figure 6 Signature of the faulty inverter IC (Length of channel is less than the normal) Volume 2, Issue 5, May 2013 Page 76
5 Figure 7 Signature of the faulty inverter IC (Length of channel is larger than the normal) Figure 8 Signature of the faulty inverter IC (Source of NMOS transistor is open) Volume 2, Issue 5, May 2013 Page 77
6 Figure 9 Signature of the faulty inverter IC (Drain of PMOS transistor is open) Figure 10 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of PMOS) Volume 2, Issue 5, May 2013 Page 78
7 Figure 11 Signature of the faulty inverter IC (Stuck-at-0 fault at the gate of NMOS) Figure 12 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of PMOS) Volume 2, Issue 5, May 2013 Page 79
8 Figure 13 Signature of the faulty inverter IC (Stuck-at-1 fault at the gate of NMOS) Figure 14 Circuit for comparing the signature of the fault free IC and IC under test Figure 5 shows the signature of the fault free inverter IC. In this signature, it can be seen that when the input is given to the inverter, the capacitor C starts discharging through it. In this figure, for fault free circuit voltage across capacitor and output of inverter is shown. Figure 6 to 13 show the responses of the inverter IC with different faults. These faults occur when the length or width of the channel of the transistors is varied or in the presence of stuck-at faults at various Volume 2, Issue 5, May 2013 Page 80
9 nodes. Figure 14 shows the circuit which compares the signature of the faulty IC with the fault free IC. This circuit contains two counters which counts the number of pulses at the output of the inverter. The outputs of the two counters are 4-bit binary numbers which are then given to a comparator IC. If the IC under test is fault free then the outputs of both the counters will be same and the comparator will show no fault. But if there is any fault in the IC, the output of both the counters will be different and the comparator will show that the IC is faulty. 5. CONCLUSION A new method for signature analysis has been described. This method provides a robust and flexible way to implement signature analysis. The most powerful aspect of this method is the ability to implement it for single failures, making it useful for field returns, qualification failures. Another important benefit of this method is the ability to use a low degree of belief with any number of signatures that are not well known or rely entirely on expert opinion. This method obviously requires a standard set of failure mechanisms as well as a standard set of terms and definitions for failure analysis. This SA method has the ability to be incorporated into an automated IC diagnosis process that uses defect models and classes for site localization in addition to failure mechanism determination. Improved models and diagnosis procedures will help reduce the amount of testing and physical failure analysis necessary to determine a signature for the failure mechanism and its location. References [1] Groza, V.; Abielmona, R.; Assaf, M.H.; Elbadri, M.; El-Kadri, M.; Khalaf, A.; A Self-Reconfigurable Platform for Built-In Self-Test Applications, Instrumentation and Measurement, IEEE Transactions on, vol.56, no.4, pp , Aug [2] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, [3] Rochit Rajsuman, Iddq Testing for CMOS VLSI, PROCEEDINGS OF THE IEEE, VOL. 88, NO. 4, APRIL [4] J. M. Acken, Testing for bridging faults (shorts) in CMOS circuits, in Design Auto. Conf., 1983, pp [5] R. Y. Li, S. C. Diehl, and S. Harrison, Power supply noise testing of VLSI chips, in Int. Test Conf., 1983, pp [6] D. Baschiera and B. Courtois, Testing CMOS: A challenge, in VLSI Design, Oct. 1984, pp [7] C. F. Hawkins and J. Soden, Electrical characteristics and testing for gate oxide shorts in CMOS ICs, in Int. Test Conf., 1985, pp [8] E. I. Muehldorf, A quality measure for LSI components, IEEE J. Solid State Circuits, pp , Oct [9] R. L. Wadsack, Fault modeling and logic simulation of CMOS and MOS integrated circuits, Bell Syst. Tech. J., pp , May June [10] J. Shen, W. Maly, and F. Ferguson, Systematic characterization of physical defects for fault analysis of MOS IC cells, in Int. Test Conf., 1984, pp [11] H.Walker and S. Director, VLASIC: A catastrophic fault yield simulator for integrated circuits, IEEE Trans. Computer-Aided Design, pp , Jan [12] M. Abramovici, M. A. Breuer and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, [13] Bob Duell, Iddq made easy CMOS Iddq test methodology Fundamental concepts, System Science, Inc., Revised edition,1997. [14] J.M. Soden, C.F. Hawkins, R.K. Gulati and W. Mao IDDQ testing: a review, Journal of Electronic Testing: Theory And Applications, vol.3, 1992, pp [15] S.D McEuen, Reliability benefits of IDDQ, J. of Electronic Testing: Theory and Application, Vol.3, 1992, pp [16] J.A. Segura, V.H. Champac, R.R. Montanes, J. Figueras and J.A. Rubio, Quiescent current analysis and experimentation of defective CMOS circuits, J. of Electronic Testing: Theory and Applications, Vol.3, 1992, pp [17] P. Nigh, W. Maly, Test generation for current testing, IEEE Design and Test of Computers, Feb.1990, pp [18] S.D McEuen, Reliability benefits of IDDQ, J. of Electronic Testing: Theory and Application, Vol.3, 1992, pp [19] K.J. Lee and J.J. Tang, A built-in current sensor based on current-mode design, IEEE Transactions on Circuits and Systems-II Analog and Digital Signal Processing, Vol. 45, No. 1, Jan.1998, pp [20] T.L. Shen, J. C. Daly, and J. C. Lo, On Chip current sensing circuit for CMOS VLSI, Proc. IEEE VLSI Test Symposium paper 16.2, 1992, pp [21] Christopher L. Henderson and Jerry M. Soden, A Signature Analysis Method for IC Failure Analysis, International Symposium for Testing and Failure Analysis, Nov I996. Volume 2, Issue 5, May 2013 Page 81
10 AUTHOR Rajendrakumar H. Khade is born in Akola district of Maharashtra state (India) on August 10, He has completed B.E. Electronics from S.G.G.S. Institute of Engineering and Technology, Vishnupuri Nanded (MS) India in 1987 and M.E. Electronics from V.J.T.I. Mumbai in 1999.He worked as faculty of Electronics department of R.A.I.T. Nerul, Navi Mumbai for 23 years. From July 2011 he joined Pillai Institute of Information Technology, New Panvel. His special fields of interest include VLSI, Digital System Design, Image Processing. Swapnil S. Gourkar received the B.E. degree in Electronics and Telecommunication Engineering in 2010 from Jawaharlal Darda Institute of Engineering and Technology, Yavatmal. Currently he is pursuing Masters Degree in Electronics Engineering from Pillai Institute of Information Technology, New Panvel and also working as a lecturer for under graduate programme at the same institute since His fields of interest are VLSI and Digital Electronics. Volume 2, Issue 5, May 2013 Page 82
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET4076) Lecture 8(2) I DDQ Current Testing (Chapter 13) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Learning aims Describe the
More informationDriving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG
Driving Toward Higher I DDQ Test Quality for Sequential Circuits: A Generalized Fault Model and Its ATPG Hisashi Kondo Kwang-Ting Cheng y Kawasaki Steel Corp., LSI Division Electrical and Computer Engineering
More informationUNIT IV CMOS TESTING
UNIT IV CMOS TESTING 1. Mention the levels at which testing of a chip can be done? At the wafer level At the packaged-chip level At the board level At the system level In the field 2. What is meant by
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 10 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Content Manufacturing Defects Wafer defects Chip defects Board defects system defects
More informationCALCULATION OF POWER CONSUMPTION IN 7 TRANSISTOR SRAM CELL USING CADENCE TOOL
CALCULATION OF POWER CONSUMPTION IN 7 TRANSISTOR SRAM CELL USING CADENCE TOOL Shyam Akashe 1, Ankit Srivastava 2, Sanjay Sharma 3 1 Research Scholar, Deptt. of Electronics & Comm. Engg., Thapar Univ.,
More informationOutline. Definition. Targeted Defects. Motivation GOAL. Ferhani, RATS/SPRING , Center for Reliable Computing 1
RATS (Reliability and Testability Seminar) Diagnosis of Defects Introducing Voltage Dependences between Nodes By François-Fabien Ferhani 5/27/2003 Ferhani, RATS/SPRING03 Outline Introduction Problems &
More informationTestability Design for Sleep Convention Logic
Advances in Computational Sciences and Technology ISSN 0973-6107 Volume 11, Number 7 (2018) pp. 561-566 Research India Publications http://www.ripublication.com Testability Design for Sleep Convention
More informationInternational Journal of Scientific & Engineering Research, Volume 5, Issue 2, February ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 2, February-2014 938 LOW POWER SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY T.SANKARARAO STUDENT OF GITAS, S.SEKHAR DILEEP
More informationLab. Course Goals. Topics. What is VLSI design? What is an integrated circuit? VLSI Design Cycle. VLSI Design Automation
Course Goals Lab Understand key components in VLSI designs Become familiar with design tools (Cadence) Understand design flows Understand behavioral, structural, and physical specifications Be able to
More informationDESIGN AND SIMULATION OF 1 BIT ARITHMETIC LOGIC UNIT DESIGN USING PASS-TRANSISTOR LOGIC FAMILIES
Volume 120 No. 6 2018, 4453-4466 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ DESIGN AND SIMULATION OF 1 BIT ARITHMETIC LOGIC UNIT DESIGN USING PASS-TRANSISTOR
More informationA Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution Irith Pomeranz 1 and Sudhakar M. Reddy 2 School of Electrical & Computer Eng. Electrical &
More informationOptimal Clustering and Statistical Identification of Defective ICs using I DDQ Testing
Optimal Clustering and Statistical Identification of Defective ICs using I DDQ Testing A. Rao +, A.P. Jayasumana * and Y.K. Malaiya* *Colorado State University, Fort Collins, CO 8523 + PalmChip Corporation,
More informationVLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET4076) Lecture 4(part 2) Testability Measurements (Chapter 6) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Previous lecture What
More informationModeling and Comparative Analysis of Logic Gates for Adder and Multiplier Applications -A VLSI based approach
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 3, Ver. I (May. -Jun. 2016), PP 67-72 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Modeling and Comparative Analysis
More informationFaults. Abstract. 1. Introduction. * Nur A. Touba is now with the Department of Electrical and Computer Engineering, University of Texas, Austin, TX
s Abstract While previous research has focused on deterministic testing of bridging faults, this paper studies pseudo-random testing of bridging faults and describes a means for achieving high fault coverage
More informationLOGIC EFFORT OF CMOS BASED DUAL MODE LOGIC GATES
LOGIC EFFORT OF CMOS BASED DUAL MODE LOGIC GATES D.Rani, R.Mallikarjuna Reddy ABSTRACT This logic allows operation in two modes: 1) static and2) dynamic modes. DML gates, which can be switched between
More informationSimulation and Analysis of SRAM Cell Structures at 90nm Technology
Vol.1, Issue.2, pp-327-331 ISSN: 2249-6645 Simulation and Analysis of SRAM Cell Structures at 90nm Technology Sapna Singh 1, Neha Arora 2, Prof. B.P. Singh 3 (Faculty of Engineering and Technology, Mody
More informationPower Analysis for CMOS based Dual Mode Logic Gates using Power Gating Techniques
Power Analysis for CMOS based Dual Mode Logic Gates using Power Gating Techniques S. Nand Singh Dr. R. Madhu M. Tech (VLSI Design) Assistant Professor UCEK, JNTUK. UCEK, JNTUK Abstract: Low power technology
More information6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1
6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,
More informationInternational Journal of Advance Engineering and Research Development LOW POWER AND HIGH PERFORMANCE MSML DESIGN FOR CAM USE OF MODIFIED XNOR CELL
Scientific Journal of Impact Factor (SJIF): 5.71 e-issn (O): 2348-4470 p-issn (P): 2348-6406 International Journal of Advance Engineering and Research Development Volume 5, Issue 04, April -2018 LOW POWER
More informationA Fault Model for VHDL Descriptions at the Register Transfer Level *
A Model for VHDL Descriptions at the Register Transfer Level * Abstract This paper presents a model for VHDL descriptions at the Register Transfer Level and its evaluation with respect to a logic level
More informationIntroduction to ICs and Transistor Fundamentals
Introduction to ICs and Transistor Fundamentals A Brief History 1958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 2003 Intel Pentium 4 mprocessor (55
More informationSense Amplifiers 6 T Cell. M PC is the precharge transistor whose purpose is to force the latch to operate at the unstable point.
Announcements (Crude) notes for switching speed example from lecture last week posted. Schedule Final Project demo with TAs. Written project report to include written evaluation section. Send me suggestions
More information250nm Technology Based Low Power SRAM Memory
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 1, Ver. I (Jan - Feb. 2015), PP 01-10 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org 250nm Technology Based Low Power
More informationComplex test pattern generation for high speed fault diagnosis in Embedded SRAM
Complex test pattern generation for high speed fault diagnosis in Embedded SRAM 1 Prasanna Kumari P., 2 Satyanarayana S. V. V., 3 Nagireddy S. 1, 3 Associate professor, 2 Master of Engineering, Teegala
More informationAn Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy
An Advanced and more Efficient Built-in Self-Repair Strategy for Embedded SRAM with Selectable Redundancy A. Sharone Michael.1 #1, K.Sivanna.2 #2 #1. M.tech student Dept of Electronics and Communication,
More informationDesign of Low Power Wide Gates used in Register File and Tag Comparator
www..org 1 Design of Low Power Wide Gates used in Register File and Tag Comparator Isac Daimary 1, Mohammed Aneesh 2 1,2 Department of Electronics Engineering, Pondicherry University Pondicherry, 605014,
More informationAnalysis and Design of Low Voltage Low Noise LVDS Receiver
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 9, Issue 2, Ver. V (Mar - Apr. 2014), PP 10-18 Analysis and Design of Low Voltage Low Noise
More informationInternational Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering
IP-SRAM ARCHITECTURE AT DEEP SUBMICRON CMOS TECHNOLOGY A LOW POWER DESIGN D. Harihara Santosh 1, Lagudu Ramesh Naidu 2 Assistant professor, Dept. of ECE, MVGR College of Engineering, Andhra Pradesh, India
More informationDesign and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology
Vol. 3, Issue. 3, May.-June. 2013 pp-1475-1481 ISSN: 2249-6645 Design and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology Bikash Khandal,
More informationINTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume 9 /Issue 3 / OCT 2017
Design of Low Power Adder in ALU Using Flexible Charge Recycling Dynamic Circuit Pallavi Mamidala 1 K. Anil kumar 2 mamidalapallavi@gmail.com 1 anilkumar10436@gmail.com 2 1 Assistant Professor, Dept of
More informationContent Addressable Memory performance Analysis using NAND Structure FinFET
Global Journal of Pure and Applied Mathematics. ISSN 0973-1768 Volume 12, Number 1 (2016), pp. 1077-1084 Research India Publications http://www.ripublication.com Content Addressable Memory performance
More informationCHAPTER 1 INTRODUCTION
CHAPTER 1 INTRODUCTION Rapid advances in integrated circuit technology have made it possible to fabricate digital circuits with large number of devices on a single chip. The advantages of integrated circuits
More informationAnalysis of 8T SRAM with Read and Write Assist Schemes (UDVS) In 45nm CMOS Technology
Analysis of 8T SRAM with Read and Write Assist Schemes (UDVS) In 45nm CMOS Technology Srikanth Lade 1, Pradeep Kumar Urity 2 Abstract : UDVS techniques are presented in this paper to minimize the power
More informationMetodologie di progetto HW Il test di circuiti digitali
Metodologie di progetto HW Il test di circuiti digitali Introduzione Versione del 9/4/8 Metodologie di progetto HW Il test di circuiti digitali Introduction VLSI Realization Process Customer s need Determine
More informationMicroelettronica. J. M. Rabaey, "Digital integrated circuits: a design perspective" EE141 Microelettronica
Microelettronica J. M. Rabaey, "Digital integrated circuits: a design perspective" Introduction Why is designing digital ICs different today than it was before? Will it change in future? The First Computer
More informationMetodologie di progetto HW Il test di circuiti digitali
Metodologie di progetto HW Il test di circuiti digitali Introduzione Versione del 9/4/8 Metodologie di progetto HW Il test di circuiti digitali Introduction Pag. 2 VLSI Realization Process Customer s need
More informationLow Power Testing of VLSI Circuits Using Test Vector Reordering
International Journal of Electrical Energy, Vol. 2, No. 4, December 2014 Low Power Testing of VLSI Circuits Using Test Vector Reordering A. M. Sudha Department of Electrical and Electronics Engineering,
More informationVLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET4076) Lecture 2 (p2) Fault Modeling (Chapter 4) Said Hamdioui Computer Engineering Lab Delft University of Technology 2009-2010 1 Previous lecture What are the different
More informationEE3032 Introduction to VLSI Design
EE3032 Introduction to VLSI Design Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan Contents Syllabus Introduction to CMOS
More informationLOW POWER SRAM CELL WITH IMPROVED RESPONSE
LOW POWER SRAM CELL WITH IMPROVED RESPONSE Anant Anand Singh 1, A. Choubey 2, Raj Kumar Maddheshiya 3 1 M.tech Scholar, Electronics and Communication Engineering Department, National Institute of Technology,
More informationTernary Content Addressable Memory Types And Matchline Schemes
RESEARCH ARTICLE OPEN ACCESS Ternary Content Addressable Memory Types And Matchline Schemes Sulthana A 1, Meenakshi V 2 1 Student, ME - VLSI DESIGN, Sona College of Technology, Tamilnadu, India 2 Assistant
More informationA Low Power 32 Bit CMOS ROM Using a Novel ATD Circuit
International Journal of Electrical and Computer Engineering (IJECE) Vol. 3, No. 4, August 2013, pp. 509~515 ISSN: 2088-8708 509 A Low Power 32 Bit CMOS ROM Using a Novel ATD Circuit Sidhant Kukrety*,
More informationTESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS
TESTING OF FAULTS IN VLSI CIRCUITS USING ONLINE BIST TECHNIQUE BASED ON WINDOW OF VECTORS Navaneetha Velammal M. 1, Nirmal Kumar P. 2 and Getzie Prija A. 1 1 Department of Electronics and Communications
More informationDYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech)
DYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech) K.Prasad Babu 2 M.tech (Ph.d) hanumanthurao19@gmail.com 1 kprasadbabuece433@gmail.com 2 1 PG scholar, VLSI, St.JOHNS
More informationTailoring Tests for Functional Binning of Integrated Circuits
2012 IEEE 21st Asian Test Symposium Tailoring Tests for Functional Binning of Integrated Circuits Suraj Sindia Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Alabama,
More informationIMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3
IMPLEMENTATION OF LOW POWER AREA EFFICIENT ALU WITH LOW POWER FULL ADDER USING MICROWIND DSCH3 Ritafaria D 1, Thallapalli Saibaba 2 Assistant Professor, CJITS, Janagoan, T.S, India Abstract In this paper
More informationTESTING AND TESTABLE DESIGN OF DIGITAL SYSTES
TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Kewal K. Saluja University of Wisconsin - Madison Motivation, Fault Models and some Callenges Overview Motivation Technology, Test cost, and VLSI realization
More informationAnalysis of 8T SRAM Cell Using Leakage Reduction Technique
Analysis of 8T SRAM Cell Using Leakage Reduction Technique Sandhya Patel and Somit Pandey Abstract The purpose of this manuscript is to decrease the leakage current and a memory leakage power SRAM cell
More informationECE 637 Integrated VLSI Circuits. Introduction. Introduction EE141
ECE 637 Integrated VLSI Circuits Introduction EE141 1 Introduction Course Details Instructor Mohab Anis; manis@vlsi.uwaterloo.ca Text Digital Integrated Circuits, Jan Rabaey, Prentice Hall, 2 nd edition
More informationESD Protection Design for Mixed-Voltage I/O Interfaces -- Overview
ESD Protection Design for Mixed-Voltage Interfaces -- Overview Ming-Dou Ker and Kun-Hsien Lin Abstract Electrostatic discharge (ESD) protection design for mixed-voltage interfaces has been one of the key
More informationFull Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing
Full Custom Layout Optimization Using Minimum distance rule, Jogs and Depletion sharing Umadevi.S #1, Vigneswaran.T #2 # Assistant Professor [Sr], School of Electronics Engineering, VIT University, Vandalur-
More informationEE586 VLSI Design. Partha Pande School of EECS Washington State University
EE586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 1 (Introduction) Why is designing digital ICs different today than it was before? Will it change in
More informationTHE latest generation of microprocessors uses a combination
1254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 11, NOVEMBER 1995 A 14-Port 3.8-ns 116-Word 64-b Read-Renaming Register File Creigton Asato Abstract A 116-word by 64-b register file for a 154 MHz
More informationESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board
ESD Protection Scheme for I/O Interface of CMOS IC Operating in the Power-Down Mode on System Board Kun-Hsien Lin and Ming-Dou Ker Nanoelectronics and Gigascale Systems Laboratory Institute of Electronics,
More informationOptimized CAM Design
Vol. 3, Issue. 5, Sep - Oct. 2013 pp-2640-2645 ISSN: 2249-6645 Optimized CAM Design S. Haroon Rasheed 1, M. Anand Vijay Kamalnath 2 Department of ECE, AVR & SVR E C T, Nandyal, India Abstract: Content-addressable
More informationDESIGN AND PERFORMANCE ANALYSIS OF CARRY SELECT ADDER
DESIGN AND PERFORMANCE ANALYSIS OF CARRY SELECT ADDER Bhuvaneswaran.M 1, Elamathi.K 2 Assistant Professor, Muthayammal Engineering college, Rasipuram, Tamil Nadu, India 1 Assistant Professor, Muthayammal
More informationA Low Power SRAM Cell with High Read Stability
16 ECTI TRANSACTIONS ON ELECTRICAL ENG., ELECTRONICS, AND COMMUNICATIONS VOL.9, NO.1 February 2011 A Low Power SRAM Cell with High Read Stability N.M. Sivamangai 1 and K. Gunavathi 2, Non-members ABSTRACT
More informationA Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications
Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp. 846 850 A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications Jai-Cheol
More informationDesign of local ESD clamp for cross-power-domain interface circuits
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Design of local ESD clamp for cross-power-domain
More informationInternational Journal of Emerging Technologies in Computational and Applied Sciences (IJETCAS)
International Association of Scientific Innovation and Research (IASIR) (An Association Unifying the Sciences, Engineering, and Applied Research) ISSN (Print): 2279-0047 ISSN (Online): 2279-0055 International
More informationDESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTER
DESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTER Amandeep Singh 1, Balwinder Singh 2 1-2 Acadmic and Consultancy Services Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India
More informationLOW POWER WITH IMPROVED NOISE MARGIN FOR DOMINO CMOS NAND GATE
LOW POWER WITH IMPROVED NOISE MARGIN FOR DOMINO CMOS NAND GATE 1 Pushpa Raikwal, 2 V. Neema, 3 S. Katiyal 1,3 School of electronics DAVV, Indore, Madhya Pradesh, India 2 Institute of Engineering and Technology,
More informationAdaptive Techniques for Improving Delay Fault Diagnosis
Adaptive Techniques for Improving Delay Fault Diagnosis Jayabrata Ghosh-Dastidar and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University of Texas,
More informationHigh Performance Memory Read Using Cross-Coupled Pull-up Circuitry
High Performance Memory Read Using Cross-Coupled Pull-up Circuitry Katie Blomster and José G. Delgado-Frias School of Electrical Engineering and Computer Science Washington State University Pullman, WA
More informationImplementation of DRAM Cell Using Transmission Gate
Implementation of DRAM Cell Using Transmission Gate Pranita J. Giri 1, Sunanda K. Kapde 2 PG Student, Department of E&TC, Deogiri Institute of Engineering & Management Studies, Aurangabad (MS), India 1
More informationInternational Journal of Digital Application & Contemporary research Website: (Volume 1, Issue 7, February 2013)
Programmable FSM based MBIST Architecture Sonal Sharma sonal.sharma30@gmail.com Vishal Moyal vishalmoyal@gmail.com Abstract - SOCs comprise of wide range of memory modules so it is not possible to test
More informationDesign of Read and Write Operations for 6t Sram Cell
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 8, Issue 1, Ver. I (Jan.-Feb. 2018), PP 43-46 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Design of Read and Write Operations
More informationA Novel Design of High Speed and Area Efficient De-Multiplexer. using Pass Transistor Logic
A Novel Design of High Speed and Area Efficient De-Multiplexer Using Pass Transistor Logic K.Ravi PG Scholar(VLSI), P.Vijaya Kumari, M.Tech Assistant Professor T.Ravichandra Babu, Ph.D Associate Professor
More informationAn Energy-Efficient Scan Chain Architecture to Reliable Test of VLSI Chips
An Energy-Efficient Scan Chain Architecture to Reliable Test of VLSI Chips M. Saeedmanesh 1, E. Alamdar 1, E. Ahvar 2 Abstract Scan chain (SC) is a widely used technique in recent VLSI chips to ease the
More informationJin-Fu Li. Department of Electrical Engineering. Jhongli, Taiwan
EEA001 VLSI Design Jin-Fu Li Advanced Reliable Systems (ARES) Lab. Department of Electrical Engineering National Central University Jhongli, Taiwan Contents Syllabus Introduction to CMOS Circuits MOS Transistor
More informationSRAM Delay Fault Modeling and Test Algorithm Development
SRAM Delay Fault Modeling and Test Algorithm Development Rei-Fu Huang, Yan-Ting Lai, Yung-Fa Chou, and Cheng-Wen Wu Laboratory for Reliable Computing (LaRC) Department of Electrical Engineering National
More informationAUTONOMOUS RECONFIGURATION OF IP CORE UNITS USING BLRB ALGORITHM
AUTONOMOUS RECONFIGURATION OF IP CORE UNITS USING BLRB ALGORITHM B.HARIKRISHNA 1, DR.S.RAVI 2 1 Sathyabama Univeristy, Chennai, India 2 Department of Electronics Engineering, Dr. M. G. R. Univeristy, Chennai,
More informationAN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS
International Journal of Engineering Inventions ISSN: 2278-7461, www.ijeijournal.com Volume 1, Issue 8 (October2012) PP: 76-80 AN OPTIMAL APPROACH FOR TESTING EMBEDDED MEMORIES IN SOCS B.Prathap Reddy
More informationA Low-Power Field Programmable VLSI Based on Autonomous Fine-Grain Power Gating Technique
A Low-Power Field Programmable VLSI Based on Autonomous Fine-Grain Power Gating Technique P. Durga Prasad, M. Tech Scholar, C. Ravi Shankar Reddy, Lecturer, V. Sumalatha, Associate Professor Department
More informationN-Model Tests for VLSI Circuits
40th Southeastern Symposium on System Theory University of New Orleans New Orleans, LA, USA, March 16-18, 2008 MC3.6 N-Model Tests for VLSI Circuits Nitin Yogi and Vishwani D. Agrawal Auburn University,
More informationDigital Fundamentals. Integrated Circuit Technologies
Digital Fundamentals Integrated Circuit Technologies 1 Objectives Determine the noise margin of a device from data sheet parameters Calculate the power dissipation of a device Explain how propagation delay
More informationDesign of Low Power Digital CMOS Comparator
Design of Low Power Digital CMOS Comparator 1 A. Ramesh, 2 A.N.P.S Gupta, 3 D.Raghava Reddy 1 Student of LSI&ES, 2 Assistant Professor, 3 Associate Professor E.C.E Department, Narasaraopeta Institute of
More informationVHDL Fault Simulation for Defect-Oriented Test and Diagnosis of Digital ICs
VHDL Fault Simulation for Defect-Oriented Test and Diagnosis of Digital ICs F. Celeiro, L. Dias, J. Ferreira, M.B. Santos, J.P. Teixeira INESC / IST, Apartado 13069, 1017 Lisboa Codex, Portugal jct@spirou.inesc.pt
More informationPerformance Evaluation of Guarded Static CMOS Logic based Arithmetic and Logic Unit Design
International Journal of Engineering Research and General Science Volume 2, Issue 3, April-May 2014 Performance Evaluation of Guarded Static CMOS Logic based Arithmetic and Logic Unit Design FelcyJeba
More informationDynamic CMOS Logic Gate
Dynamic CMOS Logic Gate In dynamic CMOS logic a single clock can be used to accomplish both the precharge and evaluation operations When is low, PMOS pre-charge transistor Mp charges Vout to Vdd, since
More informationEfficient Built In Self Repair Strategy for Embedded SRAM with selectable redundancy
Efficient Built In Self Repair Strategy for Embedded SRAM with selectable redundancy *GUDURU MALLIKARJUNA **Dr. P. V.N.REDDY * (ECE, GPCET, Kurnool. E-Mailid:mallikarjuna3806@gmail.com) ** (Professor,
More informationCROWNE: Current Ratio Outliers With Neighbor Estimator
OWNE: Current Ratio Outliers With Neighbor Estimator Sagar S. Sabade D. M. H. Walker Department of Computer Science Texas A&M University College Station, TX 77843-32 Tel: (979) 862-4387 Fax: (979) 847-8578
More informationInstruction-Level Power Consumption Estimation of Embedded Processors for Low-Power Applications
Instruction-Level Power Consumption Estimation of Embedded Processors for Low-Power Applications S. Nikolaidis and Th. Laopoulos Electronics Lab., Physics Dept., Aristotle University of Thessaloniki, Thessaloniki,
More informationCELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHNOLOGY
CELL STABILITY ANALYSIS OF CONVENTIONAL 6T DYNAMIC 8T SRAM CELL IN 45NM TECHNOLOGY K. Dhanumjaya 1, M. Sudha 2, Dr.MN.Giri Prasad 3, Dr.K.Padmaraju 4 1 Research Scholar, Jawaharlal Nehru Technological
More informationElettronica T moduli I e II
Elettronica T moduli I e II Docenti: Massimo Lanzoni, Igor Loi Massimo.lanzoni@unibo.it igor.loi@unibo.it A.A. 2015/2016 Scheduling MOD 1 (Prof. Loi) Weeks 39,40,41,42, 43,44» MOS transistors» Digital
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Practical Information
EE24 - Spring 2000 Advanced Digital Integrated Circuits Tu-Th 2:00 3:30pm 203 McLaughlin Practical Information Instructor: Borivoje Nikolic 570 Cory Hall, 3-9297, bora@eecs.berkeley.edu Office hours: TuTh
More informationCONTENTS CHAPTER 1: NUMBER SYSTEM. Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii)
CONTENTS Foreword...(vii) Preface... (ix) Acknowledgement... (xi) About the Author...(xxiii) CHAPTER 1: NUMBER SYSTEM 1.1 Digital Electronics... 1 1.1.1 Introduction... 1 1.1.2 Advantages of Digital Systems...
More informationDESIGN AND IMPLEMENTATION OF UNIVERSAL GATE USING DG-FinFET 32NM TECHNOLOGY
DESIGN AND IMPLEMENTATION OF UNIVERSAL GATE USING DG-FinFET 32NM TECHNOLOGY SEEMA MEHTA 1, DEVESH KISHORE 2, AASTHA HAJARI 3 PG Scholar 1, Assistant Professor 2,3 Shiv Kumar Singh Institute of Technology
More information(12) United States Patent
US007110229B2 (12) United States Patent Yang et al. (10) Patent No.: (45) Date of Patent: (54) ESD PROTECTION CIRCUIT AND DISPLAY PANELUSING THE SAME (76) Inventors: Sheng-Chieh Yang, No. 120, Jhenfu St.,
More informationC Program Adventures. From C code to motion
C Program Adventures From C code to motion ECE 100 Prof. Erdal Oruklu From C code to motion C Code Motion x=5; if (x!=y) { z=0; } else { z=1; } 1 Compilation of C code Virtual machine program Program download
More informationDESIGN OF PARAMETER EXTRACTOR IN LOW POWER PRECOMPUTATION BASED CONTENT ADDRESSABLE MEMORY
DESIGN OF PARAMETER EXTRACTOR IN LOW POWER PRECOMPUTATION BASED CONTENT ADDRESSABLE MEMORY Saroja pasumarti, Asst.professor, Department Of Electronics and Communication Engineering, Chaitanya Engineering
More informationPERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOLOGIES
PERFORMANCE EVALUATION OF DIFFERENT SRAM CELL STRUCTURES AT DIFFERENT TECHNOLOGIES Sapna Singh 1, Neha Arora 2, Meenakshi Suthar 3 and Neha Gupta 4 Faculty of Engineering Technology, Mody Institute of
More informationDesigning and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power
Designing and Analysis of 8 Bit SRAM Cell with Low Subthreshold Leakage Power Atluri.Jhansi rani*, K.Harikishore**, Fazal Noor Basha**,V.G.Santhi Swaroop*, L. VeeraRaju* * *Assistant professor, ECE Department,
More informationMinimizing Power Dissipation during Write Operation to Register Files
Minimizing Power Dissipation during Operation to Register Files Abstract - This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional
More informationSketch A Transistor-level Schematic Of A Cmos 3-input Xor Gate
Sketch A Transistor-level Schematic Of A Cmos 3-input Xor Gate DE09 DIGITALS ELECTRONICS 3 (For Mod-m Counter, we need N flip-flops (High speeds are possible in ECL because the transistors are used in
More informationHardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur
Hardware Modeling using Verilog Prof. Indranil Sengupta Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur Lecture 01 Introduction Welcome to the course on Hardware
More informationBoolean Algebra and Logic Gates
Boolean Algebra and Logic Gates Binary logic is used in all of today's digital computers and devices Cost of the circuits is an important factor Finding simpler and cheaper but equivalent circuits can
More informationDiagnostic Testing of Embedded Memories Using BIST
Diagnostic Testing of Embedded Memories Using BIST Timothy J. Bergfeld Dirk Niggemeyer Elizabeth M. Rudnick Center for Reliable and High-Performance Computing, University of Illinois 1308 West Main Street,
More informationA Survey on Dram Testing and Its Algorithms
RESEARCH ARTICLE OPEN ACCESS A Survey on Dram Testing and Its Algorithms K.Manju Priya 1, M. Menaka 2 Research Scholar 1, Assistant professor 2 ECE Department (ME VLSI DESIGN) SVS College of Engineering,
More information