A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications

Transcription

1 Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002, pp A Single Poly Flash Memory Intellectual Property for Low-Cost, Low-Density Embedded Nonvolatile Memory Applications Jai-Cheol Lee, Jong-sun Kim and Shiho Kim Department of Electrical, Electronic and Information Engineering, Wonkwang University, Iksan (Received 23 April 2002) A low-cost, low-density embedded nonvolatile memory using a single poly Flash memory has been developed. Since the single poly Flash memory can be fabricated without any additional masks and processing steps other than a standard CMOS logic technology, it can be used for small nonvolatile storage in a logic chip. The test chip was designed and has manufactured using 0.25 µm foundry CMOS logic technology. The unit cell size was 62.5 µm 2 and the memory macro unit had a configuration of 32 word lines with 8-bits. PACS numbers: Bv Keywords: Flash memory, Embedded momory I. INTRODUCTION A requirement exists for a low-density non-volatile memory to be integrated on a chip that can be used for redundancy circuits or to store ID codes. It may not be appropriate to add additional masking or processing steps on top of the standard single poly CMOS (Complementary Metal Oxide Semiconductor) process to make the floating gates of memory cells only for small-density Flash memories below several kbits [1,2]. Incorporating EEPROM process will make the process complex, and, in turn, the manufacturing cost of the chip becomes expensive. Therefore, a Flash memory IP(Intellectual Property) that can be manufactured with single poly CMOS technology without any additional process steps can provide a low cost solution to many application problems. A floating gate device that is compatible with a single poly CMOS process has long been known [3, 4], but it is relatively new approach to use it as a reusable IP for an embedded memory. Bergemont et al. [5] proposed a single poly Flash memory cell that had a floating gate PMOS (P-type Metal Oxide Semiconductor) and NMOS (N-type Metal Oxide Semiconductor) select switch. A cell with about a 100 µsec programming time in 0.25 µm technology needs ultraviolet radiation to erase the cell, which makes the technology impractical for a Flash memory cell. McPartland et al. [6] proposed a single poly Flash structure that used a PMOS gate and a NMOS gate as a floating gate to store data and well electrodes as a control gate (CG) and an erase gate (EG). Although the cell size is relatively large, it is practical since the cell can jclee@wonkwang.ac.kr be electrically erased with a low erasing voltage below 12 volts [6]. We incorporated McPartland s Flash structure as a base model and developed novel cell array and core circuits for a Flash memory IP that is compatible with the single poly CMOS technology. II. MEMORY CELL AND ARRAY Figure 1 shows the cell of the single poly Flash memory. The gates of a NMOS transistor MN1 and two PMOS transistors, MP1 and MP2, are connected together to form a floating gate (FG) [6]. The N-well of MP1 is used as a control gate (CG) and the N-well of MP2 is used as an erase gate (EG). Most foundry single poly CMOS technologies have two types of gate oxides, one is a thin oxide for internal core circuits, and the other is a thick oxide for I/O circuits. In Anam Semiconductor s 0.25 µm technology, the target process for the test chip, the gate oxide thickness of the transistors in the core logic is 50 Å while gate oxide thickness of the tran- Fig. 1. Single poly Flash memory cell. The unit of size is in µm.

2 A Single Poly Flash Memory Intellectual Property for Low-Cost Jai-Cheol Lee et al Fig. 2. Measured I-V characteristics of the erased and programmed cell. sistors for I/O circuits is 85 Å. We could use transistors with gate oxide thickness of 85 Å for the memory cells and the high voltage circuits. The programming voltage can be lowered by increasing a coupling ratio between CG and FG. On the other hand, in order to lower the erase voltage, a lower coupling ratio between the EG and the FG is required. We selected the sizes of MP1 and MP2 to obtain a coupling ratio of above 90 % between CG and EG and below 5 % between EG and FG. With this sizing, we designed the operating voltage of the cell as summarized in Table 1. The target threshold voltage of the erased cell is 1.0 V, and that of the programmed cell is above 5.0 V. The erase mechanism of the cell is Fowler-Nordheim tunneling by applying a high voltage to the erase gate while the source, the drain, and the control gate electrodes are grounded. Since the negative value of the threshold voltage causes an over erase problem in a NOR-type Flash memory, the threshold voltage of erased cells is desirable to be about 1 volt when supply voltage (V DD ) is 3.3 V. The programming mechanism of the cell is channel hot electron injection which is achieved by applying 5.5 V to both the control gate and the drain electrode. The measured results for the erased and programmed cell characteristics are shown in Fig. 2. The erasing time was 1 sec in the experiment. Although the cell was designed to have threshold voltage of 1 V, the threshold voltage of the cell erased by 8 V is about 0.7 V, as shown in Figure 2. When the cell was erased with 8.5 V, it showed a threshold voltage around 0.2 V. So, we could use 8 V as the erase voltage, which is low enough compared to the gate oxide breakdown voltage and the junctions breakdown voltage of the target process. The programmed cell had a threshold voltage of above 5.0 V. The memory window, the threshold voltage difference between the erased and the programmed cell, was about 4.2 V. Figure 3(a) shows the proposed NOR-type memory Fig. 3. (a) Proposed NOR-type cell array. (b) Layout drawing of the cell array with 4 cells, indicated by the dotted box in Figure 3(a). array. For the cell layout to be more efficient, a pair of cells shares erase gate and grounded source electrodes. The layout of the 4 cells indicated by the dotted rectangle is shown in Fig. 3(b). In this cell layout, the size of a unit cell is 62.5 µm 2. The basic block of the memory array is composed of 2 word lines and a common erase gate, as shown in Figure 3(a). The Flash memory macro consists of 16 basic blocks, thus, it has 32 word lines with 8 bits. The memory macro is the minimum repetitive memory unit for a placement of embedded Flash memories. III. DESIGN OF TEST CHIP For a complete design of the Flash memory, peripheral circuits such as address decoders, I/O circuits, high voltage generators etc, and a sense amplifier are needed. We used well-known peripheral circuits for the design of the test chip except for the sense amplifier. The sense amplifier should apply bit line voltages to a selected cell for not only reading but also programming operations. The sense amplifier for the proposed Flash cell is shown in Figure 4. There are three timing control signals, Vpreb, Vsense, and Vrnp, for its operation. Vpreb is a control signal that determines the pre-charging time. The Vsense signal controls the start of the sensing opera-

3 -848- Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002 Table 1. Summary of the operating conditions for the cell. Source Bit-line Control Erase Operation Voltage Voltage Gate Gate Mechanism Voltage Voltage Erase 0 V 0 V 0 V 8 9 V Program 0 V 5.5 V 5.5 V 0 V Read 0 V 1.6 V V DD 0 V Fowler-Nordheim tunneling Channel hot electron injection tion, and Vrnp chooses the bit voltage, whether programming or not, during the programming operation. When reading or programming a cell, node N1 is pre-charged to V DD while node N2 is pre-charged to a level of VppIn. The level of VppIn is 1.6 V in read operations and 5.5 V in program modes. The 5.5 V level of VppIn is supplied by a high voltage generator circuit. For the operation of the read mode, the Vpreb signal goes high level after about a 10-nsec delay from chip enable (CE), and the Vsense signal should reach a high level after predetermined delay of about 5 nsec, then, the voltage of node N1 is determined by whether the cell is erased or programmed. Figure 5 shows the simulated results for the read mode of the test chip. The N-well parasitic capacitance of the control gate and bit line parasitic capacitance that is extracted from the layout was used in the simulations. The simulated CE access time was about 20 nsec. In the programming mode, the Vrnp signal is determined by the input data, which, in turn, decides the level of the bit line signal voltage. We used logic 0 for the programmed cell and logic 1 for the erased cell. The timing diagram of the control signals for the program mode is shown in Figure 6. The operation detail of high voltage generator can be found in reference 7. To verify the operation of the core cell array and the periphery circuits, we fabricated a test chip by using Anam semiconductor s 0.25 µm single poly CMOS process through the IDEC MPW service. The test chip is shown in Fig. 7. Although the test chip was planned to include 18 blocks of a 32 8 macro shown in Fig. 3, Fig. 4. Proposed sense amplifier circuit. Fig. 5. HSPICE simulation results for the read operation. Fig. 6. Measured programming control signal (a) when the input bit is 0 and (b) when the input bit is 1.

4 A Single Poly Flash Memory Intellectual Property for Low-Cost Jai-Cheol Lee et al Fig. 9. Measured CE and data output signal. The CE access time was about 27 nsec. Fig. 7. Test chip for the proposed single poly Flash memory. measured by a digital oscilloscope are shown in Figure 9, which shows that the CE access time is about 27 nsec. The measured results are consistent with the simulated timing diagram shown in Fig. 5, which shows that the sense amplifier works correctly during the programming and the read operations, as we explained in the previous section. V. CONCLUSION Fig. 8. Measured read mode control signal. only two of them were actually integrated into the chip. Since the cell was designed to verify the operation of the Flash cell and peripheral circuits, it was sufficient for our purposes. IV. MEASUREMENT RESULTS AND DISCUSSIONS In order to probe the control signals of the chip, many internal signals are exposed to external pads. Test chips were packaged and tested with logic analyzers and digital oscilloscopes. Major signals in the sense amplifier circuits for the program mode were probed with a logic analyzer. When the input bit is 0, the Vrpn (marked by RPN3) signal is generated at a high level during programming as shown in Figure 6(a). On the other hand, when input bit is 1, the Vrpn signal stays at a low level during programming, as shown in Figure 6(b). Figure 8 shows the measured control signal for the read operation. The chip enable (CE) and the data out (Dout) signals In this paper, we proposed a Flash memory macro that can be integrated into a standard single poly CMOS process without additional masking or processing steps. Although it may not be adequate to integrate a large Flash memory with this cell array because of large cell size, its compatibility with a standard CMOS process makes this approach a good candidate for a small size nonvolatile memory block for a CMOS digital system on a chip. ACKNOWLEDGMENTS The authors thank IDEC(IC Design Education Center) for supporting design tools and MPW (Multi- Project Wafer) service. The test chip was manufactured by Anam Semiconductor through IDEC s MPW service. The first author thanks BK21 (Brain Korea 21) program for the assistance of his sabbatical year. This work was supported by Wonkwang University in REFERENCES

5 -850- Journal of the Korean Physical Society, Vol. 41, No. 6, December 2002 [1] B. Shin, K. Park, J. Kim and J. Choi, J. Korean Phy. Soc. 39, 374 (2001). [2] J. Kim, J. Choi, B. Shin, I. Choi, K. Park and S. Yang, J. Korean Phys. Soc. 39, 1100 (2001). [3] K. Ohsaki, N. Asamoto and S. Takagaki, IEEE J. Solid State Circ. 29, 311 (1994). [4] J. Han, K. Ra, S. Lee, and Young Seok Kim, J. IEEK (in Korean) 33-A, 131 (1996). [5] A. Bergemont, H. Haggag, P. Francis, A. Kalnitsky, L. Chang, C. Kuo and C. Hu, Proceedings of Nonvolatile semiconductor memory workshop-2000 (California, 2000), p. 86. [6] R. McPartland and R. Singh, Tech. Digests of Symposium on VLSI circuits (Hawaii, 2000), p. 75. [7] J. Kim and Shiho Kim, J. Korean Phy. Soc. 41, 468 (2002).