Outline. Definition. Targeted Defects. Motivation GOAL. Ferhani, RATS/SPRING , Center for Reliable Computing 1
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1 RATS (Reliability and Testability Seminar) Diagnosis of Defects Introducing Voltage Dependences between Nodes By François-Fabien Ferhani 5/27/2003 Ferhani, RATS/SPRING03 Outline Introduction Problems & Solutions Implementation & Results Conclusion 5/27/2003 Ferhani, RATS/SPRING03 2 Targeted Defects (Resistive) shorts between 2 signal lines Bridges (Resistive) shorts between a signal line and a power line s Crosstalk? Definition The Failure Trace (FT) of a chip is the list of failing patterns observed on the tester and their corresponding failing pin (also called signature) Failing Pattern Pattern 56 Pattern 89 Pattern 89 Failing Pin Pin 5 Pin 0 Pin 2 5/27/2003 Ferhani, RATS/SPRING03 3 5/27/2003 Ferhani, RATS/SPRING03 4 GOAL Using Failure Trace Fault Free Simulation Fault Simulation No layout information Find the circuit node(s) where the defect is located Collect information about the defect Also called Logic Mapping 5/27/2003 Ferhani, RATS/SPRING03 5 Motivation Yield learning Manufacture many chips (Significant) Portion of failures How to make more good chips? So, collect information about defects Location Behavior s: resistance 5/27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing
2 Motivation Collect information about test sets Which ones detect which defects Outline Introduction Problems & Solutions Implementation & Results Conclusion 5/27/2003 Ferhani, RATS/SPRING03 7 5/27/2003 Ferhani, RATS/SPRING03 8 Diagnosis Methods Stuck-At fault diagnosis [Waicukauski 89] Extensively studied Few defects behave like Stuck- At fault (5% in Elf35) Transition fault diagnosis Diagnosis Methods 2 Bridging Fault Diagnosis IDDQ [Olson 97] Logic Concatenation of stuck-at fault signatures [Millman 90] Stuck-at fault simulation [Wu 2000] 5/27/2003 Ferhani, RATS/SPRING03 9 5/27/2003 Ferhani, RATS/SPRING03 0 Logic Bridging Fault Diagnosis Bridging Fault: between two signal lines If two nodes are shorted their voltages are equal if their fault free values are opposite, one of the nodes will behave like a Stuck At. Logic Bridging Fault Diagnosis First Set of candidates: All nodes pairs Can be reduced Logic simulation [Ferhani 02] For each pair candidate Match fault simulation with failure trace [Wu 2000] Match fault dictionary with failure trace [Millman 90] 5/27/2003 Ferhani, RATS/SPRING03 5/27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 2
3 Problem Problem Different gates have different thresholds Equal or nearly equal voltages on the two bridged nodes can be interpreted differently 5/27/2003 Ferhani, RATS/SPRING03 3 5/27/2003 Ferhani, RATS/SPRING03 4 Problem Problem 2 Different gates have different threshold The same voltage at one node can be interpreted differently by different gates Called Byzantine General Problem [Wu 2000] 5/27/2003 Ferhani, RATS/SPRING03 5 5/27/2003 Ferhani, RATS/SPRING03 6 Problems Come from the fact that different gates have different threshold TSMC.35 simulations show Different gates have different thresholds These Thresholds are very close to each others Values around half the power voltage Solutions. Use only failing vectors [Wu 2000] Doesn t get rid of the problem 2. Reduce matching criteria Failing fault simulation PO intersect with Failure trace PO More candidates left after (lowers Diagnosis resolution 5/27/2003 Ferhani, RATS/SPRING03 7 5/27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 3
4 Solutions Example 3. Compute all the faulty voltages Biased voting model [Maxwell 93] Spice simulation [Rearick 93] Resource consuming Assumes we know the defect Resistance Doesn t affect driving and driven gates 5/27/2003 Ferhani, RATS/SPRING03 9 5/27/2003 Ferhani, RATS/SPRING03 20 Example Stuck At Example Look for driving gate input combination where this problem does not occur One of the two nodes clearly wins the fight Check the coherence with all the cases where the node should dominate 5/27/2003 Ferhani, RATS/SPRING03 2 5/27/2003 Ferhani, RATS/SPRING03 22 Look for failing vectors that match fault simulation No intermediate voltage problem Know when intermediate voltage problems do not occur Can use all the vectors Failing Non-failing Characteristics Use all the vectors Not only non failing Know when to expect exact match Does not assume anything Except that opening an extra pull up/down will raise/lower the voltage Can collect information about the defect: When does one node dominate the other: Wand, Wor 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 4
5 Characteristics Simple No need for computation Might not be enough vectors Even if we use all the test vectors Does not work for feedback shorts Does not take into account previous values Difference from Drive Strength Simple No need for computation Does not assume: Resistance value Perfect gates 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 26 Resistance Value If we assume the defect is just a short Can extract resistance value Outline Introduction Problems & Solutions Implementation & Results Conclusion 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 28 ISCAS 85 C7 Fault Injection Inject 50 Ohms shorts Between 2 nodes Between one node and power rail nodes, 6Gates S@ S@0 55 Bridge Fault 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 5
6 Simulation Apply exhaustive patterns Use SPICE to get failure trace TSMC.35 process Diagnosis Flow Step Pruning Logic Simulation Step 2 Fault Simulation Failing Vectors Only Step 3 Fault Simulation All Vectors 5/27/2003 Ferhani, RATS/SPRING03 3 5/27/2003 Ferhani, RATS/SPRING03 32 Step Step Candidate List Pruning Fault Free Logic Simulation [Ferhani Win02] Stuck-At candidates Nodes having same values for all failing vectors Bridging Pairs of nodes having opposite fault free values ford all failing vectors G6 Vdd G8 G9 G8 G5 G7 G5 G9 G7 G6 G % Reduction G6 G2 G7 G2 G2 G9 G2 Vdd G9 Gnd G9 Vdd % Reduction /27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 34 Step 2 Step 2 Try to match Failure trace with fault simulation For each failing vector: Stuck-at candidate: Simulate faulty value Bridge candidate Simulate one node stuck at, the other, and both Only keep the best match For each candidate Remember for which vectors the failure trace matched exactly fault simulation No intermediate voltage problem G6 Vdd G8 G9 G8 G5 G7 G5 G9 G7 G6 G % Reduction G6 G2 G7 G2 G2 G9 G2 Vdd G9 Gnd G9 Vdd % Reduction /27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 6
7 The equivalence problem behavior is equivalent to G6 Vdd G8 G9 G8 G5 Behaviour Wand 2 PMOS for s@ G6 G2 G7 G2 G2 G9 G7 G5 G2 Vdd S@ G9 G7 G9 Gnd S@0 G6 G8 G9 Vdd S@ 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 38 Step 3 All the gates in the C7 are the same No threshold problem The proposed solution still represents an improvement Can use non failing vectors Better diagnosis resolution Outline Introduction Problems & Solutions Implementation & Results Conclusion 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 40 Resistance Value In the experiment, all resistances are 50 Ohms. Most of the resistance < 00 Ohms [Rodriguez- Montanes 92] Uniformly distributed between 0 and 40k Transition faults There are 3 behaviors of a short depending on the resistance value: Logic failure under a certain value R Timing failure between R and R2 No failure above R2 5/27/2003 Ferhani, RATS/SPRING03 4 5/27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 7
8 Transition Faults Transition Fault 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 44 Conclusion Keeping track of the candidate behavior Eliminates more candidates Collects information about defect Whether there is an intermediate voltage problem or not Research Resistance Value Transition Fault Experiment Implement Step 3 Simulate Elf CUT Elf Diagnosis Future Work 5/27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING03 46 References Waicukauski, Lindbloom Failure Diagnosis of Structures VLSI IEEE Design & Test of Computers, August 989 Pages: Michael Olson, Xiaoling Sun Single Briddging Fault Diagnosis for CMOS Circuit CCECE, 997. Pages: S.D. Millman, E.J. McCluskey, J.M. Acken Diagnosing CMOS bridging faults with stuck-at fault dictionaries IEEE Int. Test Conf. proceedings, 990, Pages: References Jue Wu and Elizabeth M. Rudnick. Bridge Fault Diagnosis Usinf Stuck-At-Fault Simulation IEEE Transactions on CAD of integrated circuits and systems, Vol. 9, No 4, April 2000 Francois-Fabien Ferhani Pruning fault candidates using logic simulation Rel. and Testabil. Seminar, CRC- Stanford University, Winter Peter C. Maxwell, Robert C. Aitken Biased Voting: A Method for Simulating CMOS Bridging Faults in the Presence of Variable Gate Logic Thresholds IEEE Int. Test Conf. proceedings, 993, Pages: /27/2003 Ferhani, RATS/SPRING /27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 8
9 References Jeff Rearick, Janak H. Patel Fast and Accurate CMOS bridging Fault Simualtion IEEE Int. Test Conf. proceedings, 993, Pages: R. Rodriguez-Montanes, E. M. J. G. Bruls, J. Figueras Bridging Defects Resistance Mesaurement in a CMOS Process IEEE Int. Test Conf. proceedings, 992, Pages: /27/2003 Ferhani, RATS/SPRING , Center for Reliable Computing 9
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