Real time implementation on FPGA Summer School EMR 17 - Lille 19 au 21 juin dspace 7 parc Burospace Bièvres FRANCE

Transcription

1

2 Real time implementation on FPGA Summer School EMR 17 - Lille 19 au 21 juin 2017 dspace 7 parc Burospace Bièvres FRANCE

3 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 3 EMR17 Real time implementation on FPGA

4 Agenda FPGA Technologies Unmatched performances Field Programmable Gate Array Routing channels to carry signals from one block to another User-configurable digital logic blocks IO buffers to go to physical world Switching matrices to switch signals All of that in one component! 4 EMR17 Real time simulation on FPGA

5 Agenda FPGA : How does it work? What does it bring? Unmatched performances (Processor : 10 µs, FPGA, 100 ns) Processing trully simultaneous (processor => sequencial processing) Control of real time: latencies known and fixed (processor => load dependant) How does it execute? Programmed logics Execution step managed by FPGA and all the logic executed at one time (not sequential as on a processor) Programming logics (description of hardware functionality with a language) different than on processor Reasons for success FPGA manufacturers (Xilinx, Altera) very active (Xilinx, Altera). Cost, performances Appearance of free development tools Democratization of the VHDL (now well mastered by the developers) Ideal for rapid prototyping and specific circuits in small volumes Sustainability of developments (portability) and ease of maintenance (functional changes = update of the configuration of the component). 5 EMR17 Real time simulation on FPGA

6 Agenda FPGA: key points for real-time control How to connect to the physical world? IO hardware directly accessible from FPGA VHDL framework for optimized management of IO latencies Ready to use IO access control Hardware designed for the lowest IO access latency possible How to build a complete application? Connection between processor and FPGA Synchronization between processor and FPGA (in general, int. generation by the FPGA) Ready to use tools for the FPGA processor communication How to observe and instrument Real time platform with instrumentation like ControlDesk Blocks to exchange data between the processor real time application and the FPGA Instrumentation mecanism on FPGA (Packet record on trig.) 6 EMR17 Real time simulation on FPGA

7 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 7 EMR17 Real time implementation on FPGA

8 Agenda FPGA : Manual programming methods Manual coding With synthetizable description languages (convertible to digital logics) VHDL (IEEE 1076) = VHSIC Hardware Description Language. The more used in Europe In US, VERILOG is prefered by users Code example: if(clock event and clockà 1 ) then y<=a+b; end if Clock A B adder Y 8 EMR17 Real time simulation on FPGA

9 Agenda FPGA : graphical programming methods Modeling and simulation in SIMULINK with XSG/Vivado (Tool suite provided by Xilinx) Usage of specific blocks and related tools Modeling preferably in fix point (Floating point uses large resource) Automatic VHDL code generation (or VERILOG) Manual code can be integrated via «black boxes» Automated integration on dspace platforms with RTIFPGA library. 9 EMR17 Real time simulation on FPGA

10 Agenda FPGA : graphical programming methods Blocks for SIMULINK, provided by Xilinx Modeling, Simulation, and VHDL code generation from block diagram Available block examples Basic blocs Advanced functions Manual code integration «Soft Core» Processor Utility blocks 10 EMR17 Real time simulation on FPGA

11 Agenda FPGA : graphical programming methods «manual» porting of an existing algorithm in Simulink or modeling with XSG from a blank page 11 EMR17 Real time simulation on FPGA

12 Agenda Programming from SimScape PowerSystems TM Circuit diagram Simulink-Model (Block-orientated) SimPowerSystems Model (Topology-orientated): 12 EMR17 Real time simulation on FPGA

13 Agenda Programming from SimScape PowerSystems TM Processor ~25µs IOCNET FPGA ~2.5µs 13 EMR17 Real time simulation on FPGA

14 Agenda FPGA programming on dspace platforms Blockset Provided by dspace (RTIFPGA Blockset) Two parts: Processor Interface & FPGA Interface Processor Interface General purpose configuration «Processor Setup» Read/write on FPGA registers Block for interrupts generated by FPGA FPGA Interface General purpose configuration «FPGA Setup». Read/write Processor registers Generate interrupts for Processor Access to IOs (ADC, Dig In, DAC, Dig out ). 14 EMR17 Real time simulation on FPGA

15 Agenda Generation of two applications: processor and FPGA FPGA model XSG code generator (+ RTIFPGA) Integrated Flash mermory FPGA confi g VHDL Code Application Processor model Separate XSG model» Code generator SL coder, RTI + RTIFPGA 15 EMR17 Real time simulation on FPGA

16 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 16 EMR17 Real time implementation on FPGA

17 FPGA boards within all architectures Modular systems New DS5203 FPGA Kintex 7 (XC7K325 ou XC7K MHz 10 ns) MicroAutoBox II DS1514 with Kintex 7 (XC7K MHz 12,5 ns) MicroLabBox FPGA Kintex 7 (XC7K325) intégrated (100 MHz 10 ns) 100+ Shared IOs between µc and FPGA SCALEXIO DS2655 FPGA Kintex 7 (125 MHz 8 ns) Up to 5 M1/M2 modules 17 EMR17 Real time implementation on FPGA

18 Modular configuration: scalable number of IOs FPGA Base Board optional optic transceiver IO Modules Ready to use ConfigurationDesk functions out of the box User defined mapping between IO function and IO channels DS2655 FPGA base board Support up to 5 DS2655M1/M2 modules Integration in SCALEXIO box or in separate independent box 18 EMR17 Real time implementation on FPGA

19 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 19 EMR17 Real time implementation on FPGA

20 For HIL : batteries simulation EV1077 Solution based on dédicated hardware EV1082 controler board, managed by a PGI1 FPGA module Up to 32 EV1077 cell emulation boards (4 channels per board, 128 cells max.) Connection to HIL simulator HIL via Ethernet Dedicated blockset to access to EV1077 parameters Use of battery models from ASM (dspace ready to use opened model) Initial configuration for customer application done by dspace (service engineering for integration in rack) EV1082 Example of an integrated configuration 20 EMR17 Real time implementation on FPGA

21 Battery emulations with EV1082/EV1077 Cell voltage : 0V 6V 4 wires outputs (Kelvin links) Precision : ±1.5 mv, over all temperature range Refresh frequency > 1kHz (for 128 cellules) Max. current 1A per chanel (produced or absorbed) Current Measurement Galvanic Isolation 21 EMR17 Real time implementation on FPGA

22 For Rapid Control Prototyping : BMS (Battery Management System) Based on PGI1 FPGA module + BMS EV1093 module (24 cells per module) Modular system, supports up to 200 cells Uses the ISL78600 (Intersil) component. Precision of voltage measurement : +-3mV Sampling frequency defined by the user (max. 1 ksps) One temperature measurement available for each cell Possible to synchronize modules aquisitions Several passive cell balancing modes Galvanic isolation 22 EMR17 Real time implementation on FPGA

23 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 23 EMR17 Real time implementation on FPGA

24 Rapid prototyping of a very fast controler (<< 25µs) XSG-ACMC solution for fast implementation of controls on FPGA platform, user programmable Control & supervision («slow part») on processor board Fast control and signal management on FPGA Power management with RapidPro (FOC) 24 EMR17 Real time implementation on FPGA

25 Agenda 1. FPGA Basics 2. FPGA main programming methods 3. FPGA Hardware 4. Cell emulation and BMS 5. Control hardware setup example 6. Conclusion 25 EMR17 Real time implementation on FPGA

26 Conclusion Deterministic operations and very fast Programmable logics, with unmatched capability to execute large number of operations simultaneously Caution for programming Fix point operations with scaling Link with Processor and instrumentation Specialized links for communication between processor and FPGA Required to execute a joint application between Processor and FPGA Very usefull to easily instrument the FPGA application IO access with optimized latency Easy access to IOs is key Minimal and well controled IO access time 26 EMR17 Real time implementation on FPGA

27 Questions? 27 EMR17 Real time implementation on FPGA

28 Merci pour votre attention! 28 EMR17 Real time implementation on FPGA

29