USB Connectors. Optional IOB31 Board. *Assumes Trenton Server-Class system host board. x4 PCIe Link* (Expansion) x8 PCIe. Connector.

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1 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () Technical Information Jumpers and ss BP0 (S0) ServerClass PCI Express Backplane Block Diagram USB s (P & P) Ethernet s (P & P) PICMG. System Host Board BP0 Backplane System Host Board (Edge connectors A, B & C) Optional IOB Board x PCIe Link* (Expansion) x PCIe Link* (A0) *Assumes Trenton ServerClass system host board x PCIe (PCIe) x PCIe (PCIe) Power (P) bit/mhz (A) s (E, E) (F, F) ) PCIe Link (A) PCI Express to Dual bit/00mhz PCIe Link (A) PCI Express to Dual PCIe Link (B0) PCI Express to Dual bit/mhz bit/00mhz (B) s (C, C) (D, D) Layout Diagram S0.*.00 9.*.9..* * * = 0.00 P USB Ports P PCIe PCIe PCIeS A B C C D D E E F F 0.* *.*.9* Notes: *IOB or IOB requiredd to provide PCI Express link to t PCIe slot SHB x mech x elect. x PCIe Link (A0) PCIe Link (B0) x mech x elect. PCIe Link (A) (bit/mhz) PCIe to PCIe to (bit/00mhz) PCIe to P **Optional USB and Ethernet connectivity provided by PICMG. SHB. Not all SHBs support this capability. spacing: 0.00 Nominal PCB thickness:.00 Mounting holes:. diameter s are populated based on model. PCIe Link (A) P0 P 0.00 Some holes are common too both hole patterns Ethernet Ports P P P P. 0. All dimensions are inches.. Chassis Plans Support Center BP0 Technical Information s

2 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S0) Configuration Jumper The setup of the configuration jumper on the backplane is described below. * indicates the default value of the jumper. NOTE: For the twoposition jumper (post), TOP and BOTTOM refer to positioning when the backplane is viewed with the slotss at the top end of the backplane. Jumper JU Description Auxiliary Voltage Install on the TOP if auxiliary voltage is provided by thee standard supply. This option is used for systems which do not have either an AT or EPS standard powerr input. This mode provides the necessary for the SHB s AU signal lines. Sleep mode recovery is not supported using non AT/EPS power supplies. Install on the BOTTOM if auxiliary voltage is provided by a separate AU signal input pin. This enables the necessary SHB power signaling and allows recovery from sleep mode. This option is used for AT or EPS standard power supplies. * BP0 (S000) s The connectors available on the BP0 vary depending on the version of the backplane you have. s for the S000 (EPS) and S000 (CRA) are defined below. NOTE: on the connectors is indicated by the square pad on the PCB. P AT/EPS Power pin dual row header, Molex # V +..V PWRGD AU +..V V V PSON# V Chassis Plans Support Center BP0 Technical Information s

3 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) s (continued) P P P P P Power pin dual row header, Molex #0000 Terminal Block 0 position terminal block, Amp # Amps per circuit 9 0 Terminal Block 0 position terminal block, Amp # Amps per circuit +..V +..V +..V +..V 9 0 PowerOn pin single row header, Amp #0 PSON# Power Button pin single row header, Amp #0 PWRBT# Chassis Plans Support Center BP0 Technical Information s

4 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) CONN NECTORS (CONTINUED) P P9 P0 P P Reset pin single row header, Amp #0 SHB_RST# Power Good pin single row header, Amp #0 PWRGD +..V I/O Power 0 pin dual row header, Molex # IPMB_DA IPMB_CL SMDAT SMCLK PWRBT# PWRGD 0 0 AU +.V PSON# SHB_RST# AU_IN AU_IN V Universal Serial Bus (USB) pin dual row header, Molex #000 ( fused with selfresetting fuses) USB0 USB0 USB0+ USB0 USB USB USB+ USB Universal Serial Bus (USB) pin dual row header, Molex #000 ( fused with selfresetting fuses) USB USB USB+ USB USB USB USB+ USB Chassis Plans Support Center BP0 Technical Information s

5 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) CONN NECTORS (CONTINUED) P P P9 0/00/000BaseT Ethernet LAN 0 pin shielded RJ connector, Molex #0000 TRP+ TRP TRP+ TRP+ TRP TRP TRP+ TRP 0/00/000BaseT Ethernet LAN pin shielded RJ connector, Molex #0000 TRP+ TRP TRP+ TRP+ TRP TRP TRP+ TRP System Management Bus pin single row header, Amp #0 SMB Clock SMB Data BP0 (S000) s NOTE: on the connectors is indicated by the square pad on the PCB. P AT/EPS Power pin right angle dual row mini fit JR, Molex # V +..V PWRGD AU +..V V V PSON# V Chassis Plans Support Center BP0 Technical Information s

6 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) s (continued) P P P P P Power pin right angle mini fit JR, Molex #00 Terminal Block 0 position terminal block, Amp # Amps per circuit 9 0 Terminal Block 0 position terminal block, Amp # Amps per circuit +..V +..V +..V +..V 9 0 PowerOn pin single row header, Amp #0 PSON# Power Button pin single row header, Amp #0 PWRBT# Chassis Plans Support Center BP0 Technical Information s

7 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) s (continued) P P9 P0 P P Reset pin single row header, Amp #0 SHB_RST# Power Good pin single row header, Amp #0 PWRGD +..V I/O Power 0 pin dual row header, Molex # IPMB_DA IPMB_CL SMDAT SMCLK PWRBT# PWRGD 0 0 AU +.V PSON# SHB_RST# AU_IN AU_IN V Universal Serial Bus (USB) pin dual row header, Molex #000 ( fused with selfresetting fuses) USB0 USB0 USB0+ USB0 USB USB USB+ USB Universal Serial Bus (USB) pin dual row header, Molex #000 ( fused with selfresetting fuses) USB USB USB+ USB USB USB USB+ USB Chassis Plans Support Center BP0 Technical Information s

8 0 Carroll Canyon Rd San Diego, CA 9 Phone () 0 Fax () BP0 (S000) s (continued) P P P9 0/00/000BaseT Ethernet LAN 0 pin shielded RJ connector, Molex #0000 TRP+ TRP TRP+ TRP+ TRP TRP TRP+ TRP 0/00/000BaseT Ethernet LAN pin shielded RJ connector, Molex #0000 TRP+ TRP TRP+ TRP+ TRP TRP TRP+ TRP System Management Bus pin single row header, Amp #0 SMB Clock SMB Data Chassis Plans SHB Optional Backplane I/O Support For the BP0 CHASSIS PLANS SHB ETHERNET LAN0 LAN LAN USB0 USB USB USB USB USB USB USB USB NLT/NLI SLT/SLI MCseries n/ /a n/ /a Requires factory build option. LAN is a 0/00/ /000BASET Ethernet interface when usingg a MCseries SHB Note: The letter indicates an interface connection routed to SHB edge connector C for use on the backplane Chassis Plans Support Center BP0 Technical Information s