NuMicro Family Nano100(A) Series Datasheet

Transcription

1 ARM Cortex -M 32-bit Microcontroller NuMicro Family Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. Mar 31, 2015 Page 1 of 95 Revision V1.00

2 Table of Contents 1 GENERAL DESCRIPTION FEATURES Nano100 Features Base Line Nano120 Features USB Connectivity Line PARTS INFORMATION LIST AND PIN CONFIGURATION NuMicro Nano100 Series Selection Code NuMicro Nano100 Products Selection Guide NuMicro Nano100 Base Line Selection Guide NuMicro Nano120 USB Connectivity Line Selection Guide Pin Configuration NuMicro Nano100 Pin Diagram NuMicro Nano120 Pin Diagram Pin Description NuMicro Nano100 Pin Description NuMicro Nano120 Pin Description BLOCK DIAGRAM Nano100 Block Diagram Nano120 Block Diagram FUNCTIONAL DESCRIPTION ARM Cortex -M0 Core Overview Features Memory Organization Overview Memory Map Nested Vectored Interrupt Controller (NVIC) Overview Features System Manager Overview Features Clock Controller Overview Features FLASH Memory Controller (FMC) Overview Features External Bus Interface Overview Features General Purpose Controller Mar 31, 2015 Page 2 of 95 Revision V1.00

3 5.8.1 Overview Features DMA Controller Overview Features Timer Controller Overview Features Pulse Width Modulation (PWM) Overview Features Watchdog Timer Controller Overview Features RTC Overview Features UART Controller Overview Features Smart Card Host Interface (SC) Overview Features I 2 C Overview Features SPI Overview Features I 2 S Overview Features USB Overview Features Analog to Digital Converter (ADC) Overview Features APPLICATION CIRCUIT ELECTRICAL CHARACTERISTIC Absolute Maximum Ratings DC Electrical Characteristics AC Electrical Characteristics Mar 31, 2015 Page 3 of 95 Revision V1.00

4 7.3.1 External Input Clock External 4~24 MHz XTAL Oscillator External khz Crystal Internal 12 MHz Oscillator Internal 10 khz Oscillator Analog Characteristics bit ADC Brown-out Detector Power-On Reset Temperature Sensor Internal Voltage Reference USB PHY Specifications PACKAGE DIMENSIONS (14x14x1.4 mm footprint 2.0 mm) (7x7x1.4 mm footprint 2.0 mm) (7x7x1.4 mm footprint 2.0 mm) QFN33 (5x5x0.8 mm footprint 0.5 mm) REVISION HISTORY Mar 31, 2015 Page 4 of 95 Revision V1.00

5 List of Figures Figure 3-1 NuMicro TM Nano100 Series Selection Code Figure 3-2 NuMicro TM Nano pin Assignment Figure 3-3 NuMicro TM Nano pin Assignment Figure 3-4 NuMicro TM Nano pin Assignment Figure 3-5 NuMicro TM Nano100 QFN 33-pin Assignment Figure 3-6 NuMicro TM Nano pin Assignment Figure 3-7 NuMicro TM Nano pin Assignment Figure 3-8 NuMicro TM Nano pin Assignment Figure 3-9 NuMicro TM Nano120 QFN 33-pin Assignment Figure 4-1 NuMicro TM Nano100 Block Diagram Figure 4-2 NuMicro TM Nano120 Block Diagram Figure 6-1 M0 Functional Block Figure 8-1 Typical Crystal Application Circuit Mar 31, 2015 Page 5 of 95 Revision V1.00

6 List of Tables Table 1-1 Connectivity Support Table... 8 Table 3-1 Nano100 Base Line Selection Table Table 3-2 Nano120 USB Connectivity Line Selection Table Mar 31, 2015 Page 6 of 95 Revision V1.00

7 1 GENERAL DESCRIPTION The Nano100 series ultra-low power 32-bit microcontroller is embedded with ARM Cortex -M0 core operated at a wide voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with 32K/64K-byte embedded Flash and 8K/16K-byte embedded SRAM. Integrating USB 2.0 fullspeed function, RTC, 12-bit SAR ADC, and provides high performance connectivity peripheral interfaces such as UART, SPI, I2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and ISO for Smart card, the Nano100 series supports Brown-Out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. The Nano100 series provides low power voltage, low power consumption, low standby current, high integration peripherals, high-efficiency operation, fast wake-up function and lowest cost 32- bit microcontrollers. The Nano100 series is suitable for a wide range of battery device applications such as: Portable Data Collector Portable Medical Monitor Portable RFID Reader Portable Barcode Scanner Security Alarm System System Supervisors Power Metering USB Accessories Smart Card Reader Wireless Game Control Device IPTV Remote Smart Keyboard Wireless Sensors Node Device (WSN) Wireless RF4CE Remote Control Wireless Audio Wireless Automatic Meter Reader (AMR) Electronic Toll Collection(ETC) The Nano100 Base line, an ultra-low power 32-bit microcontroller with the embedded ARM Cortex -M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with 32K/64K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates RTC, 8- channels 12-bit SAR ADC, and provides high performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 2xISO for Smart card. The Nano100 Base line supports Brown-Out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. The Nano120 USB Connectivity line, an ultra-low power 32-bit microcontroller with the embedded ARM Cortex -M0 core, operates at wide voltage range from 1.8V to 3.6V and runs up to 32 MHz frequency with 32K/64K bytes embedded flash and 8K/16K bytes embedded SRAM. It integrates USB 2.0 full-speed device function, RTC, 8-channels 12-bit SAR ADC, and provides high performance connectivity peripheral interfaces such as 2xUART, 3xSPI, 2xI2C, I2S, GPIOs, EBI (External Bus Interface) for external memory-mapped device access and 2xISO for Smart card. The Nano120 USB Connectivity line supports Brown-Out Detector, Power-down mode with RAM retention and fast wake-up via many peripheral interfaces. Mar 31, 2015 Page 7 of 95 Revision V1.00

8 Product Line UART SPI I2C I2S USB ADC RTC EBI SC Timer Nano100 Nano120 Table 1-1 Connectivity Support Table Mar 31, 2015 Page 8 of 95 Revision V1.00

9 2 FEATURES The equipped features are dependent on the product line and their sub products. 2.1 Nano100 Features Base Line Core Brown-out ARM Cortex -M0 core running up to 32 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Serial Wire Debug supports with 2 watchpoints/4 breakpoints Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory SRAM Memory Runs up to 32 MHz with zero wait state for discontinuous address read access 64K/32K bytes application program memory (APROM) 4 KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on-chip Flash EPROM 16K/8K bytes embedded SRAM Supports DMA mode DMA: Supports 5 channels: one VDMA channel and 4 PDMA channels VDMA Memory-to-memory transfer Supports block transfer with stride Supports word/half-word/byte boundary address Supports address direction: increment and decrement PDMA Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer Supports word boundary address Supports word alignment transfer length in memory-to-memory mode Supports word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Supports word/half-word/byte transfer data width from/to peripheral Supports address direction: increment, fixed, and wrap around Mar 31, 2015 Page 9 of 95 Revision V1.00

10 Clock Control Flexible selection for different applications Built-in 12 MHz OSC (Trimmed to 1%) for system operation, and low power 10 khz OSC for watchdog and wake-up idle operation Low power 10 khz OSC for watchdog and low power system operation Supports one PLL, up to 96 MHz, for high performance system operation (32 MHz) and USB application (48 MHz). GPIO Timer External 4~24 MHz crystal input for precise timing operation External khz crystal input for RTC function and low power system operation Three modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger pin configured as interrupt source with edge/level setting Supports High Driver and High Sink mode Supports input 5V tolerance (except ADC shared pins PC.6 and PC.7) Supports 4 sets of 32-bit timers, each with 24-bit up-counting timer and one 8-bit pre-scale counter Independent Clock Source for each timer Provides one-shot, output toggle and periodic operation modes Internal trigger event to ADC module Supports PDMA mode Timer can wake system up from power down or idle mode Watchdog Timer RTC Clock Source from LIRC (Internal 10 khz Low Speed Oscillator Clock) Selectable time out period from 1.6 ms ~ 26 sec (depending on clock source) Interrupt or reset selectable when watchdog time-out Wake system up from Power-down or Idle mode Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Mar 31, 2015 Page 10 of 95 Revision V1.00

11 Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second PWM/Capture UART SPI Wake system up from Power-down or Idle mode Supports 80 bytes spare registers and a snoop pin to clear the content of these spare registers Supports 2 PWM modules, each has two 16-bit PWM generators Provides eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-zone generator for complementary paired PWM Up to eight 16-bit digital Capture timers (shared with PWM timers), and provides eight capture inputs (rising, falling, or both) Supports One-shot and Continuous mode Supports Capture interrupt Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS bit mode and direction control. Programmable baud rate generator Supports PDMA mode Wake system up from Power-down or Idle mode Up to three sets of SPI controller Master up to 16 MHz, and Slave up to 6 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when SPI controller is used as the master, and 1 slave/device select line when SPI controller is used as the slave Supports byte suspend mode in 32-bit transmission Supports two channel PDMA requests, one for transmit and another for receive Supports three wire mode, no slave select signal, bi-direction interface Wake system up from Power-down or Idle mode Mar 31, 2015 Page 11 of 95 Revision V1.00

12 I2C I2S ADC Up to two sets of I2C device Master/Slave up to 1 Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows Programmable clocks allowing for versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) Interface with external audio CODEC Operated as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I2S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 12-bit SAR ADC Up to 8-ch single-ended input from external pin One internal channel from AVDD, AVSS, Temp sensor, and internal reference voltage Supports Single Scan, Single Cycle Scan, and Continuous Scan mode Each channel with individual result register Only scan on enabled channels Threshold voltage detection (comparator function) Conversion started by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TRM0_CH0, TMR0_CH1, TMR1_CH0 Mar 31, 2015 Page 12 of 95 Revision V1.00

13 SmartCard (SC) and TMR1_CH1) to enable ADC Compliant to ISO T=0, T=1 Supports up to two ISO ports Separates receive/transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 267 ETU) A 24-bit and two 8 bit time out counters for Answer to Request (ATR) and waiting times processing Supports auto inverse convention function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detect the card is removal EBI (External bus interface) support Accessible space: 64 KB in 8-bit mode or 128 KB in 16-bit mode Supports 8bit/16bit data width Supports byte write in 16-bit Data Width mode One built-in temperature sensor with 1 resolution 96-bit unique ID Operating Temperature: -40 ~85 Packages: All Green package (RoHS) 100-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 33-pin(5x5) Mar 31, 2015 Page 13 of 95 Revision V1.00

14 2.2 Nano120 Features USB Connectivity Line Core ARM Cortex -M0 core running up to 32 MHz One 24-bit system timer Supports Low Power Sleep mode Single-cycle 32-bit hardware multiplier NVIC for the 32 interrupt inputs, each with 4-levels of priority Brown-out Serial Wire Debug supports with 2 watchpoints/4 breakpoints Built-in 2.5V/2.0V/1.7V BOD for wide operating voltage range operation Flash EPROM Memory Runs up to 32 MHz with zero wait state for discontinuous address read access. 64K/32K bytes application program memory (APROM) 4KB in system programming (ISP) loader program memory (LDROM) Programmable data flash start address and memory size with 512 bytes page erase unit In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM SRAM Memory 16K/8K bytes embedded SRAM Support PDMA mode DMA: Support 5 channels: one VDMA channel and 4 PDMA channels VDMA Memory-to-memory transfer Support block transfer with stride Support word/half-word/byte boundary address Support address direction: increment and decrement PDMA Clock Control Peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfer Support word boundary address Support word alignment transfer length in memory-to-memory mode Support word/half-word/byte alignment transfer length in peripheral-tomemory and memory-to-peripheral mode Support word/half-word/byte transfer data width from/to peripheral Support address: increment, fixed, and wrap around Flexible selection for different applications Mar 31, 2015 Page 14 of 95 Revision V1.00

15 Built-in 12MHz OSC (Trimmed to 1%) for system operation, and low power 10 khz OSC for watchdog and wake-up operation GPIO Timer Low power 10 khz OSC for watchdog and low power system operation Support one PLL, up to 96 MHz, for high performance system operation (32MHz) and USB application (48MHz). External 4~24 MHz crystal input for precise timing operation External khz crystal input for RTC function and low power system operation Three modes: Push-Pull output Open-Drain output Input only with high impendence All inputs with Schmitt trigger pin can be configured as interrupt source with edge/level setting High driver and high sink IO mode support Support input 5V tolerance (except ADC shared pins PC.6 and PC.7) Support 4 sets of 32-bit timers, each with 24-bit up-timer and one 8-bit pre-scale counter Independent Clock Source for each timer Provides one-shot, output toggle and periodic operation modes Internal trigger event to ADC module Support PDMA mode Wake system up from Power-down or Idle mode Watchdog Timer RTC Clock Source from LIRC. (Internal 10 khz Low Speed Oscillator Clock) Selectable time out period from 1.6 ms ~ 26 sec (depending on clock source) Interrupt or reset selectable on watchdog time-out Wake system up from Power-down or Idle mode Supports software compensation by setting frequency compensate register (FCR) Supports RTC counter (second, minute, hour) and calendar counter (day, month, year) Supports Alarm registers (second, minute, hour, day, month, year) Selectable 12-hour or 24-hour mode Automatic leap year recognition Supports periodic time tick interrupt with 8 periodic options 1/128, 1/64, 1/32, Mar 31, 2015 Page 15 of 95 Revision V1.00

16 PWM/Capture UART SPI 1/16, 1/8, 1/4, 1/2 and 1 second Wake system up from Power-down or Idle mode Support 80 bytes spare registers and a snoop pin to clear the content of these spare registers Support 2 PWM module, each has two 16-bit PWM generators Provide eight PWM outputs or four complementary paired PWM outputs Each PWM generator equipped with one clock divider, one 8-bit prescaler, two clock selectors, and one Dead-Zone generator for complementary paired PWM Up to eight 16-bit digital Capture timers (shared with PWM timers) provide eight rising/falling capture inputs Support one shot and continuous mode Support Capture interrupt Up to two 16-byte FIFO UART controllers UART ports with flow control (TX, RX, CTSn and RTSn) Supports IrDA (SIR) function Supports LIN function Supports RS bit mode and direction control. (Low Density Only) Programmable baud rate generator Supports PDMA mode Wake system up from Power-down or Idle mode Up to three sets of SPI controller Master up to 16 MHz, and Slave up to 6 MHz Supports SPI/MICROWIRE Master/Slave mode Full duplex synchronous serial data transfer Variable length of transfer data from 4 to 32 bits MSB or LSB first data transfer RX and TX on both rising or falling edge of serial clock independently Two slave/device select lines when SPI controller is as the master, and 1 slave/device select line when SPI controller is as the slave I2C Supports byte suspend mode in 32-bit transmission Supports two channel PDMA requests, one for transmit and another for receive Supports three wire, no slave select signal, bi-direction interface Wake system up from Power-down or Idle mode Up to two sets of I2C device Mar 31, 2015 Page 16 of 95 Revision V1.00

17 I2S ADC Master/Slave up to 1Mbit/s Bi-directional data transfer between masters and slaves Multi-master bus (no central master) Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus Serial clock synchronization used as a handshake mechanism to suspend and resume serial transfer Built-in 14-bit time-out counter requesting the I2C interrupt if the I2C bus hangs up and timer-out counter overflows Programmable clocks allow versatile rate control Supports 7-bit addressing mode Supports multiple address recognition (four slave addresses with mask option) Interface with external audio CODEC Operated as either Master or Slave mode Capable of handling 8, 16, 24 and 32 bit word sizes Supports Mono and stereo audio data Supports I2S and MSB justified data format Provides two 8 word FIFO data buffers: one for transmitting and the other for receiving Generates interrupt requests when buffer levels cross a programmable boundary Supports two PDMA requests: one for transmitting and the other for receiving 12-bit SAR ADC with 800K SPS Up to 8-ch single-end input from external pin. One internal channel from AVDD, AVSS, Temp sensor, and internal reference voltage. Supports single scan, single cycle scan, and continuous scan modes Each channel with individual result register Only scan on enabled channels Threshold voltage detection (comparator function) Conversion start by software programming or external input Supports PDMA mode Supports up to four timer time-out events (TMR0, TMR1, TMR2, TMR3) to enable ADC SmartCard (SC) Mar 31, 2015 Page 17 of 95 Revision V1.00

18 Compliant to ISO T=0, T=1 Supports up to two ISO ports Separates receive / transmit 4 bytes entry FIFO for data payloads Programmable transmission clock frequency Programmable receiver buffer trigger level Programmable guard time selection (11 ETU ~ 267 ETU) A 24-bit and two 8 bit time out counter for Answer to Request (ATR) and waiting times processing Supports auto inverse convention function Supports transmitter and receiver error retry and error limit function Supports hardware activation sequence process Supports hardware warm reset sequence process Supports hardware deactivation sequence process Supports hardware auto deactivation sequence when detect the card is removal USB 2.0 Full-Speed Device One set of USB 2.0 FS Device 12Mbps On-chip USB Transceiver Provides 1 interrupt source with 4 interrupt events Supports Control, Bulk In/Out, Interrupt and Isochronous transfers Auto suspend function when no bus signaling for 3 ms Provide 6 programmable endpoints Include 512 Bytes internal SRAM as USB buffer Provide remote wake-up capability One built-in temperature sensor with 1 resolution 96-bit unique ID Operating Temperature: -40 ~85 Packages: All Green package (RoHS) 100-pin(14x14) / 64-pin(7x7) / 48-pin(7x7) / QFN 33-pin(5x5) Mar 31, 2015 Page 18 of 95 Revision V1.00

19 3 PARTS INFORMATION LIST AND PIN CONFIGURATION 3.1 NuMicro Nano100 Series Selection Code Figure 3-1 NuMicro TM Nano100 Series Selection Code Mar 31, 2015 Page 19 of 95 Revision V1.00

20 3.2 NuMicro Nano100 Products Selection Guide NuMicro Nano100 Base Line Selection Guide Part No. Flash (Kbytes) SRAM (Kbytes) NANO100ZC2AN 32K 8K Configurable 4K up to V - V 4 - V QFN33 NANO100ZD2AN 64K 8K Configurable 4K up to V - V 4 - V QFN33 NANO100ZD3AN 64K 16K Configurable 4K up to V - V 4 - V QFN33 NANO100LC2AN 32K 8K Configurable 4K up to V - V 4 2 V 48 NANO100LD2AN 64K 8K Configurable 4K up to V - V 4 2 V 48 NANO100LD3AN 64K 16K Configurable 4K up to V - V 4 2 V 48 NANO100SD2AN 64K 8K Configurable 4K up to V V V 4 2 V 64* NANO100SD3AN 64K 16K Configurable 4K up to V V V 4 2 V 64* QFN33: 5x5mm ; 48: 7x7mm ; 64*: 7x7mm ISP Timer Connectivity IRC 12-bit ISO- Data Flash ROM I 2 S PWM RTC EBI 10KHz PDMA (32-bit) UART SPI I 2 ADC (Kbytes) C USB 12MHz Table 3-1 Nano100 Base Line Selection Table NuMicro Nano120 USB Connectivity Line Selection Guide ICP ISP IAP Package Part No. Flash (Kbytes) SRAM (Kbytes) Data Flash ISP ROM (Kbytes) Timer (32-bit) Connectivity UART SPI I 2 C USB NANO120ZC2AN 32K 8K Configurable 4K up to V 4 2 V QFN33 NANO120ZD2AN 64K 8K Configurable 4K up to V 4 2 V QFN33 NANO120ZD3AN 64K 16K Configurable 4K up to V 4 2 V QFN33 NANO120LC2AN 32K 8K Configurable 4K up to V - V 4 2 V 48 NANO120LD2AN 64K 8K Configurable 4K up to V - V 4 2 V 48 NANO120LD3AN 64K 16K Configurable 4K up to V - V 4 2 V 48 NANO120SD2AN 64K 8K Configurable 4K up to V V V 4 2 V 64* NANO120SD3AN 64K 16K Configurable 4K up to V V V 4 2 V 64* I 2 S PWM 12-bit ADC RTC EBI IRC 10KHz 12MHz PDMA ISO ICP ISP IAP Package QFN33: 5x5mm ; 48: 7x7mm ; 64*: 7x7mm Table 3-2 Nano120 USB Connectivity Line Selection Table Mar 31, 2015 Page 20 of 95 Revision V1.00

21 3.3 Pin Configuration NuMicro Nano100 Pin Diagram NuMicro Nano pin PA.5 PA.6 PA.7 PD.5 PC.7 PC.6 PC.15 PC.14 PB.15 XT1_Out XT1_In /RESET PB.8 PE.15 PE.14 PE.13 PB.14 PB.13 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PD.8 PD.9 PD.10 PD.11 PD.12 PD.13 PB.4 PB.5 PB.6 PB.7 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS VSS VDD ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 PC.12 PC.13 PE.0 PE.1 PE.2 PE.3 PE.4 AVDD PC.0 PC.1 PC.2 PC PC.5 PD.15 PD.14 PD PD PB PB PB PB.0 VSS PE.7 VDD PE PE PE.10 PVSS PB PB PB.11 Vref PE PE.6 PD PD PD PD PD.4 PC.4 NANO pin PF.4 PF.5 PE.11 PE.12 Figure 3-2 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 21 of 95 Revision V1.00

22 NuMicro Nano pin PA.5 PA.6 PA.7 AVDD PC.7 PC.6 PC.15 PC.14 PB.15 XT1_Out XT1_In /RESET PB.8 PB.14 PB.13 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PB.4 PB.5 PB.6 PB.7 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC PB.9 PB.10 PB.11 PE.5 PC PC PC.2 PC.3 PD.15 PD VSS VDD PVSS NANO pin PD.7 PD.6 PB.3 PB.2 PB.1 PB.0 Figure 3-3 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 22 of 95 Revision V1.00

23 NuMicro Nano pin PA.5 PA.6 PA.7 PC.7 PC.6 PB.15 XT1_Out XT1_In /RESET PB.8 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PB.4 PB.5 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA PB PB PB.11 AVDD PE PB PB.2 PVSS NANO pin PC.0 PC.1 PC.2 PC.3 PB.1 PB.0 Figure 3-4 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 23 of 95 Revision V1.00

24 NuMicro Nano100 QFN 33-pin PA.5 AVDD PC.6 PB.15 XT1_OUT XT1_IN /RESET X32O X32I PA.11 PA.10 LDO VDD VSS PA.4 PA.3 ICE_CK/PF.1 ICE_DAT/PF.0 PA.14 PA VSS PC.0 PC.1 PC.2 PC.3 PB.3 PB.2 PB.1 PB.0 PA.9 PA PA.2 PA NANO100 QFN 33-pin Figure 3-5 NuMicro TM Nano100 QFN 33-pin Assignment Mar 31, 2015 Page 24 of 95 Revision V1.00

25 3.3.2 NuMicro Nano120 Pin Diagram NuMicro Nano pin PA.5 PA.6 PA.7 PD.5 PC.7 PC.6 PC.15 PC.14 PB.15 XT1_Out XT1_In /RESET VSS VDD PF.4 PF.5 PVSS PB.8 PE.15 PE.14 PE.13 PB.14 PB.13 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PD.8 PD.9 PD.10 PD.11 PD.12 PD.13 PB.4 PB.5 PB.6 PB.7 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS VSS VDD ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC.11 PC.12 PC.13 PE.0 PE.1 PE.2 PE.3 PE.4 AVDD PC.0 PC.1 PC.2 PC PC.5 PD.15 PD.14 PD PD PB PB PB PB PB PB PB.11 Vref PE PE.6 PD PD PD PD PD.4 PC.4 Nano pin USB_DP USB_DM VDD33 VBUS PE.7 PE.8 Figure 3-6 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 25 of 95 Revision V1.00

26 NuMicro Nano pin PA.5 PA.6 PA.7 AVDD PC.7 PC.6 PC.15 PC.14 PB.15 XT1_Out XT1_In /RESET PB.8 PB.14 PB.13 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PB.4 PB.5 PB.6 PB.7 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA.15 PC.8 PC.9 PC.10 PC PB.9 PB.10 PB.11 PE.5 PC PC PC.2 PC.3 PB.3 PB VSS VDD PVSS NANO pin PB.1 PB.0 D+ D- VDD33 VBUS Figure 3-7 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 26 of 95 Revision V1.00

27 NuMicro Nano pin PA.5 PA.6 PA.7 AVDD PC.7 PC.6 PB.15 XT1_Out XT1_In /RESET PVSS PB.8 PB.12 X32O X32I PA.11 PA.10 PA.9 PA.8 PB.4 PB.5 LDO VDD VSS PA.4 PA.3 PA.2 PA.1 PA.0 AVSS ICE_CK/PF.1 ICE_DAT/PF.0 PA.12 PA.13 PA.14 PA NANO pin PC.0 PC.1 PC.2 PC.3 PB.3 PB.2 PB.1 PB.0 D+ D- VDD33 VBUS Figure 3-8 NuMicro TM Nano pin Assignment Mar 31, 2015 Page 27 of 95 Revision V1.00

28 NuMicro Nano120 QFN 33-pin PA.5 AVDD PC.6 PB.15 XT1_OUT XT1_IN /RESET PVSS PA.11 PA.10 PA.9 LDO VDD VSS PA.4 PA.3 ICE_CK/PF.1 ICE_DAT/PF.0 PA.14 PA VSS PC.0 PC.1 PC.2 PC.3 D+ D- VDD33 VBUS PA.8 PB PA.2 PA NANO120 QFN 33-pin Figure 3-9 NuMicro TM Nano120 QFN 33-pin Assignment Mar 31, 2015 Page 28 of 95 Revision V1.00

29 3.4 Pin Description NuMicro Nano100 Pin Description Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description 1 PE.15 2 PE.14 3 PE.13 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. 4 1 PB.14 User program must enable pull-up resistor in 48 package. SPISS21 O SPI2 2nd slave select pin nint0 I External interrupt0 input pin 5 2 PB.13 User program must enable pull-up resistor in 48 package. AD1 EBI Address/Data bus bit1 PB AD0 EBI Address/Data bus bit0 CLKO O Frequency Divider output pin X32O O External khz crystal output pin X32I I External khz crystal input pin PA.11 I2C1SCK I2C1 clock pin nrd O EBI read enable output pin SC0RST O SmartCard0 RST pin MOSI20 SPI2 1st MOSI (Master Out, Slave In) pin PA.10 I2C1SDA I2C1 data pin nwr O EBI write enable output pin SC0PWR O SmartCard0 Power pin MISO20 SPI2 1st MISO (Master In, Slave Out) pin PA.9 Mar 31, 2015 Page 29 of 95 Revision V1.00

30 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description I2C0SCL I2C0 clock pin SC0DAT SmartCard0 DATA pin SPICLK2 O SPI2 serial clock pin PA I2C0SDA I2C0 data pin SC0CLK O SmartCard0 clock pin SPISS20 O SPI2 1st slave select pin 13 PD.8 14 PD.9 15 PD PD PD PD.13 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package PB.4 RX1 I UART1 Data receiver input pin SC0CD I SmartCard0 card detect pin SPISS20 O SPI2 1st slave select pin PB TX1 O UART1 Data transmitter output pin SPICLK2 O SPI2 serial clock pin PB.6 User program must enable pull-up resistor in 48 package RTSn1 O UART1 Request to Send output pin ALE O EBI address latch enable output pin MISO20 SPI2 2nd MISO (Master In, Slave Out) pin Mar 31, 2015 Page 30 of 95 Revision V1.00

31 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description PB.7 User program must enable pull-up resistor in 64 and 48 package CTSn1 I UART1 Clear to Send input pin ncs O EBI chip select enable output pin MOSI20 SPI2 1st MOSI (Master Out, Slave In) pin LDO P LDO output pin VDD P Power supply for ports and LDO source VSS P Ground 26 PE PE PE PE.9 30 PE.8 31 PE.7 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. PB RX0 I UART0 Data receiver input pin MOSI10 SPI1 1st MOSI (Master Out, Slave In) pin PB TX0 O UART0 Data transmitter output pin MISO10 SPI1 1st MISO (Master In, Slave Out) pin PB RTSn0 O UART0 Request to Send output pin nwrl O EBI low byte write enable output pin SPICLK1 O SPI1 serial clock pin PB.3 Mar 31, 2015 Page 31 of 95 Revision V1.00

32 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description CTSn0 I UART0 Clear to Send input pin nwrh O EBI high byte write enable output pin SPISS10 O SPI1 1st slave select pin PD PD PD PD.15 User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. 40 PC.5 User program must enable pull-up resistor in 64 and 48 package. MOSI01 O SPI0 2nd MOSI (Master Out, Slave In) pin 41 PC.4 User program must enable pull-up resistor in 64 and 48 package. MISO01 I SPI0 2nd MISO (Master In, Slave Out) pin PC MOSI00 O SPI0 1st MOSI (Master Out, Slave In) pin I2SDO O I2S data output SC1RST O SmartCard1 RST pin PC MISO00 I SPI0 1st MISO (Master In, Slave Out) pin I2SDI I I2S data input SC1PWR O SmartCard1 PWR pin PC SPICLK0 SPI0 serial clock pin I2SBCLK I2S bit clock pin SC1DAT SmartCard1 DATA pin PC.0 SPISS00 SPI0 1st slave select pin Mar 31, 2015 Page 32 of 95 Revision V1.00

33 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description I2SLRCLK I2S left right channel clock SC1CLK O SmartCard1 clock pin 46 PE.6 User program must enable pull-up resistor in 64 and 48 package PE.5 PWM1CH1 PWM1 Channel1 output PB.11 PWM1CH0 PWM1 Channel0 output TMR3 O Timer3 external counter input MISO00 SPI0 1st MISO (Master In, Slave Out) pin PB SPISS01 SPI0 2nd slave select pin TMR2 O Timer2 external counter input MOSI00 SPI0 1st MOSI (Master Out, Slave In) pin PB SPISS11 SPI1 2nd slave select pin TMR1 O Timer1 external counter input nint0 I External interrupt0 input pin 51 PE.4 User program must enable pull-up resistor in 64 and 48 package. MOSI00 SPI0 1st MOSI (Master Out, Slave In) pin 52 PE.3 User program must enable pull-up resistor in 64 and 48 package. MISO00 SPI0 1st MISO (Master In, Slave Out) pin 53 PE.2 User program must enable pull-up resistor in 64 and 48 package. SPICLK0 O SPI0 serial clock pin 54 PE.1 PWM1CH3 PWM1 Channel3 output User program must enable pull-up resistor in 64 and 48 package. SPISS00 O SPI0 1st slave select pin Mar 31, 2015 Page 33 of 95 Revision V1.00

34 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description 55 PE.0 PWM1CH2 PWM1 Channel2 output User program must enable pull-up resistor in 64 and 48 package. I2SMCLK O I2S master clock output pin PC.13 User program must enable pull-up resistor in 64 and 48 package. MOSI11 O SPI1 2nd MOSI (Master Out, Slave In) pin 56 PWM1CH! O PWM1 Channel1 output SNOOPER I Snooper pin nint0 I External interrupt 0 I2C0SCK O I2C0 clock pin PC.12 User program must enable pull-up resistor in 64 and 48 package. 57 MISO11 I SPI1 2nd MISO (Master In, Slave Out) pin PWM1CH0 O PWM1 Channel0 output nint0 I External interrupt0 input pin I2C0SDA I2C0 data pin PC.11 User program must enable pull-up resistor in 48 package. MOSI10 O SPI1 1st MOSI (Master Out, Slave In) pin TX1 O UART1 Data transmitter output pin PC.10 User program must enable pull-up resistor in 48 package. MISO10 I SPI1 1st MISO (Master In, Slave Out) pin RX1 I UART1 Data receiver input pin PC.9 SPICLK1 SPI1 serial clock pin User program must enable pull-up resistor in 48 package. I2C1SCK I2C1 clock pin PC.8 User program must enable pull-up resistor in 48 package. Mar 31, 2015 Page 34 of 95 Revision V1.00

35 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description SPISS10 SPI1 1st slave select pin MCLK O EBI external clock output pin I2C1SDA I2C1 data pin PA.15 PWM0CH3 PWM0 Channel3 output I2SMCLK O I2S master clock output pin TC3 I Timer3 capture input TX0 O UART0 Data transmitter output pin PA.14 PWM0CH2 PWM0 Channel2 output AD15 EBI Address/Data bus bit15 TC2 I Timer 2 capture input RX0 I UART0 Data receiver input pin PA.13 PWM0CH1 PWM0 Channel1 output AD14 EBI Address/Data bus bit14 TC1 I Timer1 capture input I2C0SCK I2C0 clock pin PA.12 PWM0CH0 PWM0 Channel0 output AD13 EBI Address/Data bus bit13 TC0 I Timer 0 capture input I2C0SDA I2C0 data pin ICE_DAT Serial Wired Debugger Data pin PF.0 nint0 I External interrupt0 input pin ICE_CK I Serial Wired Debugger Clock pin PF.1 CLKO O Frequency Divider output pin nint1 I External interrupt1 input pin 68 VDD P Power supply for ports and LDO source for internal PLL and digital circuit VSS P Ground Mar 31, 2015 Page 35 of 95 Revision V1.00

36 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description AVSS AP Ground Pin for analog circuit PA.0 ADC0 AI ADC analog input0 PA ADC1 AI ADC analog input1 AD12 EBI Address/Data bus bit12 PA ADC2 AI ADC analog input2 AD11 EBI Address/Data bus bit11 RX1 I UART1 Data receiver input pin PA ADC3 AI ADC analog input3 AD10 EBI Address/Data bus bit10 TX1 O UART1 Data transmitter output pin PA ADC4 AI ADC analog input4 AD9 EBI Address/Data bus bit9 I2C0SDA I2C0 data pin PA ADC5 AI ADC analog input5 AD8 EBI Address/Data bus bit8 I2C0SCK I2C0 clock pin PA.6 ADC6 AI ADC analog input AD7 EBI Address/Data bus bit7 TC3 I Timer3 capture input PWM0CH3 O PWM0 Channel3 output PA.7 ADC7 AI ADC analog input AD6 EBI Address/Data bus bit6 TC2 I Timer2 capture input PWM0CH2 O PWM0 Channel2 output Mar 31, 2015 Page 36 of 95 Revision V1.00

37 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description 79 Vref AP Voltage reference input for ADC AVDD AP Power supply for internal analog circuit PD.0 User program must enable pull-up resistor in 64 and 48 package. 81 RX1 I UART1 Data receiver input pin SPISS20 SPI2 2nd slave select pin SC1CLK O SmartCard1 clock pin PD.1 User program must enable pull-up resistor in 64 and 48 package. 82 TX1 O UART1 Data transmitter output pin SPICLK2 SPI2 serial clock pin SC1DAT SmartCard1 DATA pin. PD.2 User program must enable pull-up resistor in 64 and 48 package. 83 RTSn1 O UART1 Request to Send output pin I2SLRCLK I2S left right channel clock MISO20 I SPI2 1st MISO (Master In, Slave Out) pin SC1PWR O SmartCard1 Power pin PD.3 User program must enable pull-up resistor in 64 and 48 package. 84 CTSn1 I UART1 Clear to Send input pin I2SBCLK I2S bit clock pin MOSI20 O SPI2 1st MOSI (Master Out, Slave In) pin SC1RST O SmartCard1 RST pin PD.4 User program must enable pull-up resistor in 64 and 48 package. 85 I2SDI I I2S data input MISO21 I SPI2 2nd MISO (Master In, Slave Out) pin SC1CD I SmartCard1 card detect 86 PD.5 User program must enable pull-up resistor in 64 and 48 package. Mar 31, 2015 Page 37 of 95 Revision V1.00

38 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description I2SDO O I2S data output MOSI21 O SPI2 2nd MOSI (Master Out, Slave In) pin PC AD5 EBI Address/Data bus bit5 TC1 I Timer1 capture input PWM0CH1 O PWM1 Channel1 output PC.6 AD4 EBI Address/Data bus bit TC0 I Timer 0 capture input SC1CD I SmartCard1 card detect pin PWM0CH0 O PWM0 Channel0 output PC.15 User program must enable pull-up resistor in 48 package AD3 EBI Address/Data bus bit3 TC0 I Timer0 capture input PWM1CH2 O PWM1 Channel1 output PC.14 User program must enable pull-up resistor in 64 and 48 package. AD2 EBI Address/Data bus bit2 PWM1CH3 PWM1 Channel3 output PB.15 nint1 I External interrupt1 input pin SNOOPER I Snooper pin XT1_OUT O External 4~24 MHz crystal output pin XT1_IN I External 4~24 MHz crystal input pin nreset I External reset input: Low active, set this pin low reset chip to initial state. With internal pull-up VSS P Ground VDD P 97 PF.4 Power supply for ports and LDO source for internal PLL and digital circuit User program must enable pull-up resistor in 64 and 48 package. Mar 31, 2015 Page 38 of 95 Revision V1.00

39 Pin No. 100-pin 64-pin 48-pin QFN 33-pin Pin Name Type Description I2C0SDA I2C0 data pin 98 PF.5 User program must enable pull-up resistor in 64 and 48 package. I2C0SCK I2C0 clock pin PVSS P PLL Ground PB ADCTRG I ADC external trigger input. TMR0 I Timer0 external counter input nint0 I External interrupt0 input pin Note: Pin Type: I = Digital Input; O = Digital Output; AI = Analog Input; AO = Analog Output; P = Power Pin; AP = Analog Power Mar 31, 2015 Page 39 of 95 Revision V1.00

40 3.4.2 NuMicro Nano120 Pin Description Pin No QFN 33 Pin Name Pin Type Description 1 PE.15 2 PE.14 3 PE.13 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. 4 1 PB.14 User program must enable pull-up resistor in 48 package. nint0 I External interrupt0 input pin SPISS21 O SPI2 2nd slave select pin 5 2 PB.13 User program must enable pull-up resistor in 48 package. AD1 EBI Address/Data bus bit1 PB AD0 EBI Address/Data bus bit0 CLKO O Frequency Divider output pin X32O O External khz crystal output pin X32I I External khz crystal input pin PA.11 I2C1SCK I2C1 clock pin nrd O EBI read enable output pin SC0RST O SmartCard0 RST pin MOSI20 SPI2 1st MOSI (Master Out, Slave In) pin PA.10 2 I2C1SDA I2C1 data pin nwr O EBI write enable output pin SC0PWR O SmartCard0 Power pin MISO20 SPI2 1st MISO (Master In, Slave Out) pin PA.9 I2C0SCL I2C0 clock pin Mar 31, 2015 Page 40 of 95 Revision V1.00

41 Pin No QFN 33 Pin Name Pin Type Description SC0DAT SmartCard0 DATA pin SPICLK2 O SPI2 serial clock pin PA I2C0SDA I2C0 data pin SC0CLK O SmartCard0 clock pin SPISS20 O SPI2 1st slave select pin 13 PD.8 14 PD.9 15 PD PD PD PD.13 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package. PB RX1 I UART1 Data receiver input pin SC0CD I SmartCard0 card detect pin SPISS20 O SPI2 1st slave select pin PB TX1 O UART1 Data transmitter output pin SPICLK2 O SPI2 serial clock pin PB.6 User program must enable pull-up resistor in 48 package RTSn1 O UART1 Request to Send output pin ALE O EBI address latch enable output pin MISO20 SPI2 2nd MISO (Master In, Slave Out) pin Mar 31, 2015 Page 41 of 95 Revision V1.00

42 Pin No QFN 33 Pin Name Pin Type Description PB.7 User program must enable pull-up resistor in 48 package CTSn1 I UART1 Clear to Send input pin ncs O EBI chip select enable output pin MOSI20 SPI2 1st MOSI (Master Out, Slave In) pin LDO P LDO output pin VDD P Power supply for ports and LDO source VSS P Ground 26 PE.8 27 PE.7 User program must enable pull-up resistor in 64 and 48 package. User program must enable pull-up resistor in 64 and 48 package VBUS USB POWER SUPPLY: From USB Host or HUB VDD33 USB Internal Power Regulator Output 3.3V Decoupling Pin D- USB USB Differential Signal D D+ USB USB Differential Signal D+ PB RX0 I UART0 Data receiver input pin MOSI10 SPI1 1st MOSI (Master Out, Slave In) pin PB.1 TX0 O UART0 Data transmitter output pin MISO10 SPI1 1st MISO (Master In, Slave Out) pin PB RTSn0 O UART0 Request to Send output pin nwrl O EBI low byte write enable output pin SPICLK1 O SPI1 serial clock pin PB CTSn0 I UART0 Clear to Send input pin nwrh O EBI high byte write enable output pin SPISS10 O SPI1 1st slave select pin Mar 31, 2015 Page 42 of 95 Revision V1.00

43 Pin No QFN 33 Pin Name Pin Type Description 36 PD.6 37 PD.7 38 PD PD.15 User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. User program must enable pull-up resistor in 48 package. 40 PC.5 User program must enable pull-up resistor in 64 and 48 package. MOSI01 O SPI0 2nd MOSI (Master Out, Slave In) pin 41 PC.4 User program must enable pull-up resistor in 64 and 48 package. MISO01 I SPI0 2nd MISO (Master In, Slave Out) pin PC MOSI00 O SPI0 1st MOSI (Master Out, Slave In) pin I2SDO O I2S data output SC1RST O SmartCard1 RST pin PC.2 MISO00 I SPI0 1st MISO (Master In, Slave Out) pin I2SDI I I2S data input SC1PWR O SmartCard1 PWR pin PC SPICLK0 SPI0 serial clock pin I2SBCLK I2S bit clock pin SC1DAT SmartCard1 DATA pin PC SPISS00 SPI0 1st slave select pin I2SLRCLK I2S left right channel clock SC1CLK O SmartCard1 clock pin Mar 31, 2015 Page 43 of 95 Revision V1.00

44 Pin No QFN 33 Pin Name Pin Type Description 46 PE.6 User program must enable pull-up resistor in 64 and 48 package PE.5 PWM1CH1 PWM1 Channel1 output PB TMR3 O Timer3 external counter input PWM1CH0 PWM1 Channel0 output MISO00 SPI0 1st MISO (Master In, Slave Out) pin PB SPISS01 SPI0 2nd slave select pin TMR2 O Timer2 external counter input MOSI00 SPI0 1st MOSI (Master Out, Slave In) pin PB.9 SPISS11 SPI1 2nd slave select pin TMR1 O Timer1 external counter input nint0 I External interrupt0 input pin 51 PE.4 User program must enable pull-up resistor in 64 and 48 package. MOSI00 SPI0 1st MOSI (Master Out, Slave In) pin 52 PE.3 User program must enable pull-up resistor in 64 and 48 package. MISO00 SPI0 1st MISO (Master In, Slave Out) pin 53 PE.2 User program must enable pull-up resistor in 64 and 48 package. SPICLK0 O SPI0 serial clock pin 54 PE.1 PWM1CH3 PWM1 Channel3 output User program must enable pull-up resistor in 64 and 48 package. SPISS00 O SPI0 1st slave select pin 55 PE.0 User program must enable pull-up resistor in 64 and 48 package. Mar 31, 2015 Page 44 of 95 Revision V1.00

45 Pin No QFN 33 Pin Name Pin Type Description PWM1CH2 PWM1 Channel2 output I2SMCLK O I2S master clock output pin PC.13 User program must enable pull-up resistor in 64 and 48 package. MOSI11 O SPI1 2nd MOSI (Master Out, Slave In) pin 56 PWM1CH! O PWM1 Channel1 output SNOOPER I Snooper pin nint0 I External interrupt 0 input pin I2C0SCK O I2C0 clock pin PC.12 User program must enable pull-up resistor in 64 and 48 package. 57 MISO11 I SPI1 2nd MISO (Master In, Slave Out) pin PWM1CH0 O PWM1 Channel 0 output nint0 I External interrupt 0 input pin I2C0SDA I2C0 data pin PC.11 User program must enable pull-up resistor in 48 package. MOSI10 O SPI1 1st MOSI (Master Out, Slave In) pin TX1 O UART1 Data transmitter output pin PC.10 User program must enable pull-up resistor in 48 package. MISO10 I SPI1 1st MISO (Master In, Slave Out) pin RX1 I UART1 Data receiver input pin PC.9 SPICLK1 SPI1 serial clock pin User program must enable pull-up resistor in 48 package. I2C1SCK I2C1 clock pin PC.8 SPISS10 SPI1 1st slave select pin User program must enable pull-up resistor in 48 package. MCLK O EBI external clock output pin Mar 31, 2015 Page 45 of 95 Revision V1.00

46 Pin No QFN 33 Pin Name Pin Type Description I2C1SDA I2C1 data pin PA.15 PWM0CH3 PWM0 Channel3 output I2SMCLK O I2S master clock output pin TC3 I Timer3 capture input TX0 O UART0 Data transmitter output pin PA PWM0CH2 PWM0 Channel2 output AD15 EBI Address/Data bus bit TC2 I Timer 2 capture input RX0 I UART0 Data receiver input pin PA.13 PWM0CH1 PWM0 Channel1 output AD14 EBI Address/Data bus bit14 TC1 I Timer1 capture input I2C0SCK I2C0 clock pin PA.12 PWM0CH0 PWM0 Channel0 output AD13 EBI Address/Data bus bit13 TC0 I Timer 0 capture input I2C0SDA I2C0 data pin ICE_DAT Serial Wired Debugger Data pin PF.0 nint0 I External interrupt0 input pin ICE_CK I Serial Wired Debugger Clock pin PF.1 CLKO O Frequency Divider output pin nint1 I External interrupt1 input pin 68 VDD P Power supply for ports and LDO source for internal PLL and digital circuit VSS P Ground AVSS AP Ground Pin for analog circuit PA.0 Mar 31, 2015 Page 46 of 95 Revision V1.00