CS152 Computer Architecture and Engineering Lecture 26. Low Power Design. May 3, 2001 John Kubiatowicz (http.cs.berkeley.

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1 CS52 Computer Architecture and Engineering Lecture 26 Low Power Design May 3, 2 John Kubiatowicz (http.cs.berkeley.edu/~kubitron) lecture slides: Recap: I/O Summary I/O performance limited by weakest link in chain between OS and device Queueing theory is important % utilization means very large latency Remember, for M/M/ queue (exponential source of requests/service) - queue size goes as u/(-u) - latency goes as T ser u/(-u) For M/G/ queue (more general server, exponential sources) - latency goes as m(z) x u/(-u) = T ser x {/2 x (+C)} x u/(-u) Three Components of Disk Access Time: Seek Time: advertised to be 8 to 2 ms. May be lower in real life. Rotational Latency: 4. ms at 72 RPM and 8.3 ms at 36 RPM Transfer Time: 2 to 2 MB per second I/O device notifying the operating system: Polling: it can waste a lot of processor time I/O interrupt: similar to exception except it is asynchronous Delegating I/O responsibility from the CPU: DMA, or even IOP Lec26. Lec26.2 Recap: Disk Device Terminology Recap: Disk I/O Performance 3 Response Time (ms) Disk Latency = Queueing Time + Controller time + Seek Time + Rotation Time + Xfer Time Order of magnitude times for 4K byte transfers: Average Seek: 8 ms or less Rotate: rpm Xfer: 72 rpm Metrics: Response Time Throughput latency goes as T ser u/(-u) u = utilization Proc Queue 2 Throughput (Utilization) (% total BW) Response time = Queue + Device Service time % IOC Device % Lec26.3 Lec26.4

2 Recap: Array Reliability Redundant Arrays of Disks Reliability of N disks = Reliability of Disk N 5, Hours 7 disks = 7 hours Disk system MTTF: Drops from 6 years to month! Arrays (without redundancy) too unreliable to be useful! Files are "striped" across multiple spindles Redundancy yields high data availability Disks will fail Contents reconstructed from data redundantly stored in the array Capacity penalty to store it Bandwidth penalty to update Mirroring/Shadowing (high capacity cost) Hot spares support reconstruction in in parallel with access: very high media availability can be be achieved Techniques: Horizontal Hamming Codes (overkill) Parity & Reed-Solomon Codes Failure Prediction (no capacity overhead!) VaxSimPlus Technique is controversial Lec26.5 Lec26.6 RAID : Disk Mirroring/Shadowing RAID 3: Parity Disk recovery group P Each disk is fully duplicated onto its "shadow" Very high availability can be achieved Bandwidth sacrifice on write: Logical write = two physical writes Reads may be optimized Most expensive solution: % capacity overhead Targeted for high I/O rate, high availability environments Lec26.7 logical record Striped physical records Parity computed across recovery group to protect against hard disk failures 33% capacity cost for parity in this configuration wider arrays reduce capacity costs, decrease expected availability, increase reconstruction time Arms logically synchronized, spindles rotationally synchronized logically a single high capacity, high transfer rate disk Targeted for high bandwidth applications: Scientific, Image Processing Lec26.8

3 RAID 5+: High I/O Rate Parity Problems of Disk Arrays: Small Writes RAID-5: Small Write Algorithm A logical logical write write becomes four four physical I/Os I/Os Independent writes writes possible because of of interleaved parity parity Reed-Solomon Codes Codes ("Q") ("Q") for for protection during during reconstruction Targeted for mixed applications D D D2 D3 P D4 D5 D6 P D7 D8 D9 P D D D2 P D3 D4 D5 P D6 D7 D8 D9 Increasing Logical Disk Addresses Stripe Stripe Unit D new data Logical Write = 2 Physical Reads + 2 Physical Writes + D D D2 D3 P old data XOR (. Read) old (2. Read) parity + XOR (3. Write) (4. Write) D2 D2 D22 D23 P... Disk Columns Lec26.9 D D D2 D3 P Lec26. Hewlett-Packard (HP) AutoRAID Subsystem Organization HP has interesting solution which combines both mirroring and RAID level 5. Dynamically adapts disk storage - For recent or highly used data, uses mirroring - For less recently used data, uses RAID 5 Gets speed of mirroring when it matters and density of RAID 5 on average host manages interface to host, DMA control, buffering, parity logic physical device control host adapter array controller single board disk controller single board disk controller single board disk controller striping software off-loaded from host to array controller no applications modifications no reduction of host performance single board disk controller often piggy-backed in small format devices Lec26. Lec26.2

4 System Availability: Orthogonal RAIDs System-Level Availability String Controller String Controller host I/O Controller Fully dual redundant host I/O Controller Array Controller String Controller String Controller String Controller String Controller Array Controller Array Controller Goal: Goal: No No Single Single Points Points of of Failure Failure Data Recovery Group: unit of data redundancy Redundant Support Components: fans, power supplies, controller, cables End to End Data Integrity: internal parity protected data paths Lec26.3 Recovery Group... with duplicated paths, higher performance can be obtained when there are no failures Lec26.4 Administrivia Pending schedule: Tuesday 5/8: Last class (wrap up, evaluations, etc) Thursday 5/: Oral reports: Times TBA - Signup sheet will be on my office door next week - Project reports must be submitted via web by 5pm on 5/ Friday 5/: Grades ready System for examining grades is up James posted description of how to use on the web page Please check your grades! - Midterm II should be up there by tomorrow Solutions to Midterm II not up yet (sorry!) Oral Report Powerpoint 5 minute presentation, 5 minutes for questions 7 Talk Commandments for a Bad Talk I. Thou shalt not illustrate. II. Thou shalt not covet brevity. III. Thou shalt not print large. IV. Thou shalt not use color. V. Thou shalt not skip slides in a long talk. VI. Thou shalt cover thy naked slides. VII. Thou shalt not practice. Lec26.5 Lec26.6

5 Following all the commandments We describe the philosophy and design of the control flow machine, and present the results of detailed simulations of the performance of a single processing element. Each factor is compared with the measured performance of an advanced von Neumann computer running equivalent code. It is shown that the control flow processor compares favorablylism in the program. We present a denotational semantics for a logic program to construct a control flow for the logic program. The control flow is defined as an algebraic manipulator of idempotent substitutions and it virtually reflects the resolution deductions. We also present a bottom-up compilation of medium grain clusters from a fine grain control flow graph. We compare the basic block and the dependence sets algorithms that partition control flow graphs into clusters. Our compiling strategy is to exploit coarse-grain parallelism at function application level: and the function application level parallelism is implemented by fork-join mechanism. The compiler translates source programs into control flow graphs based on analyzing flow of control, and then serializes instructions within graphs according to flow arcs such that function applications, which have no control dependency, are executed in parallel. A hierarchical macro-control-flow computation allows them to exploit the coarse grain parallelism inside a macrotask, such as a subroutine or a loop, hierarchically. We use a hierarchical definition of macrotasks, a parallelism extraction scheme among macrotasks defined inside an upper layer macrotask, and a scheduling scheme which assigns hierarchical macrotasks on hierarchical clusters. We apply a parallel simulation scheme to a real problem: the simulation of a control flow architecture, and we compare the performance of this simulator with that of a sequential one. Moreover, we investigate the effect of modelling the application on the performance of the simulator. Our study indicates that parallel simulation can reduce the execution time significantly if appropriate modelling is used. We have demonstrated that to achieve the best execution time for a control flow program, the number of nodes within the system and the type of mapping scheme used are particularly important. In addition, we observe that a large number of subsystem nodes allows more actors to be fired concurrently, but the communication overhead in passing control tokens to their destination nodes causes the overall execution time to increase substantially. The relationship between the mapping scheme employed and locality effect in a program are discussed. The mapping scheme employed has to exhibit a strong locality effect in order to allow efficient execution. We assess the average number of instructions in a cluster and the reduction in matching operations compared with fine grain control flow execution. Medium grain execution can benefit from a higher output bandwidth of a processor and finally, a simple superscalar processor with an issue rate of ten is sufficient to exploit the internal parallelism of a cluster. Although the technique does not exhaustively detect all possible errors, it detects nontrivial errors with a worst-case complexity quadratic to the system size. It can be automated and applied to systems with arbitrary loops and nondeterminism. Alternatives to a Bad Talk Practice, Practice, Practice! Use casette tape recorder to listen, practice Try videotaping Seek feedback from friends Use phrases, not sentences Notes separate from slides (don t read slide) Pick appropriate font, size (~ 24 point to 32 point) Estimate talk length - 2 minutes per slide Use extras as backup slides (Question and Answer) Use color tastefully (graphs, emphasis) Don t cover slides Use overlays or builds in powerpoint Go to room early to find out what is WRONG with setup Beware: PC projection + dark rooms after meal! Lec26.7 Lec26.8 Include in your final presentation Who is on team, and who did what Everyone should say something High-level description of what you did and how you combined components together Use block diagrams rather than detailed schematics Assume audience knows Chapters 6 and 7 already Include novel aspects of design Did you innovate? How? Why did you choose to do things the way that you did? Give Critical Path and Clock cycle time Bring paper copy of schematics in case there are detailed questions. What could be done to improve clock cycle time? Description of testing philosophy! Mystery program statistics: instructions, clock cycles, CPI, why stalls occur (cache miss, load-use interlocks, branch mispredictions,... ) Lessons learned, what might do different next time Lec26.9 Slides Borrowed from Bob Broderson Low Power Design Lec26.2

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11 Lec26.4 Lec26.42 Back to original goal: Processor Usage Model Desired Compute-intensive and Throughput low-latency processes Ceiling: Set by top speed of the processor Typical Usage Delivered Throughput Peak Excess throughput Single-user system not always computing Background and high-latency processes System Optimizations: Maximize Peak Throughput Minimize Average Energy/operation (maximize computation per battery life) time time Wake up Compute ASAP Go to idle/sleep mode Always high throughput Always high energy/operation Lec26.43 Lec26.44

12 Another approach: Reduce Frequency Delivered Throughput Frequency set by user Peak f CLK Reduced PowerBook Control Panel Slow Fast Alternative: Dynamic Voltage Scaling Delivered Throughput Reduce throughput & f Peak CLK, Reduce energy/operation time Energy/operation remains unchanged... while throughput scales down with f CLK Problems: Circuits designed to be fast are now wasted. Demand for peak throughput not met. time Dynamically scale energy/operation with throughput Extend battery life by up to x with the same hardware! Key: Process scheduler determines operating point. Lec26.45 Lec26.46 What about bus transitions?,qsxw (QFRGHU (QFRGHG9HUVLRQ 'HFRGH Can we reduce total number of transitions on buses by sophisticated bus drivers? 2XWSXW Can we encode information in a way that takes less power? Do this on chip?! Trying to reduce total number of transitions Reasoning Increasing importance of wires relative to transistors Spend transistors to drive wires more efficiently? Try to reduce transitions over wires Orthogonal to other power-saving techniques I.e. voltage reduction, low-swing drive clock gating Parallelism (like vectors!) Lec26.47 Lec26.48

13 Huffman-based Compression Hamming Weight,QSXW (QFRGHU 'HFRGH 2XWSXW,QSXW (QFRGHU 'HFRGH 2XWSXW «Variable bit length ± problem! Possible soln: macro clock «DS )XQFWLRQ «Find a map function to minimize transition Search space is large 256! (For 8-bit bus) Leads to transition code idea Less bits!= less transitions Lec26.49 Lec26.5 Hamming Transcoder Hamming Transcoder (con t) 6WDWH7UDQVLWLRQ'LDJUDP &RGH[)) )UHT [WDEOH IRUELWEXV Only transitions matter, not absolute value Recognize more frequent transitions & assign lowweight code to them &RGH[ )UHT Guarantees more frequent transitions have less bits changes on the wire Most frequent arc assigned low-weight codes Use output codes to XOR transmission line Every in coded version causes transistion Most frequent arcs cause least number of transitions Lec26.5 Lec26.52

14 Transition Code ± Setup Simulation Results () icu_data bus &RGHU 'HFRGHU # of Transitions Uncompressed Rank = Rank = 9 Rank = 256 &RGHU &XUEXVYDOXH UHY LQSXW &XULQSXW 7UDQVLWLRQ 7DEOH 7UDQVFRGH &RGHG" ;25 7R%XV Savings Rank 9 saves 79.52% Rank 256 saves 79.68% Rank 9th bit overhead Rank : 23% Rank 9:.29% Lec26.53 Lec26.54 Simulation Results (2) # of Transitions icu_data transition vs. rank Rank XPEHURIWUDQVLWLRQV GURSVTXLFNO\DV UDQNVLQFUHDVHV [WDEOHPLJKW QRWEHQHFHVVDU\ 2WKHUWUDFHILOHVVKRZ VLPLODUWUHQGV Conclusion Best way to say power or energy: do nothing! Most Important equations to remember: Energy = CV 2 Power = CV 2 f Slowing clock rate does not reduce energy for fixed operation! RWHLFXBGDWD FRQQHFWVEHWZHHQLQVWUXFWLRQFDFKHXQLWDQG LQWHJHUXQLW$IDLUO\ORQJEXVDFFRUGLQJWRSLFR-DYD VIORRUSODQ Ways of reducing energy: Pipelining with reduced voltage Parallelism with reduced voltage Lec26.55 Lec26.56