A Simple Relaxation based Circuit Simulator for VLSI Circuits with Emerging Devices

Transcription

1 A Simple Relaxation based Circuit Simulator for VLSI Circuits with Emerging Devices Balwinder Kumar, Yogesh Dilip Save, H. Narayanan, and Sachin B. Patkar Electrical Engineering Department, Indian Institute of Technology - Bombay, Mumbai 476. Abstract This paper presents a circuit simulator based on look-up table approach for simulation of VLSI digital circuits with emerging devices which currently cannot be simulated with existing commercial simulators. We have used a point relaxation based circuit simulator which is suitable for digital circuits. To validate our circuit simulator, we have simulated standard circuits with MOS devices of SPICE level 49 for.8 micron technology and results are in very good agreement with a commercial simulator. Further, we have successfully simulated standard circuits with an emerging device, FinFET inverter, chain of FinFET inverters, 3- stage ring oscillator of FinFET inverters and read-write operations for FinFET 6-T SRAM cell. Our results match with that of the device simulator. Finally, we have been able to simulate digital circuits with approximately.6 million FinFETs (52 52 SRAM memory array) using less than.7gb working memory (Pentium-4, 3.GHz). Keywords: Look-up Table, Spline interpolation, FinFET, Relaxation, Digital Circuit, Circuit Simulator. Introduction During the last two decades, the number of transistors that can be placed on a chip has been approximately doubling every year. In the case of digital circuit, especially memory, this relationship holds strongly. With increased size of VLSI circuits, the simulation of large circuits becomes an important issue in circuit design. Conventional circuit simulators are impractical for such large circuits. Also with development in technology, new devices are emerging frequently. In order to evaluate the performance of circuits with these emerging devices, an accurate device model is required. The analytical model development of emerging devices is a difficult task as the model becomes increasingly complex with decrease in size of the device. An alternative to the analytical model based methods is a look-up table (LUT) method, which solves the above mentioned problems. The LUT method involves generation of the device characteristics tables either from direct measurements or through device simulators and uses interpolation techniques to obtain values at the intermediate points. The data tables and the interpolation method determines the accuracy of the LUT approach. With the availability of good process and device simulators, it is possible to generate the device characteristics curves even before fabricating the actual device. The LUT approach does not require analytical models. Further, unlike analytical models, improvement in data can be easily accommodated. The accuracy of the LUT based simulator depends on the number of points taken on the characteristics. Higher accuracy can be achieved with larger number of data points. But this requires larger memory for storage. Circuit simulators based on the direct method for solving a linear system of equations are not suitable with LUT approach as they require substantially more memory for storing the system coefficient matrix. Those based on iterative methods are most suitable for the LUT based simulators due to their reduced memory requirements. The point relaxation based simulators have already shown usefulness in handling large digital circuits []. Simulators based on this method require memory essentially to store the data structure. There is no need to build an explicit coefficient matrix for the equations. Thus a circuit simulator which uses a combination of LUT and point relaxation method is useful in handling large digital circuits. The use of LUT was first proposed in [2] to simulate digital circuits. In the last three decades, many improvement schemes for interpolation optimization [3], reducing memory storage requirement [4], effective construction of derivative information [5] etc. have been proposed. In [6], a new LUT method is presented for simulation of FinFET circuits but that circuit has not more than a few hundreds of transistors. The main aim of our work is to show use of relaxation method to solve large digital circuits with millions of emerging devices. The outline of the present paper is as follows. We discuss the look-up table approach for emerging devices in section 2. In section 3, cubic spline interpolation method is described which is used to interpolate the current variables and the capacitances. The overview of relaxation based circuit simulator is given in section 4. In section 5, we validate our circuit simulator through simulation of standard circuits (CMOS inverter, buffer chain of inverters and 3-stage ring oscillator) and compare it with commercial simulator HSPICE for MOS devices of SPICE level 49 for.8 micron technology. Section 6 is devoted to circuits with emerging devices. Standard circuits, FinFET inverter, chain of FinFET inverters, 3-stage ring oscillator of FinFET inverters and read-write operations for six-transistor FinFET SRAM cell are simulated using our simulator and results are verified using the device simulator. The usefulness of our simulator

2 for large size digital circuit is shown through simulation of FinFET based SRAM circuits containing millions of transistors. 2. Look-Up Table Approach for emerging devices In order to simulate a circuit, the information about inputoutput characteristics of devices is required. The current through device is a function of terminal voltages and the geometry of the device e.g., in MOS transistors, drain current is a function of gate source voltage V GS, drain source voltage V DS and bulk source voltage V BS and the dimensions width and length of the device. If we consider all the n parameters and generate n-dimensional look-up tables, this leads to large storage and evaluation time. Instead of this one can use the knowledge of the device physics and technology to reduce dimension of tables [7] as smaller dimensional tables require moderate storage and less evaluation time. To describe the transient and AC analysis accurately, in addition to static current of the device, the relation with ac current is also required. In VLSI circuits the ac current is mainly because of device capacitance. If all the capacitances are considered then the size of the table becomes large. Instead of that one can consider the capacitances that significantly contribute. There are different techniques available to extract the capacitances of emerging devices. One can employ transient analysis or AC analysis based methods to extract the capacitances using device simulator. Many device simulators provide the capacitance data tables directly. Once the lookup tables are available, an interpolation scheme can be used to obtain intermediate values in the data tables. 3. Spline Interpolation There are many different interpolation methods in numerical analysis that can be used in the LUT approach. The choice of the interpolation method depends upon the requirements like accuracy and smoothness. The spline interpolation method is the popular choice. This method employs polynomial functions with certain degree of smoothness to interpolate the data. For MOS circuit simulations, first derivative continuity is required [8]. Hence the cubic spline method has been used for the interpolation of data as it uses third degree polynomials and ensures the continuity upto the second derivative. Consider, a table consisting of values of independent variable x and corresponding values of dependent variable y. Let S i denote the cubic polynomial that will be used on the sub interval [t i,t i+ ]. In cubic spline, polynomial values at knots and, first and second derivatives of polynomial at interior of knots should be continuous. These conditions lead to 2(n ) + 2(n 2) = 4n 6 equations, but we have 4(n ) coefficients. Additional 2 equations are obtained from boundary conditions. Based on the choice of these conditions, we get different types of cubic splines. We have used natural cubic spline [9] where end points conditions are S (t ) = S (t n ) = () The cubic polynomial for x [t i,t i+ ] is given by ( yi+ h i where S i (x) = z i+ (x t i ) 3 + z i (t i+ x) 2 + ) 6h i ( 6h i yi (x t i ) + h i h i 6 z i h i 6 z i+ z i = S (t i ) ) (t i+ x) (2) The coefficients of various polynomial segments are stored to use for computation. 4. Circuit Simulator We have used circuit simulator [] which is based on Point Relaxation method. In this method, the given circuit is broken into smaller sub-circuits, in case of each sub-circuit is actually a single node. So a circuit of n nodes is essentially treated as n sub-circuits, each sub-circuit containing the concerned node and the adjacent nodes. In point relaxation method, while solving for a node potential, it is assumed that potential of all other nodes are known. This process is iterated over all the nodes. Gauss- Seidel iterations for all the nodes continues until convergence is reached. At each node, Newton-Raphson technique is used to linearize the nonlinear element and then it is solved for node potential. Convergence in is dependent on unidirectionality of signal flow and weak coupling between sub circuits. If coupling between the sub-circuits is significant and signal flow is bidirectional then the rate of convergence is slow. MOS device is a unidirectional device and MOS digital circuits usually have minimal feedback in practice. So, this relaxation technique is useful in simulating MOS integrated circuits []. 5. Validation of approach To validate correctness of our simulator, we have simulated standard circuits with MOS devices and compared results with a commercial simulator. We have used Spice model LEVEL 49, VERSION = 3. for.8 micron technology for MOS devices. 5. I D V DS curve interpolation Initially we have the interpolated values of I D V DS with spice generated values. As the second derivative is nearly zero close to start and end point of I D V DS characteristics, natural cubic spline is used as interpolation technique. Figure shows the interpolated I D V DS for V GS = V. There is always a trade-off between memory usage and accuracy. Figure 2 shows the relationship between accuracy and the number of data points. The error is exponentially

3 I DS (A) 6e-5 5e-5 4e-5 3e-5 2e-5 e-5 Interpolated I DS -V DS, V GS = V Points=7 Spice data Interpolated V DS (V) Fig. : I D (V DS ) interpolated curve at V GS = V decreasing with the number of data points. For 3% accuracy we need with only 8 data points but to achieve % accuracy more than 5 data points are required. For optimal accuracy and memory usage we have used 8 data points. I D (A) e-5 6e-5 4e-5 2e-5-2e-5 Interpolated I D -V GS, V DS =.8 V Spice data Interpolated curve Points= V GS (V) Fig. 3: I D (V GS ) interpolated curve at V DS =.8 V curves. This problem can be resolved by choosing a data point at peak and two close points on both side on the peak point. max abs. percentage error max abs. percentage error in I DS -V DS, V GS =.8 V 4 max abs. percentage error No. of data points C DD (f) 3e-6 2.5e-6 2e-6.5e-6 e-6 C DD Interpolated Curve V DS =.2 V tcad Interpolated 5e V GS (V) Fig. 2: Maximum error Vs No. of data points 5.2 I D V GS curve interpolation For I D V GS curve, simple polynomial interpolation is good only for non sub-threshold regions. In sub-threshold regions a large number of data points are required to get accurate results. Thus we have used combined interpolation technique which uses exponential interpolation for subthreshold region, polynomial interpolation for strongly inverted region and combined interpolation in transition region for I D V GS curves interpolation. Figure 3 shows I D V GS interpolation curves at V DS =.8V. 5.3 Capacitance interpolation Figure 4 shows the drain capacitance curve for V DS =.2V. We have used Sentaurus device simulator to generate data points. The interpolated values match closely with that of TCAD generated. It can be observed that interpolation is not very accurate around the peak occurring in capacitance Fig. 4: C DD (V GS ) interpolated curve 5.4 Inverter DC transfer characteristics We have simulated CMOS inverter using look-up table in and compared our results with HSPICE. Figure 5 shows transfer curve of inverter. Table shows the comparison of switching voltage of inverter as computed by and HSPICE for different device dimensions. We have found excellent agreement with HSPICE results. Our simulated curves match with SPICE very closely and shows the accuracy of the interpolation routines used. 5.5 Buffer chain of inverters Buffer chain of CMOS inverters has been simulated using and results are shown in Figure 6. We have simulated buffer chains of different number of inverter stages. The results are compared with that of HSPICE. In all cases the accuracy is within 2.4%.

4 Output Volatge (V) Inverter DC Transfer Curve Max. Diff=.7e-3 HSPICE Mean Diff= 3.55e-4 Table 2: Buffer chain with different number of stages Stages Delay Time error(%) HSPICE 8.38 ns.3 ns ns.755 ns ns ns ns 3. ns ns ns Stage Ring Oscillator Input Volatge (V) Fig. 5: Inverter DC transfer curve Table : Switching voltage for different device dimensions Dimensions Switching voltage error W P = 3. W N HSPICE (%) L =.5 µ, W N =. µ.888 V.888 V L =.5 µ, W N = 5. µ.8844 V.8843 V. L =. µ, W N = 4. µ.8663 V.8663 V L = 5. µ, W N = µ.852 V.852 V L = 5. µ, W N = 2 µ.852 V.852 V.5.5 5e-9 e-8.5e-8 2e-8 2.5e-8 3e-8 3.5e-8 Fig. 7: 3 stage ring oscillator of MOSFET inverter 5.6 Ring oscillator simulation We have simulated a ring oscillator circuit with and HSPICE and results are shown in Figure 7. Using LUT routine, we have simulated the circuit with different number of stages and, for different device dimensions for 3-stage ring oscillator. The results are shown in table 3. In all cases difference is less than 2 %. 6. Results and Discussions As an application of the use of look-up table method, we have simulated circuits having FinFET devices. FinFETs are emerging devices whose accurate analytical models are not presently available. This makes SPICE like simulators.5.5 Buffer Chain of 8 Inverters Input HSPICE 8e- e-9 e-9.4e-9.6e-9.8e-9 2e-9 2.2e-9 2.4e-9 Fig. 6: Buffer chain of 8 MOSFET inverters Table 3: Ring oscillator with different number of stages No. of Stages Oscillation Frequency Error(%) HSPICE 3 MHz 36 MHz MHz 223 MHz MHz 78 MHz MHz 46 MHz MHz 24 MHz MHz 9 MHz incapable of simulating circuits involving such devices as they employ device analytical models. However, with integration of LUT routines into, it is capable of simulating such circuits. To simulate a circuit having FinFETs, requires to have look-up table for its drain current I D and various capacitances such as gate source capacitance C gs, gate drain capacitance C gd, drain source capacitance C ds. Device simulator SENTARUS has been used to generate look-up table for drain current I D and various capacitances of FinFETs. The section discusses the results obtained in simulation of FinFET inverter and buffer chain of FinFET inverters, 3-stage ring oscillator of FinFET inverters and read-write operations for FinFET 6-T SRAM cell. 6. FinFET inverter We have simulated FinFET inverter by using look-up tables for its drain current I D in. Figure 8 shows the DC transfer curve of FinFET inverter. We have got excellent agreement with device simulator results with difference less than 4 for all data points.

5 FinFET Inverter DC Transfer Curve Input Device Simulator Fig. 8: FinFET inverter DC transfer curve 6.2 Chain of FinFET inverters We have simulated chain of 3 FinFET inverter by using look-up tables for its drain current I D and capacitances in. Delay for chain of 3 FinFETs comes out to be 4.5 ps. We have got good agreement with device simulator results. The first stage output of the circuit is shown in Figure 9. Figure shows that there is some mismatch between the LUT enabled output and device simulator data. The possible reason could be the very high frequency of operation and breakdown of quasi-static model. We have used capacitance data generated at frequency MHz, but the operational frequency is order of few GHz. 6.3 FinFET ring oscillator We have simulated 3-stage ring oscillator with Fin- FET inverters and result is shown in Figure. Due to convergence problem, device simulator could not simulate the circuit. As a result we can not validate the accuracy of our simulation directly. However, we have compared single stage delay calculated from the frequency of the ring oscillator with the delay obtained from simulation of a chain of FinFET inverter using device simulator. The oscillation frequency comes out to be 8.85 GHZ. It gives single stage delay of.8 ps which matches with the result obtained from device simulator. This proves the ability of LUT enabled to simulate circuits involving emerging devices like FinFETs correctly. 3 Stage Ring Oscillator of FinFET Inverters Chain of 3 FinFET Inverters -.2 3e-2 6e-2 9e-2 e-.5e- Input Device Simulator e- 2e- 3e- 4e- 5e- Fig. : 3 stage ring oscillator of FinFET inverters Fig. 9: First stage output of chain of 3 FinFET inverters Chain of 3 FinFET Inverters -.2 3e-2 6e-2 9e-2 e-.5e- Input Device Simulator Fig. : Third stage output of chain of 3 FinFET Inverters T SRAM with FinFET We have simulated the six-transistor FinFET SRAM cell. The bit line capacitance values is taken as ff. In case of read operations, both the bit lines were pre-charged to. V. When the word line goes high, one of the bit lines is discharged, depending upon whether or is stored in cell. Figure 2 shows the read operation, when is stored in cell. In case of write operations, if we want to write into cell, we charge bit line to and bit line bar to and vice-versa. When the word line goes high, desired value is written into cell. Figure 3 shows the write operation for changing the cell value from to. Table 4 shows a performance Bremics for read operation in terms of memory and simulation time. From the table it is clear that the timing performance and memory usage of Bremics is linear. We have simulated SRAM memory array

6 SRAM read operation e- 2e- 3e- 4e- 5e- word line SRAM read operation e- 2e- 3e- 4e- 5e- Q Q bar SRAM read operation e- 2e- 3e- 4e- 5e- bit line bit line bar Fig. 2: FinFET SRAM read operation SRAM write operation 5e- e-.5e- 2e- 2.5e- 3e- 3.5e- 4e- SRAM write operation word line 5e- e-.5e- 2e- 2.5e- 3e- 3.5e- 4e- SRAM write operation bit line bit line bar 5e- e-.5e- 2e- 2.5e- 3e- 3.5e- 4e- Q Q bar Fig. 3: FinFET SRAM write operation Table 4: Memory and Timing Performance of for SRAM (memory read operation) SRAM size Nodes Memory Usage(MB) Time(sec) 8x x x x x x x of size (.6 million transistors) using only.7gb working memory even though LUT requires large memory to store the characteristics. This is possible because of the use of a point relaxation method for a solution of a system of equations as there is no need to store an explicit coefficient matrix for the equations. 7. Conclusion The primary aim of the present work is to demonstrate that using an elementary relaxation technique and the lookup method a large circuit (about million FinFETs) with emerging devices can be simulated in reasonable time. We have presented results to support this claim by analyzing an SRAM memory array of size (.6 million transistors) in 3 hours using only.7gb working memory. This shows that the capability of integration of a point relaxation method with LUT to handle a large size digital circuits with emerging devices. Also, as point relaxation method is inherently parallelizable, one can easily extend the use this simulator to simulate entire chip using parallelization techniques. The look-up tables used in this work are based on data provided by device simulators. One can use actual experimental data also to build look-up tables without any change in the approach. References [] S. Roy, Y. Save, H. Narayanan, and S. B. Patkar, Large scale VLSI circuit simulation using point relaxation, in International Conference on Scientific Computing, CSC 2, 2, pp [2] B. Chawla, H. Gummel, and P. Kozak, Motis-an MOS timing simulator, IEEE Transactions on Circuits and Systems, vol. 22, no. 2, pp. 9 9, Dec 975. [3] J. Barby, J. Vlach, and K. Singhal, Polynomial splines for MOSFET model approximation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, no. 5, pp , May 988. [4] P. Meijer, Fast and smooth highly nonlinear multidimensional table models for device modeling, IEEE Transactions on Circuits and Systems, vol. 37, no. 3, pp , Mar. 99. [5] A. Rofougaran and A. Abidi, A table lookup FET model for accurate analog circuit simulation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 2, no. 2, pp , Feb [6] R. A. Thakker, C. Sathe, A. B. Sachid, M. S. Baghini, V. R. Rao, and M. B. Patil, A novel table-based approach for design of FinFET circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 7, pp. 6 7, 29. [7] P. Subramaniam, Modeling MOS VLSI circuits for transient analysis, IEEE Journal of Solid-State Circuits, vol. 2, no. 2, pp , Apr 986. [8] J. Coughran, W.M., E. Grosse, and D. Rose, Cazm: A circuit analyzer with macromodeling, IEEE Transactions on Electron Devices, vol. 3, no. 9, pp , Sep 983. [9] W. Cheney and D. Kincaid, Numerical mathematics and computing, Brooks Cole Publishing Company, pp , 985. [] W. Mokari and D. Smart, Robust VLSI circuit simulation techniques based on overlapped waveform relaxation IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 4, no. 4, pp. 5 58, 995.