description V CC V SS DQ4 DQ3 DQ1 DQ4 CAS RAS OE A9 A11 A0 A1 A2 A3 A7 A6 A5 A4 DJ/DGA PACKAGES ( TOP VIEW )

Transcription

1 This data sheet is applicable to all TMS41x409As and TMS42x409As symbolized by Revision B, Revision E, and subsequent revisions as described in the device symbolization section. Organization Single Power Supply (5 V or 3.3 V) Performance Ranges: ACCESS ACCESS ACCESS EDO TIME TIME TIME CYCLE trac tcac taa thpc MAX MAX MAX MIN 41x409A ns 13 ns 25 ns 20 ns 41x409A ns 15 ns 30 ns 25 ns 41x409A ns 18 ns 35 ns 30 ns 42x409A ns 13 ns 25 ns 20 ns 42x409A ns 15 ns 30 ns 25 ns 42x409A ns 18 ns 35 ns 30 ns Extended-Data-Out (EDO) Operation -Before- ( CBR) Refresh Low Power Dissipation 3-State Unlatched Output High-Reliability Plastic 24/ 26-Lead 300-Mil-ide Surface-Mount Small-Outline J-Lead (SOJ) Package (DJ Suffix) and 24/26-Lead 300-Mil-ide Surface-Mount Thin Small-Outline Package (TSOP) (DGA Suffix) Operating Free-Air Temperature Range 0 C to 70 C description The TMS41x409A and TMS42x409A series are bit dynamic random-access memory (DRAM) devices organized as words of four bits each. These devices feature maximum access times of 50, 60, and 70 ns. All address and data-in lines are latched on chip to simplify system design. Data out is unlatched to allow greater system flexibility. TMS416409A, TMS417409A, TMS426409A, TMS427409A A0 A11 NC VCC VSS DEVICE V CC DQ1 DQ2 A11 A10 A0 A1 A2 A3 V CC DJ/DGA PACKAGES ( TOP VIE ) PIN NOMENCLATURE Inputs Data In / Data Out Column- Strobe No Internal Connection Output Enable Row- Strobe 5-V or 3.3-V Supply Ground rite Enable A11 is NC for TMS417409A and TMS427409A. See Available Options Table AVAILABLE OPTIONS PR SUPPLY V SS DQ4 DQ3 A9 A8 A7 A6 A5 A4 V SS SELF REFRESH, BATTERY BACKUP REFRESH CYCLES TMS416409A 5 V 4096 in 64 ms TMS417409A 5 V 2048 in 32 ms TMS426409A 3.3 V 4096 in 64 ms TMS427409A 3.3 V 2048 in 32 ms The TMS416409A and TMS417409A are offered in a 24/ 26-lead plastic surface-mount SOJ package (DJ suffix). The TMS426409A and TMS427409A are offered in a 24/26-lead plastic surface-mount SOJ package (DJ suffix) and a 24/ 26-lead plastic surface-mount TSOP (DGA suffix). These packages are designed for operation from 0 C to 70 C Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 1997, Texas Instruments Incorporated POST OFFICE BOX 1443 HOUSTON, TEXAS

2 logic symbol (TMS416409A and TMS426409A) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A D10/21D0 RAM 4096 K 4 A 20D19/21D9 20D20 20D21 C20 [RO] G23/[REFRESH RO] 24 [PR DN] C21[COLUMN] G24 & C22 23,21D 24,25 EN G25 DQ1 DQ2 DQ3 DQ A,22D 26 A,Z26 This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BOX 1443 HOUSTON, TEXAS

3 logic symbol (TMS417409A and TMS427409A) TMS416409A, TMS417409A, TMS426409A, TMS427409A A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A D11/21D0 20D21/21D10 RAM 4096 K 4 A C20 [RO] G23/[REFRESH RO] 24 [PR DN] C21[COLUMN] G24 & 23C22 23,21D 24,25 EN G25 DQ1 DQ2 DQ3 DQ A,22D 26 A,Z26 This symbol is in accordance with ANSI/IEEE Std and IEC Publication POST OFFICE BOX 1443 HOUSTON, TEXAS

4 functional block diagram TMS416409A, TMS426409A Timing and Control A0 A1 A11 Column- Buffers Row- Buffers R o w D e c o d e Column Decode Sense Amplifiers 256K Array 256K Array 256K Array I/O Buffers Data- In Reg. Data- Out Reg Column addresses A10 and A11 are not used. TMS417409A, TMS427409A Timing and Control A0 A1 A10 Column- Buffers Row- Buffers Column Decode Sense Amplifiers 256K Array R 256K Array 256K Array o 256K Array w 256K Array D e c o d e 256K Array I/O Buffers Data- In Reg. Data- Out Reg POST OFFICE BOX 1443 HOUSTON, TEXAS

5 operation extended data out Extended data out (EDO) allows data output rates of up to 50 MHz for 50-ns devices. hen keeping the same row address while selecting random column addresses, the time for row-address setup and hold and for address multiplex is eliminated. The maximum number of columns that can be accessed is determined by t P, the maximum low time. Extended data out does not place the data in/data out pins (DQ pins) into the high-impedance state with the rising edge of. The output remains valid for the system to latch the data. After goes high, the DRAM decodes the next address. and can control the output impedance. Descriptions of and further explain EDO operation benefit. address: A0 A11 ( TMS416409A and TMS426409A) and A0 A10 (TMS417409A and TMS427409A) Twenty-two address bits are required to decode each of the storage cell locations. For the TMS416409A and TMS426409A,12 row-address bits are set up on A0 through A11 and latched onto the chip by the row-address strobe (). Ten column-address bits are set up on A0 through A9. For the TMS417409A and TMS427409A, 11 row-address bits are set up on inputs A0 through A10 and latched onto the chip by. Eleven column-address bits are set up on A0 through A10. All addresses must be stable on or before the falling edge of and. is similar to a chip enable because it activates the sense amplifiers as well as the row decoder. is used as a chip select, activating the output buffers and latching the address bits into the column-address buffers. output enable () controls the impedance of the output buffers. hile and are low and is high, can be brought low or high and the DQs transition between valid data and high impedance (see Figure 8). There are two methods for placing the DQs into the high-impedance state and maintaining that state during high time. The first method is to transition high before transitions high and keep high for t CHO (hold time, from ) past the transition. This disables the DQs and they remain disabled, regardless of, until falls again. The second method is to have low as transitions high. Then can pulse high for a minimum of t P (precharge time, ) anytime during high time, disabling the DQs regardless of further transitions on until falls again (see Figure 8). write enable () The read or write mode is selected through. A logic high on selects the read mode, and a logic low selects the write mode. The data inputs are disabled when the read mode is selected. hen goes low prior to (early write), data out remains in the high-impedance state for the entire cycle, permitting a write operation with grounded. If goes low in an extended-data-out read cycle, the DQs are disabled so long as is high (see Figure 9). data in/data out (DQ1 DQ4) Data is written during a write or read-modify-write cycle. Depending on the mode of operation, the later falling edge of or strobes data into the on-chip data latch with setup and hold times referenced to the later edge. The DQs drive valid data after all access times are met and remain valid except in cases described in the and sections. POST OFFICE BOX 1443 HOUSTON, TEXAS

6 -only refresh TMS416409A, TMS426409A A refresh operation must be performed at least once every 64 ms to retain data. This can be achieved by strobing each of the 4096 rows (A0 A11). A normal read or write cycle refreshes all bits in each row that is selected. A -only operation can be used by holding at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a -only refresh. TMS417409A, TMS427409A A refresh operation must be performed at least once every 32 ms to retain data. This can be achieved by strobing each of the 2048 rows (A0 A10). A normal read or write cycle refreshes all bits in each row that is selected. A -only operation can be used by holding at the high (inactive) level, conserving power as the output buffers remain in the high-impedance state. Externally generated addresses must be used for a -only refresh. hidden refresh A hidden refresh can be performed while maintaining valid data at the output pin. This is accomplished by holding at V IL after a read operation and cycling after a specified precharge period, similar to a -only refresh cycle. The external address is ignored, and the refresh address is generated internally. -before- ( CBR) refresh CBR refresh is performed by bringing low earlier than (see parameter t CSR ) and holding it low after falls (see parameter t CHR ). For successive CBR refresh cycles, can remain low while cycling. The external address is ignored, and the refresh address is generated internally. power up To achieve proper device operation, an initial pause of 200 µs followed by a minimum of eight initialization cycles is required after power up to the full V CC level. These eight initialization cycles must include at least one refresh (-only or CBR) cycle. test mode The test mode (see Figure 1) is initiated with a CBR-refresh cycle while simultaneously holding the input low. The entry cycle performs an internal refresh cycle while internally setting the device to perform parallel read or write on subsequent cycles. hile in the test mode, any data sequence can be performed. The device exits test mode if a CBR refresh cycle with held high or a -only refresh cycle is performed. In the test mode, the device is configured as 1024K bits 4 bits for each DQ. Each DQ pin has a separate 4-bit parallel read and write data bus that ignores column addresses A0 and A1. During a read cycle, the four internal bits are compared for each DQ pin. If the four bits agree, DQ goes high; if not, DQ goes low. Test time is reduced by a factor of four for this series. 6 POST OFFICE BOX 1443 HOUSTON, TEXAS

7 test mode (continued) Entry Cycle Test Mode Cycle Exit Cycle Normal Mode NOTE A: The states of, data in, and address are defined by the type of cycle used during test mode. Figure 1. Test-Mode Cycle POST OFFICE BOX 1443 HOUSTON, TEXAS

8 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC (TMS41x409A) V to 7 V Supply voltage range, V CC (TMS42x409A) V to 4.6 V Voltage range on any pin (TMS41x409A) (see Note 1) V to 7 V Voltage range on any pin (TMS42x409A) (see Note 1) V to 4.6 V Short-circuit output current ma Power dissipation Operating free-air temperature range, T A C to 70 C Storage temperature range, T stg C to 125 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to VSS. recommended operating conditions TMS41x409A TMS42x409A MIN NOM MAX MIN NOM MAX UNIT VCC Supply voltage V VSS Supply voltage 0 0 V VIH High-level input voltage VCC V VIL Low-level input voltage (see Note 2) V TA Operating free-air temperature C NOTE 2: The algebraic convention, where the more negative (less positive) limit is designated as minimum, is used for logic-voltage levels only. 8 POST OFFICE BOX 1443 HOUSTON, TEXAS

9 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TMS416409A VOH PARAMETER High-level output voltage TEST CONDITIONS A A A- 70 MIN MAX MIN MAX MIN MAX IOH = 5 ma V VOL Low-level output voltage IOL = 4.2 ma V II IO ICC1 ICC2 ICC3 ICC4 Input current (leakage) Output current (leakage) Average read- or write-cycle current Average standby current Average refresh current (-only refresh or CBR) Average EDO current VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, high UNIT ± 10 ± 10 ± 10 µa ± 10 ± 10 ± 10 µa VCC = 5.5 V, Minimum cycle ma VIH = 2.4 V ( TTL), After one memory cycle, and high VIH = VCC 0.2 V (CMOS), After one memory cycle, and high VCC = 5.5 V, Minimum cycle, cycling, high ( only), low after low (CBR) VCC = 5.5 V, low, thpc = MIN, cycling For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while = VIL Measured with a maximum of one address change during each EDO cycle, thpc ma ma ma ma POST OFFICE BOX 1443 HOUSTON, TEXAS

10 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS417409A VOH PARAMETER High-level output voltage TEST CONDITIONS A A A- 70 MIN MAX MIN MAX MIN MAX IOH = 5 ma V VOL Low-level output voltage IOL = 4.2 ma V II IO ICC1 ICC2 ICC3 ICC4 Input current (leakage) Output current (leakage) Average read- or write-cycle current Average standby current Average refresh current (-only refresh or CBR) Average EDO current VCC = 5.5 V, VI = 0 V to 6.5 V, All others = 0 V to VCC VCC = 5.5 V, VO = 0 V to VCC, high UNIT ± 10 ± 10 ± 10 µa ± 10 ± 10 ± 10 µa VCC = 5.5 V, Minimum cycle ma VIH = 2.4 V ( TTL), After one memory cycle, and high VIH = VCC 0.2 V (CMOS), After one memory cycle, and high VCC = 5.5 V, Minimum cycle, cycling, high ( only), low after low (CBR) VCC = 5.5 V, low, thpc = MIN, cycling For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while = VIL Measured with a maximum of one address change during each EDO cycle, thpc ma ma ma ma 10 POST OFFICE BOX 1443 HOUSTON, TEXAS

11 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS426409A VOH VOL II IO ICC1 ICC2 ICC3 PARAMETER TEST CONDITIONS A A A- 70 MIN MAX MIN MAX MIN MAX High-level IOH = 2 ma LVTTL output voltage IOH = 100 µa LVCMOS VCC 0.2 VCC 0.2 VCC 0.2 Low-level IOL = 2 ma LVTTL output voltage IOL = 100 µa LVCMOS Input current (leakage) Output current (leakage) Average read- or write- cycle current Average standby current Average refresh current (-only refresh or CBR) VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VCC = 3.6 V, high VO = 0 V to VCC, UNIT V V ± 10 ± 10 ± 10 µa ± 10 ± 10 ± 10 µa VCC = 3.6 V, Minimum cycle ma VIH = 2 V (LVTTL) After one memory cycle, and high VIH = VCC 0.2 V (LVCMOS), After one memory cycle, and high VCC = 3.6 V, Minimum cycle, cycling, high (-only refresh), low after low (CBR) ma ma ma ICC4 Average VCC = 3.6 V, thpc = MIN, ma EDO current low, cycling For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while = VIL Measured with a maximum of one address change during each EDO cycle, thpc POST OFFICE BOX 1443 HOUSTON, TEXAS

12 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) TMS427409A VOH VOL II IO ICC1 ICC2 ICC3 PARAMETER TEST CONDITIONS A A A- 70 MIN MAX MIN MAX MIN MAX High-level IOH = 2 ma LVTTL output voltage IOH = 100 µa LVCMOS VCC 0.2 VCC 0.2 VCC 0.2 Low-level IOL = 2 ma LVTTL output voltage IOL = 100 µa LVCMOS Input current (leakage) Output current (leakage) Average read- or write- cycle current Average standby current Average refresh current (-only refresh or CBR) VCC = 3.6 V, VI = 0 V to 3.9 V, All others = 0 V to VCC VCC = 3.6 V, high VO = 0 V to VCC, UNIT V V ± 10 ± 10 ± 10 µa ± 10 ± 10 ± 10 µa VCC = 3.6 V, Minimum cycle ma VIH = 2 V (LVTTL) After one memory cycle, and high VIH = VCC 0.2 V (LVCMOS), After one memory cycle, and high VCC = 3.6 V, Minimum cycle, cycling, high (-only refresh), low after low (CBR) ma ma ma ICC4 Average VCC = 3.6 V, thpc = MIN, ma EDO current low, cycling For conditions shown as MIN / MAX, use the appropriate value specified in the timing requirements. Measured with outputs open Measured with a maximum of one address change while = VIL Measured with a maximum of one address change during each EDO cycle, thpc 12 POST OFFICE BOX 1443 HOUSTON, TEXAS

13 capacitance over recommended ranges of supply voltage and operating free-air temperature, f = 1 MHz (see Note 3) PARAMETER MIN MAX UNIT Ci(A) Input capacitance, A0 A11 5 pf Ci() Input capacitance, 7 pf Ci(RC) Input capacitance, and 7 pf Ci() Input capacitance, 7 pf Co Output capacitance 7 pf A11 is NC (no internal connection) for TMS417409A and TMS427409A. and = VIH to disable outputs NOTE 3: VCC = NOM supply voltage ±10%, and the bias on pins under test is 0 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 4) 41x409A-50 42x409A-50 41x409A-60 42x409A-60 41x409A-70 42x409A-70 PARAMETER UNIT MIN MAX MIN MAX MIN MAX taa Access time from column address (see Note 5) ns tcac Access time from (see Note 5) ns tcpa Access time from precharge (see Note 5) ns trac Access time from (see Note 5) ns ta Access time from (see Note 5) ns tclz Delay time, to output in low impedance ns trez Output buffer turn off delay from (see Note 6) ns tcez Output buffer turn off delay from (see Note 6) ns tz Output buffer turn off delay from (see Note 6) ns tez Output buffer turn off delay from (see Note 6) ns NOTES: 4. ith ac parameters, it is assumed that tt = 2 ns. 5. For TMS42x409A, access times are measured with output reference levels of VOH = 2 V and VOL = 0.8 V. 6. The maximum values of trez, tcez, tz, and tez are specified when the output is no longer driven. Data in should not be driven until one of the applicable maximum specifications is satisfied. POST OFFICE BOX 1443 HOUSTON, TEXAS

14 EDO timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) 41x409A-50 42x409A-50 41x409A-60 42x409A-60 41x409A-70 42x409A-70 UNIT MIN MAX MIN MAX MIN MAX thpc Cycle time, EDO page mode, read-write ns tprc Cycle time, EDO read-write ns tcsh Delay time, active to precharge ns tcho Hold time, from ns tdoh Hold time, output from ns t Pulse duration, active (see Note 7) ns tpe Pulse duration, active (output disable only) ns toch Setup time, before ns tcp Pulse duration, precharge ns tp Precharge time, ns NOTES: 4: ith ac parameters, it is assumed that tt = 2 ns. 7. In a read-write cycle, tcd and tcl must be observed. 14 POST OFFICE BOX 1443 HOUSTON, TEXAS

15 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) 41x409A-50 42x409A-50 41x409A-60 42x409A-60 41x409A-70 42x409A-70 UNIT MIN MAX MIN MAX MIN MAX trc Cycle time, random read or write ns trc Cycle time, read-write ns tp Pulse duration, active, fast page mode (see Note 8) ns t Pulse duration, active, non-page mode (see Note 8) ns trp Pulse duration, precharge ns tp Pulse duration, write command ns tasc Setup time, column address ns tasr Setup time, row address ns tds Setup time, data in (see Note 9) ns trcs Setup time, read command ns tcl Setup time, write command before precharge ns trl Setup time, write command before precharge ns tcs Setup time, write command before active (early-write only) ns trp Setup time, high before low (CBR refresh only) ns tts Setup time, low before low (test mode only) ns tcsr Setup time, referenced to ( CBR refresh only ) ns tcah Hold time, column address ns tdh Hold time, data in (see Note 9) ns trah Hold time, row address ns trch Hold time, read command referenced to (see Note 10) ns trrh Hold time, read command referenced to (see Note 10) ns tch Hold time, write command during active ( early-write only ) ns troh Hold time, referenced to ns trh Hold time, high after low (CBR refresh) ns tth Hold time, low after low (test mode only) ns tchr Hold time, referenced to ( CBR refresh only ) ns th Hold time, command ns trhcp Hold time, active from precharge ns NOTES: ith ac parameters, it is assumed that tt = 2 ns. In a read-write cycle, trd and trl must be observed. 9. Referenced to the later of or in write operations 10. Either trrh or trch must be satisfied for a read cycle. POST OFFICE BOX 1443 HOUSTON, TEXAS

16 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Note 4) (continued) 41x409A-50 42x409A-50 41x409A-60 42x409A-60 41x409A-70 42x409A-70 MIN MAX MIN MAX MIN MAX tad Delay time, column address to write command ( read-write only ) ns tcp Delay time, low after x precharge (read-write only) ns tcrp Delay time, precharge to ns tcd Delay time, to write command ( read-write only ) ns td Delay time, to data in ns trad Delay time, to column address (see Note 11) ns tral Delay time, column address to precharge ns tcal Delay time, column address to precharge ns trcd Delay time, to ( see Note 11) ns trpc Delay time, precharge to ns trsh Delay time, active to precharge ns trd Delay time, to write command (read-write only) ns ttaa Access time from address (test mode) ns ttcpa Access time, from column precharge (test mode) ns ttrac Access time, from (test mode) ns tt Transition time ns tref Refresh time interval NOTES: 4. ith ac parameters, it is assumed that tt = 2 ns. 11. The maximum value is specified only to ensure access time. UNIT 4x6409A ms 4x7409A ms 16 POST OFFICE BOX 1443 HOUSTON, TEXAS

17 PARAMETER MEASUREMENT INFORMATION VTH VCC RL R1 Output Under Test CL = 100 pf (see Note A) Output Under Test CL = 100 pf (see Note A) R2 (a) LOAD CIRCUIT (b) ALTERNATE LOAD CIRCUIT NOTE A: CL includes probe and fixture capacitance. DEVICE VCC (V) R1 () R2 () VTH (V) RL () 41x409A x409A Figure 2. Load Circuits for Timing Parameters POST OFFICE BOX 1443 HOUSTON, TEXAS

18 PARAMETER MEASUREMENT INFORMATION trc t trp tt tcsh trcd trsh tcrp tasr t trah trad tasc tcal tral tcp Row Column trcs tcah trrh trch taa tcac tcez trez Hi-Z See Note A tclz trac ta Valid Data Out tez tpe tz troh NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 3. Read-Cycle Timing 18 POST OFFICE BOX 1443 HOUSTON, TEXAS

19 PARAMETER MEASUREMENT INFORMATION trc t trp tt trsh trcd tcrp tcsh tasr tasc t tcp tcal trah tral tcah Row Column trad tcl trl tch tcs tdh tds Valid Data Figure 4. Early-rite-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

20 PARAMETER MEASUREMENT INFORMATION trc t tt trsh trp trcd t tcrp tcsh tasr tasc tcp tral trah tcal tcah Row Column trad tds tcl trl tp tclz tdh Invalid Data Out td Valid Data In th Figure 5. rite-cycle Timing 20 POST OFFICE BOX 1443 HOUSTON, TEXAS

21 tad t CD TMS416409A, TMS417409A, TMS426409A, TMS427409A PARAMETER MEASUREMENT INFORMATION trc t tt trp trcd tcrp tasr trah t tcp trad tasc tcah tt Row Column trcs tcl trd tp trl tcac taa tds tclz tdh Hi-Z See Note A Data Out Data In trac ta td tz th NOTE A: Output can go from the high-impedance state to an invalid-data state prior to the specified access time. Figure 6. Read-rite-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

22 PARAMETER MEASUREMENT INFORMATION tp tt trcd tcsh thpc trhcp trsh tcrp trp t tcp trah tasc tasr tcah tcal tral Row Column #1 Column #2 Column #3 trad ta trch trcs tcac tdoh trrh trac tclz taa tcac taa tcpa tcez trez See Note C See Note A Data #1 Data #2 Data #3 NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. C. Access time is tcpa-, taa-, or tcac-dependent. Output is turned off by tcez if goes high during low. Figure 7. EDO Read Cycle 22 POST OFFICE BOX 1443 HOUSTON, TEXAS

23 PARAMETER MEASUREMENT INFORMATION trp tp tcsh thpc t tcp trhcp trsh tasr trah tasc tcah tcal tral Row Column #1 Column #2 Column #3 trad toch tcho tp tp ta trcs ta tcac trrh trch tclz tdoh tcac tz See Note A taa tcpa tcez trez trac tz taa Data #1 Data #1 Data #2 Data #3 NOTE A: Output is turned off by tcez if goes high during low. Figure 8. EDO Read-Cycle ith Control POST OFFICE BOX 1443 HOUSTON, TEXAS

24 PARAMETER MEASUREMENT INFORMATION tp tcsh thpc trhcp trsh trp tcrp t tcp tasr tasc trah tcah tcal tral Row Column #1 Column #2 Column #3 trad trcs ta tpe tcac tcac trch trrh trac tclz taa tcac tcpa taa tez tdoh tcpa taa tcez trez Data #1 Data #2 Data #3 Figure 9. EDO Read-Cycle ith Control 24 POST OFFICE BOX 1443 HOUSTON, TEXAS

25 PARAMETER MEASUREMENT INFORMATION tp trp trhcp trcd tcsh t thpc trsh tcrp tasc trah tasr tcah tcp tcal tral Row Column Column trad tcs tcl tch tcl trl tdh tds Data In Data In NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 10. EDO Early-rite-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

26 PARAMETER MEASUREMENT INFORMATION trp tp trhcp trcd tcsh thpc tcal trsh tcrp trah tasr tasc t tcah tcp tral Row Column Column trad tcl tcl tds tp trl tdh tclz th Valid Data In Valid In Invalid Data out th td NOTE A: A read cycle or a read-write cycle can be intermixed with write cycles as long as read and read-write timing specifications are not violated. Figure 11. EDO rite-cycle Timing 26 POST OFFICE BOX 1443 HOUSTON, TEXAS

27 PARAMETER MEASUREMENT INFORMATION trp tp tcsh trcd tprc tcp trsh tcrp tasc tasr t trad tcah tcal tral Row Column 1 Column 2 trah trd tcd tad tp tcp tcl trl trac trcs taa tcac tds tcpa tdh Valid Out 2 (see Note A) th tclz ta Valid Out 1 tz Valid In 1 th td Valid In 2 NOTES: A. Output can go from the high-impedance state to an invalid-data state prior to the specified access time. B. A read or write cycle can be intermixed with read-write cycles as long as the read- and write-timing specifications are not violated. Figure 12. EDO Read-rite-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

28 PARAMETER MEASUREMENT INFORMATION t trc tcrp trp tt trpc tasr trah Row Row Hi Z Figure 13. -Only Refresh-Cycle Timing 28 POST OFFICE BOX 1443 HOUSTON, TEXAS

29 PARAMETER MEASUREMENT INFORMATION trp trc t trpc tcsr tt tchr trp trh Hi-Z Figure 14. Automatic-CBR-Refresh-Cycle Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

30 PARAMETER MEASUREMENT INFORMATION Memory Cycle t trp Refresh Cycle t trp Refresh Cycle tchr t tasc tcah trah tasr Row Col trh trrh trh trp trcs trp trp trh trac taa tcac tez trez tcez Valid Data Out tclz ta tz Figure 15. Hidden-Refresh-Cycle (Read) Timing 30 POST OFFICE BOX 1443 HOUSTON, TEXAS

31 PARAMETER MEASUREMENT INFORMATION Memory Cycle Refresh Cycle Refresh Cycle t trp t trp t tchr tcah tasc trah tasr Row Col tcs trp trh tp tds tch tdh Valid Data Figure 16. Hidden-Refresh-Cycle (rite) Timing POST OFFICE BOX 1443 HOUSTON, TEXAS

32 PARAMETER MEASUREMENT INFORMATION trp trc tcsr t trpc tchr tt tts tth Hi-Z Figure 17. Test-Mode-Entry-Cycle Timing trc trp t trpc tcsr tchr tt trp trh trez tcez Hi-Z Figure 18. Test-Mode-Exit-Cycle CBR-Refresh-Cycle Timing 32 POST OFFICE BOX 1443 HOUSTON, TEXAS

33 DJ (R-PDSO-J24/26) MECHANICAL DATA PLASTIC SMALL-OUTLINE J-LEAD PACKAGE (17,27) (17,02) (7,75) (7,49) (8,64) (8,38) (0,81) (0,66) (3,76) (3,25) (2,69) TYP (0,20) NOM Seating Plane (0,51) (0,41) (0,18) M (0,10) (6,99) (6,60) (1,27) / B 02/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Plastic body dimensions do not include mold protrusion. Maximum mold protrusion is (0,125). POST OFFICE BOX 1443 HOUSTON, TEXAS

34 DGA (R-PDSO-G24/26) MECHANICAL DATA PLASTIC SMALL-OUTLINE PACKAGE (1,27) (0,50) (0,30) (0,21) M (9,42) (9,02) (7,72) (7,52) (0,15) NOM (17,24) (17,04) Gage Plane (0,25) (0,60) (0,40) Seating Plane (1,19) MAX (0,05) MIN (0,10) / C 11/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion. 34 POST OFFICE BOX 1443 HOUSTON, TEXAS

35 device symbolization (TMS416409A illustrated) TMS416409A, TMS417409A, TMS426409A, TMS427409A TI -SS Speed ( - 50, - 60, - 70) TMS416409A DJ Package Code E Y M LLLL P Assembly Site Code Lot Traceability Code Month Code Year Code Die Revision Code afer Fab Code POST OFFICE BOX 1443 HOUSTON, TEXAS

36 36 POST OFFICE BOX 1443 HOUSTON, TEXAS

37 IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage ( Critical Applications ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR ARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be directed to TI through a local SC sales office. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. Copyright 1998, Texas Instruments Incorporated