Implement a PCIe endpoint using Qsys System Integration Tool

Transcription

1 Implement a PCIe endpoint using Qsys System Integration Tool

2 Agenda What is Qsys? Qsys UI Using Qsys in FPGA design flow Qsys files Qsys Intellectual Property(IP) 2

3 Tradi?onal System Design Address Decoder Processor (32-bit Master) Bus Interface Address Data Arbiter Interrupt Controller PCI Express (64-bit Master) Bus Interface Address Data Width Adapter Width Adapter Width Adapter Width Adapter Width Adapter Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Slave 4 32-Bit Slave 5 64-Bit Components in system use different interfaces to communicate (some standard, some non- standard) Typical system requires significant engineering work to design custom interface logic Integra?ng design blocks and intellectual property (IP) is tedious and error- prone 3

4 4 Introducing Qsys

5 Automa?c Interconnect Genera?on Processor (32-bit Master) PCI Express (64-bit Master) Address Decoder Bus Interface Address Data Arbiter Interrupt Controller Bus Interface Address Qsys automatically generates interconnect Data Width Adapter Width Adapter Width Adapter Width Adapter Width Adapter Bus Interface Bus Interface Bus Interface Bus Interface Bus Interface Slave 1 8-Bit Slave 2 32-Bit Slave 3 16-Bit Avoids error- prone integra?on Saves development?me with automa?c logic & HDL genera?on Enables you to focus on value- add blocks Slave 4 32-Bit Slave 5 64-Bit 5

6 Qsys Benefits Simplifies complex system development Automa?c interconnect genera?on Raises the level of design abstrac?on High level design and system visualiza?on Provides a standard plavorm: IP integra?on, custom IP authoring, IP verifica?on Enables design re- use Scales easily to meet the needs of end product Reduces?me to market Reduces design development?me Eases verifica?on 6

7 Easy- to- Use System Integra?on UI Library of Available IP n Interface protocols n Memory n DSP n Embedded n Bridges n PLL n Custom systems Connect IP and Systems IP 1 Custom 1 IP 2 IP 3 Custom 2 Accelerate Development HDL Simplify Integration Automate Error-Prone Integration Tasks 7

8 Design Re- Use Qsys enables re- use of IP and systems with IP management capabili?es Project A Top top top Project B Package as IP Add to library Top Qsys Project C Top 8

9 Target Qsys Applica?ons Qsys can be used in almost every FPGA design Designs fall into two categories Control plane Memory mapped Reading and wri?ng to control and status registers Data plane Streaming Data switching (muxing, demuxing), aggrega?on, bridges Applica?ons include video and image processing, high- speed interfaces, embedded and memory 9

10 Processor Required? What if your design does not require a processor? Qsys systems do not require a processor Other components can ini?ate transfer requests and exert system control Memory- mapped components use master slave e.g. state machine, direct memory access (DMA) Streaming data uses source sink e.g. video camera, pa[ern generator So\ Processors (e.g. Nios II) or external processors may be connected to the Qsys Interconnect 10

11 Qsys vs. SOPC Builder Similari?es IP integra?on with switch fabric connec?vity Dynamic system genera?on High level system visualiza?on Custom IP authoring IP verifica?on and bus func?onal models (BFMs) Simula?on support for ModelSim Real-?me system debug 11

12 Qsys vs. SOPC Builder Differences In addi;on to SOPC Builder capabili;es, Qsys adds: High- performance interconnect Hierarchy Industry standard interfaces IP management capabili?es High-Performance Interconnect Hierarchy Industry-Standard Interfaces Design System Based on Network-on-Chip architecture Avalon Interfaces IP Management Package AMBA AXI as IP Add to Library (design reuse) 12

13 Increasing the Level of Abstrac?on Abstraction & Improved Productivity Level Low Medium High Block Block Block Block IP IP IP IP System System System System Design Block Integration Schematic Entry Tool SOPC Builder Tool IP Integration Design a system with IPs IP re-use IP verification System Integration Design a system with systems System re-use System verification Qsys System Integration Tool 13

14 SOPC Builder Systems in Qsys Qsys can open SOPC Builder files Qsys will transform SOPC Builder system into Qsys system.sopc file maintained Cleanup op?on available 14

15 Agenda What is Qsys? Qsys UI Using Qsys in FPGA design flow Qsys files Qsys Intellectual Property(IP) 15

16 Component Library System Contents System Inspector Address Map Clock Seangs Project Seangs Genera?on HDL Example Messages Qsys UI Overview 16

17 Open Qsys from Quartus II So\ware Quartus II so\ware Tools Menu Select Qsys Open or create new Qsys system Can also open.qsys file from Quartus II File menu 17

18 Qsys System- Integra?on Tool Qsys tabs Component Library System Contents Messages 18

19 Component Library Lists available IP and systems Type search string to filter the list Reuse previous systems hierarchy Expand categories to browse components Double-click component or click Add button to add selected component to system 19

20 Qsys UI: System Contents Tab Displays components and subsystems Use to add/remove/connect components System Components Enable/disable components 20

21 System Contents: Component Interfaces Number of independent interfaces with which component communicates with rest of system Clock and reset considered separate interfaces 21

22 System Contents: Connec?ons Panel Use Connec?ons panel to specify interface connec?vity Clocks, resets Masters and slaves Sources and sinks Interrupt senders and receivers Custom instruc?on senders and receivers Each dot represents a connec?on between two interfaces Qsys generates system interconnect based on this configura?on Direc?on shown with arrows Hide connec?ons for added readability Collapsing components Using filters 22

23 System Contents: Exports Explicitly export interfaces Choose interfaces to connect outside Qsys system Any interface can be exported Managed in Export column Click interface to export, then type name Exported interfaces displayed with pin icon 23

24 System Contents: Clocks Clock Source component Defines input clock(s) to system Connect two interfaces Clock Input interface fed from outside system (export) Clock Output interface connects to Clock Input interface of other system components 24

25 System Contents: Resets 1. Manually connect each reset interface User has more control over reset implementa?on Reset only subset of the components in system Must use care to avoid reset loops and system lockup MM Slave reset in middle of transac?on, Master waits forever Reset interfaces declared independent of clock interface S?ll associated with a clock interface Reset synchronized to associated clock Mul?ple resets can enter the system, like clocks Uses Reset Controller Block (later) 2. Choose Create Global Reset Network from System menu Automa?cally connects all Reset Inputs 25

26 Reset Connec?on Points External reset input interface Reset Output interface drives Reset Input interfaces of other system components 26

27 System Contents: Conduit Interfaces Conduits are used for any non- standard interfaces (groups of signals) User must manually specify signals that make up conduit interface Like- typed conduits can be connected in the UI Same signals with opposite direc?ons May be exported outside system 27

28 System Contents: Addressing Each memory- mapped master interface has own address map When slave ports are shared, the address map converges Maximum 32- bit address space (4GB) for each master interface Master address map is a collec?on of the following Connected slave interface base addresses Connected slave interface address spans (determines end address) Lowest and highest slave addresses make up the address space of the master Manually assign slave addresses Double- click or let Qsys auto- assign Master interface 28 Master address space based on connected slaves

29 Qsys UI: Address Map Tab Table of memory- mapped addresses Double- click cell to manually edit slave addressing Supports per- master addressing for shared slaves Single slave represented by different address ranges for different masters Master interfaces represented by columns 29 Slave interfaces represented by rows

30 Qsys UI: Clock Seangs Tab Use for further clock management Add new clocks to system Rename system clocks for readability Specify clock frequencies Must also create proper TimeQuest SDC constraints Double-click to change name or frequency (non-pll) 30

31 Qsys UI: Project Seangs Tab Control interconnect implementa?on Handshake, FIFO, or Auto clock domain crossing logic Pipelining in interconnect 31

32 Instance Parameters Define parameters and associated script that configures instan?a?ons of current system Discussed in the Advanced Qsys System Integra?on Tool Methodologies class Used in hierchical systems 32

33 Qsys UI: System Inspector Tab Review system and component details System hierarchy Top- level system connec?on Component interfaces Connec?ons between components Component details Edit component seangs 33

34 System Inspector System View System level settings Top-level symbol diagram 34

35 System Inspector Exported Interface All exported interfaces Selected exported interface 35

36 System Inspector Connec?ons Connection type Selected connection properties All interface connections 36

37 System Inspector Submodules Selected component parameter editor settings* All system components * Some wizard settings can be edited 37

38 System Inspector Submodule Interface Selected interface type Components interfaces Selected interface settings including timing waveforms 38

39 Qsys UI: HDL Example Tab Creates Verilog or VHDL instan?a?on template Use to instan?ate Qsys system as a submodule in design 39

40 Qsys UI: Genera?on Tab Choose what files to generate (Simula?on, synthesis, or symbol) Choose Output Directory Path (default is subdirectory) Click Generate bu[on (bo[om of tab) 40

41 Qsys UI: Messages Documents system error, warning and informa?on messages Includes summary of error and warning counts 41

42 Addi?onal UI Features System edi?ng Filtering Auto- assignments and inser?ons 42

43 System Edi?ng Remove components from system Highlight component and click X bu[on Highlight component and hit Delete key Change order of components in system Arrange components in System Contents tab to make system and component connec?ons more easily understandable Does not change addressing or connec?ons 43

44 Filtering Filter System Contents display based on Component name Interface type Connec?on source/des?na?on Default filter is all components and all interfaces except interrupts Select pre- defined filters by right- clicking on any component or interface in System Contents Create new custom filters by clicking on Filter bu[on and defining filter criteria 44

45 Other Useful Qsys Commands Accessible from the File menu Refresh System Refreshes all IP and components to detect any changes Accessible from System menu Assign Base Addresses Automa?cally eliminates conflicts in slave addressing Create Global Reset Network Insert Avalon - ST Adapters Automa?cally inserts adapters between source and sinks to compensate for differences (e.g?ming, data width, data format, error flags) Remove Dangling ConnecLons Removes unconnected connec?on lines (interfaces) from ac?ve components in the System Contents tab 45

46 Agenda What is Qsys? Qsys UI Using Qsys in FPGA design flow Qsys files Qsys Intellectual Property(IP) 46

47 FPGA Hardware Design Flow Design Specification LE M4K M512 I/O Qsys System Integration Tool Design Entry/RTL Coding - Behavioral or Structural Description of Design RTL Simulation - Functional Simulation (Modelsim, Quartus II software) - Verify Logic Model & Data Flow (No Timing Delays) Synthesis - Translate design into device specific primitives - Optimization to meet required area & performance constraints - Quartus II software or other supported synthesis tools Place & Route - Map primitives to specific locations inside - Target technology with reference to area & performance constraints - Specify routing resources to be used 47

48 FPGA Hardware Design Flow t clk Timing Analysis - Verify performance specifications were met - TimeQuest static timing analysis Gate Level Simulation - Timing simulation - Verify design will work in target technology Test FPGA on PC Board - Program & test device on board - Use Quartus II tools (e.g. Signaltap II logic analyzer) for debugging 48

49 Qsys System Genera?on 1. Create Qsys system 2. Generate HDL files for synthesis on GeneraLon tab Generates HDL files into a synthesis subdirectory 3. Set top- level project en?ty Instan?ate Qsys system as sub- block in another design file or specify Qsys system name as top- level design en?ty 4. Add generated.qip file to Quartus II project Adds all required generated HDL files 5. Constrain design 6. Compile design Use Qsys to make changes to system, rather than edi?ng any generated HDL 49

50 Agenda What is Qsys? Qsys UI Using Qsys in FPGA design flow Qsys files Qsys Intellectual Property(IP) 50

51 Qsys Source Files.qsys file Each.qsys file represents a single Qsys system (components, connec?ons and parameteriza?ons) All other files for Qsys system created during system genera?on Can use mul?ple Qsys files in a single Quartus II project (hierarchy) 51

52 Qsys Output Files Top- level folder files <system_name>.sopcinfo XML file describing Qsys system used for so\ware development tools <system_name>.bsf Symbol file for Quartus II schema?c editor (op?onal) <system_name>.html Genera?on report including output files generated, component list, etc. Files for synthesis Located in <system_name>/synthesis folder <system_name>.qip Script file that adds all files needed for synthesis to Quartus II project <system_name>.v Qsys system top- level file connec?ng all components together (Verilog only) Submodule files for synthesis Located in submodule folder Combina?on of Verilog, SystemVerilog and/or VHDL files represen?ng system.sdc?ming constraint files may also be generated (add to Quartus II project) Files for simula?on Discussed later 52

53 Qsys Output Files Example project (folder) sm_transfer_system.qsys sm_transfer_system.sopcinfo sm_transfer_system.bsf sm_transfer_system.html sm_transfer_system (folder) synthesis (folder) sm_transfer_system.qip sm_transfer_system.v submodules (folder) component.v,.vhd and.sv files component.sdc 53

54 Agenda What is Qsys? Qsys UI Using Qsys in FPGA design flow Qsys files Qsys Intellectual Property(IP) 54

55 Component Library Review Lists available IP and systems Type search string to filter the list Reuse previous systems hierarchy Expand categories to browse components Double-click component or click Add button to add selected component to system 55

56 Component Library Parameter Editors A\er clicking Add, configure component op?ons and interfaces before adding to system IP_Compiler for PCI Express PLL Parameter Editor On-Chip FIFO Parameter Editor 56

57 IP Components Basic components Streaming components Memory components Tristate components Bridge components High- speed interface components Processor components 57

58 Clock source Basic IP Components Defines external clock inputs to the system Reset bridge Use when component - generated reset must be connected to internal logic and be exported Qsys does not allow interfaces to be exported and connected inside system Component reset Reset Bridge To reset input interfaces Exported reset 58

59 Streaming IP Components Use to manipulate data flows in streaming systems Demul?plexer Mul?plexer Channel adapter Data format adapter Timing adapter Delay Spli[er 59

60 On- chip Memory IP Components On- chip RAM/ROM On- chip FIFO Off- chip SDRAM Controller DDR/DDR2/DDR3 Controller QDRII/QDRII+ SRAM Controller RLDRAM II Controller Flash Interfaces 60

61 DMA Direct Memory Access (DMA) Perform bulk data transfers between Avalon- MM address ranges Sca[er- gather DMA Perform bulk data transfers and merges between non- con?guous memory and con?nuous address space 61

62 Tri- State IP Components Generic tri- state controller Represents any controller block that uses tri- states Tri- state pin sharer Allows mul?ple off- chip devices to share FPGA pins Tri- state bridge Bridges unidirec?onal core signals and tri- state I/O signals Must be used to connect to off- chip tri- state devices 62

63 Bridge IP Components Avalon- MM clock crossing bridge Uses FIFOs for buffered high- throughput clock domain crossing from Avalon- MM master to slave Avalon- MM pipeline bridge Specify pipelining of command and response segments Control interface topology with or without pipelining Allow expor?ng of mul?ple MM interfaces through one aggregate interface JTAG to Avalon master bridge Uses JTAG commands to access and control Qsys components SPI slave to Avalon master bridge Uses SPI interface to access and control Qsys components 63

64 High- Speed Interface IP IP_Compiler for PCI Express* 10/100/1000 Mb (Triple- Speed) Ethernet 10Gb Ethernet Interlaken RapidIO * All except for IP_Compiler for PCI Express require additional licensing to use in finished product. 64

65 IP_Compiler for PCI Express Configures Hard IP for PCI Express and embedded transceivers Performs transac?on, data link, PHYMAC layer and func?onality Supports PCI Express Gen 2 (5.0 Gbps) & Gen 1 (2.5 Gbps) Supports root port and endpoint applica?ons Connects directly to FPGA logic using Avalon- MM master and slave interfaces FPGA PCI Express Hard IP Block Avalon-MM data &control interfaces Transaction Layer Data Link Layer PHYMAC Layer PIPE Embedded Transceiver Block Transceiver Block n Transceiver Block 2 Transceiver Block 1 Transceiver Block 0 To / from Slot or cable 65

66 Processor IP Components Nios II processor Altera s second genera?on so\- core 32 bit RISC microprocessor Licenses MegaCore func?on Nios II instructor- led classes: Designing with the Nios II Processor Developing SoRware for the Nios II Processor 66

67 Informa?on for Exercise PCIe transactions targeting bar0 translated to Avalon-MM transfers sent to the on-chip memory. PCIe transactions targeting bar1 translated to Avalon-MM transfers sent to DMA control and PCIe core CRA. Programmed DMA can transfer data between on-chip memory and PCIe core (tx_out) to be converted to PCIe transactions. DMA read write Master interface PCI Express IP Core control On-Chip Memory Slave interface bar0 bar1 CRA tx_out 4 PCIe Link data Qsys Connections - Avalon-MM Master or Master/Slave Component - Avalon-MM Slave Component 67

68 Step 1: Create Quartus II project(1) 11_1.png

69 Step 1: Create Quartus II project(2)

70 Step 1: Create Quartus II project(3)

71 Step 2: Start Qsys

72 Step 3: add a Hard IP for PCI Express func?on to the system(1)

73 Step 3: add a Hard IP for PCI Express func?on to the system(2) Configure the general, system-related settings. In the PCIe System Settings section of the IP_Compiler for PCI Express editor, choose the following options: Select x1 for the number of Lanes. Select 100 MHz for the Reference clock frequency. Select 64bits for the Test out width. Leave both the Gen2 Lane Rate Mode and Enable 62.5 Mhz application clock options de-selected.

74 Step 3: add a Hard IP for PCI Express func?on to the system(3) Configure the PCIe Base Address Registers (BARs) for this endpoint. Go to the PCI Base Address Registers (Type 0 Configuration Space) section of the IP_Compiler for PCI Express editor and choose the following options: Verify BAR 0 (the first row) has been set to 64 bit Prefetchable. The BAR type for BAR 1 should read: 1 - Occupied. Click on the BAR Type field for BAR 2 (i.e. row 3). From the drop -down menu that appears, select 32-bit Non-Prefetchable. Leave the BAR Size and Avalon Base Address fields set to their defaults.

75 Step 3: add a Hard IP for PCI Express func?on to the system(4) Configure the PCIe Read-Only Registers for this endpoint. Go to the Device Identification Registers section of the IP_Compiler for PCI Express editor and ensure the following options are set: The Vendor ID to 0x1172. The Device ID to 0xE001. The Revision ID to 0x09. The Class code to 0xFF0000. The Subsystem vendor ID to 0x1172. The Subsystem ID to 0x01144.

76 Step 3: add a Hard IP for PCI Express func?on to the system(5) Configure the Buffer Configuration settings. Go to the Buffer Configuration section of the IP_Compiler for PCI Express editor and choose the following options: For Maximum Payload Size, use the drop-down menu to select 256 Bytes. For the Desired performance for received requests, select High.

77 Step 3: add a Hard IP for PCI Express func?on to the system(6) Configure the Avalon-MM interface to the embedded system. Go to the Avalon MM Settings section of the IP_Compiler for PCI Express editor. Choose the following: For Peripheral Mode, use the drop-down menu to select Requester /Completer. Enable the Control Register Access (CRA) Avalon slave port option. Leave the Auto Enable PCIe Interrupt (enabled at power-on) and Disable Auto Reordering for Rx Completion TLP s options disabled.

78 Step 3: add a Hard IP for PCI Express func?on to the system(7) Configure the Avalon address translation. Go to the Address Translation section of the IP_Compiler for PCI Express editor. Choose the following options: For the Address Translation Table Configuration, use the drop-down menu to select Dynamic translation table. Select 2 as the Number of address pages. Select 1 MByte 20 bits for the Size of address pages.

79 Step 3: add a Hard IP for PCI Express func?on to the system(8)

80 Step 4: Add DMA Controller(1)

81 Step 4: Add DMA Controller(2)

82 Step 4: Add DMA Controller(3)

83 Step 5: Add on- chip Memory(1)

84 Step 5: Add on- chip Memory(2)

85 Step 5: Add on- chip Memory(3)

86 Step 6: Connect the component interfaces(1)

87 Step 6: Connect the component interfaces(2)

88 Step 6: Connect the component interfaces(3)

89 Step 6: Connect the component interfaces(4)

90 Step 6: Connect the component interfaces(5) Export the calibration block interface of the Hard IP for PCIe. In the System Contents tab, highlight the cal_blk_clk interface of the pcie_hard_ip_0 component. Click in the Export column and confirm the exported name for this interface is pcie_hard_ip_0_cal_blk_clk. Type the name, if necessary. Hit Enter when finished.

91 Step 6: Connect the component interfaces(6)

92 Step 6: Connect the component interfaces(7)

93 Step 7: Adjust System Addresses(1) Set the address of the pcie_hard_ip_0 component s Control Register Access port to 0x On the System Contents tab, locate the Base address column. For the cra interface of the pcie_hard_ip_0 component, confirm that the address is set to 0x Change, if necessary, by double-clicking in the Base address field and typing in the address.

94 Step 7: Adjust System Addresses(2)

95 Step 8: Choose final seangs and generate the Qsys system(1) Review the system clock settings. On the Clock Settings tab, verify that the pcie_hard_ip_0 component is generating a 125 MHz clock for the system. Establish final Qsys settings. On the Project Settings tab, review the block diagram to make sure all of your exported interfaces are visible. In the Parameters section, choose the following options: Device Family: Arria II GX Clock crossing adapter type:fifo Limit interconnect pipeline stages to:2 Generation ID: 0 Generate the system. On the Generation tab, leave all options in the Simulation section set to None. In the Synthesis section, enable both options to Create HDL design files for synthesis and to Create block symbol file (.bsf). Click Generate.

96 Step 8: Choose final seangs and generate the Qsys system(2) Generate the system. On the Generation tab, leave all options in the Simulation section set to None. In the Synthesis section, enable both options to Create HDL design files for synthesis and to Create block symbol file (.bsf). Click Generate.

97 Step 9:Incorporate into top- level file and compile(1)

98 Step 9:Incorporate into top- level file and compile(2)

99 Step 9:Incorporate into top- level file and compile(3)

100 Step 9:Incorporate into top- level file and compile(4)

101 Step 9:Incorporate into top- level file and compile(5)

102 Step 9:Incorporate into top- level file and compile(6)

103 Step 9:Incorporate into top- level file and compile(7)

104 Step 9:Incorporate into top- level file and compile(8)

105 Step 9:Incorporate into top- level file and compile(9)

106 Digital Video Design and Implementation Skills Using FPGA

107 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

108 Ø Basic Design on DE2-115 Composite Input TV Decoder VGA DAC SDRAM Cyclone IV FPGA 4CE115

109 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

110 Ø TV Decoder VSync HSync Field Composite (Analog) A/DC Digital Decoder Y Cb Cr

111 Ø TV Decoder Programming Output 13.5MHz xx xx xx xx xx Y 0 Y 1 xx Cb 0 Cr 1 + Hsync + Vsync + Field 27MHz xx xx xx xx xx xx + Hsync + Vsync + Field Cb 0 Y 0 Cr 1 Y 1 27MHz xx xx FF SAV Cb 0 Y 0 Cr 1 Y 1

112 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

113 Ø Input Format:ITU-R656 End Start Video Data FF0000:Control Code Header XY: Field/Vertical-Active/Vertical-Active Indicator

114 Ø Decoder ITU-R656 Data Stream 0 Cb ITU656 Data 1, 3 2 Y Cr SAV(Reset) 27MHz 2-bit Counter

115 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

116 Ø What is Interlaced Scan? Upper Field Lower Field Interlace Scan Progressive Scan

117 Ø Why is Interlaced Scan?

118 Ø De-interlaced Method n Video mode. Ø Intra-Field (Bob or Interpolation or ELA) Ø Inter-Field (Blend or Weave) Ø Motion Adaptive Ø Motion Compensation n Film mode. Ø 3:2 Pull-Down (NTSC) Ø 2:2 Pull-Down (PAL)

119 Video Mode Ø Intra-Field:Bob Ø Method: Advantage: Duplicate Video no loss. each Line line buffer for each only. field. No extra judgment. Ø Disadvantage: Less resolution. Source Jagged. Output Shake. Odd 001 Odd 001 Odd 001 Odd 002 Odd 002 Source Odd 002 Line n+1 Odd 239 Odd 240 Odd 239 Odd 239 Odd 240 Odd 240 Even 001 Even 002 Line Buffer Line Time Buffer Source Even 239 Even 240 Output Even 001 Even 001 Even 002 Even 002 Output Line 2n/2n+1 Even 239 Even 239 Even 240 Even 240

120 Video Mode Ø Intra-Field:Interpolation Ø Method: Advantage: Interpolate Video no loss. the Line new buffer line from only. the No scan extra lines judgment. for each field. Ø Disadvantage: Source Output Less resolution. Jagged. Odd 001 Odd 001 Avg (Odd 001/002) Odd 002 Odd 002 Avg (Odd 002/003) Source Line n+1 Odd 239 Odd 240 Odd 239 Line Buffer Time Avg (Odd239/240) Odd 240 Odd 240 Line Buffer Line Buffer Even 001 Even 002 Source Even 239 Even 240 Output Even 001 Even 001 Avg (Even 001/002) Even 002 Output Line 2n-3/2n-2/2n-1 Avg (Even 238/239) Even 239 Avg (Even 239/240) Even 240 Line 2n-1/2n/2n+1

121 Video Mode Ø Inter-Field:Weave Ø Memory: Method: Field Merge buffer the odd needed. and even field. Source Odd1 001 Odd1 002 Odd1 239 Odd1 240 Time Even1 001 Even1 002 Even1 239 Even1 240 Time Odd2 001 Odd2 002 Odd2 239 Odd2 240 Time Even2 001 Even2 002 Even2 239 Even2 240 Output Odd1 001 Even1 001 Odd1 002 Even1 002 Odd1 239 Even1 239 Odd1 240 Even1 240 Odd2 001 Even1 001 Odd2 002 Even1 002 Odd2 239 Even1 239 Odd2 240 Even1 240 Odd2 001 Even2 001 Odd2 002 Even2 002 Odd2 239 Even2 239 Odd2 240 Even2 240

122 Video Mode Ø Inter-Field:Blend Ø Memory: Method: Field Resize buffer the average needed. odd and even field. Source Odd1 001 Odd1 002 Odd1 239 Odd1 240 Time Even1 001 Even1 002 Even1 239 Even1 240 Time Odd2 001 Odd2 002 Odd2 239 Odd2 240 Time Even2 001 Even2 002 Even2 239 Even2 240 Output Avg (Odd1 001/Even1 001) Avg (Odd1 001/Even1 001) Avg (Odd1 002/Even1 002) Avg (Odd1 002/Even1 002) Avg (Odd1 239/Even1 239) Avg (Odd1 239/Even1 239) Avg (Odd1 240/Even1 240) Avg (Odd1 240/Even1 240) Avg (Odd2 001/Even1 001) Avg (Odd2 001/Even1 001) Avg (Odd2 002/Even1 002) Avg (Odd2 002/Even1 002) Avg (Odd2 239/Even1 239) Avg (Odd2 239/Even1 239) Avg (Odd2 240/Even1 240) Avg (Odd2 240/Even1 240) Avg (Odd2 001/Even2 001) Avg (Odd2 001/Even2 001) Avg (Odd2 002/Even2 002) Avg (Odd2 002/Even2 002) Avg (Odd2 239/Even2 239) Avg (Odd2 239/Even2 239) Avg (Odd2 240/Even2 240) Avg (Odd2 240/Even2 240)

123 Film Mode Ø 3:2 Pull Down Detection 0 24frames/sec 3 60fields/sec Error Error X Error X 9 X 6 Error 8 odd even odd even odd even odd even odd even Still 4 Scan Code Scan = Code Scan 0 = Code Scan Check = Code Scan ok = Code Scan = Code = ?? Scan Code = X

124 Film Mode Ø PAL:2:2 Pull Down 24frames/sec 50fields/sec

125 Film Mode Ø 2:2 Pull Down Detection Error 1 Error motion 1 0 Sawtooth Still odd1 2 even1 odd2 Check ok If sawtooth_even1 > threshold, then sawtooth detected!

126 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

127 Ø Scaler Digital Video Source Buffer Digital Rescaling Algorithm LCD Display Rescaling

128 Ø 4:3 => 16:9 Original 4:3 Image 4:3 Image Fit on 16:9 Display Simple Linear Scaling Non-Linear Horizontal Scaling

129 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

130 Ø Color Space Conversion u YCbCr to RGB R = 1.164(Y-16) (Cr-128) G = 1.164(Y-16) (Cb-128) (Cr-128) B = 1.164(Y-16) (Cb-128) = 1 + 1/ / / = 1 + 1/2 + 1/ / = 1/ / / = 1/2 + 1/ / = 2 + 1/2 6

131 Ø Basic Digital TV Design Composite Input Altera FPGA VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

132 Ø VGA Timing Vertical Sync VGA MONITOR

133 Ø VGA Controller Architecture H-Sync DATA X Y Source Clock H-Sync Generator Pixel Clock H-Counter Pixel Clock PLL Memory X DATA Request V-Sync Generator V-Counter VGA Data Control V-Sync Y R G B

134 Ø Video Quality? Composite Input VGA Timing VS HS TV Decoder ITU-R 656 Decoder De- Interlace Scaler YCbCr to RGB R G B VGA DAC SCLK SDATA I 2 C Controller SDRAM

135