±10V, 12-Bit, Serial, Voltage-Output DAC

Transcription

1 9-39; Rev ; 2/3 ±V, 2-Bit, Serial, Voltage-Output DAC General Description The 2-bit, serial-interface, digital-to-analog converter (DAC) provides bipolar ±5V to ±V outputs from ±2V to ±5V power-supply voltages, or a unipolar 5V to V output from a single 2V to 5V powersupply voltage. The features excellent linearity with both integral nonlinearity (INL) and differential nonlinearity (DNL) guaranteed to ± LSB (max). The device also features a fast µs to.5 LSB settling time, and a hardwareshutdown feature that reduces current consumption to 3.5µA. The output goes to midscale at power-up in bipolar mode (V), and to zero scale at power-up in unipolar mode (V). A clear input (CLR) asynchronously clears the DAC register and sets the output to V. The output can be asynchronously updated with the load DAC (LDAC) input. The device features a MHz SPI -/QSPI -/ MICROWIRE -compatible serial interface that operates with 3V or 5V logic. Additional features include a serial-data output (DOUT) for daisy chaining and readback functions. The requires a 2V to 5.25V external reference voltage and is available in a 6-pin SSOP package that operates over the extended -4 C to +85 C temperature range. Motor Control Industrial Process Controls Industrial Automation Automatic Test Equipment (ATE) Analog I/O Boards Data-Acquisition Systems Applications Features Unipolar or Bipolar Output-Voltage Ranges Unipolar: to (+2 x V REF ) (Single or Dual Supply) Bipolar: (-2 x V REF ) to (+2 x V REF ) (Dual Supply) Guaranteed INL ± LSB (max) Guaranteed Monotonic: DNL ± LSB (max) µs Settling Time to.5 LSB Low 3.5µA Shutdown Current MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Power-On Reset Sets DAC Output to V Schmitt Trigger Inputs for Direct Optocoupler Interface Serial-Data Output Allows Daisy Chaining of Devices Small 6-Pin SSOP Ordering Information PART TEMP RANGE PIN-PACKAGE EAE -4 C to +85 C 6 SSOP TOP VIEW Pin Configuration SCLK 6 LDAC DIN 2 5 CLR 3 4 V DD DOUT 4 3 REF DGND 5 2 V SS V CC 6 AGND SHDN 7 SGND UNI/BIP 8 9 OUT SSOP SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS V DD to AGND...-.3V to +7V V SS to AGND...-7V to +.3V V DD to V SS...+34V V CC to DGND...-.3V to +6V AGND to DGND...-.3V to +.3V SGND to AGND...-.3V to +.3V SCLK, DIN,, SHDN, UNI/BIP, CLR, LDAC, DOUT to DGND...-.3V to (V CC +.3V) OUT to AGND...(V SS -.3V) to (V DD +.3V) REF to AGND...-.3V to +6V Maximum Current into REF...±mA Maximum Current into Any Pin Excluding REF...±5mA Continuous Power Dissipation (T A = +7 C) 6-Pin SSOP (derate 7.mW/ C above +7 C)...57mW Operating Temperature Range...-4 C to +85 C Junction Temperature...+5 C Storage Temperature Range C to +5 C Lead Temperature (soldering, s)...+3 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTI (DUAL SUPPLY) (V DD = +5V ±5%, V SS = -5V ±5%, V CC = +5V ±%, AGND = DGND = SGND = V, V REF = 5V, R LOAD = 2kΩ, C LOAD = 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N 2 Bits Integral Nonlinearity INL ± LSB Differential Nonlinearity DNL Guaranteed monotonic ± LSB Zero-Scale Error Bipolar, code = 8hex ± Unipolar, code = hex ±2 Zero-Scale Temperature Bipolar.3 Coefficient Unipolar.5 Gain Error Bipolar, no load ±2 Unipolar, no load ±2 Gain-Error Temperature Bipolar, no load 2 Coefficient Unipolar, no load 2 ANALOG OUTPUT (OUT) Output Voltage Range (V SS +.5V) < < (V DD -.5V) Resistive Load to GND R LOAD 2 kω Capacitive Load to GND C LOAD 25 pf DC Output Resistance.5 Ω SGND INPUT (SGND) Input Impedance 92 kω REFERENCE INPUT (REF) Reference-Voltage Input Range V -2 x V REF Code = 555hex, worst-case code 5 22 Input Resistance R REF Shutdown x V REF LSB ppm FSR/ C LSB ppm FSR/ C Reference Bandwidth V REF = 2mV P-P + 5VDC 2 khz V kω 2

3 ELECTRICAL CHARACTERISTI (DUAL SUPPLY) (continued) (V DD = +5V ±5%, V SS = -5V ±5%, V CC = +5V ±%, AGND = DGND = SGND = V, V REF = 5V, R LOAD = 2kΩ, C LOAD = 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN,, SHDN, UNI/BIP, CLR, LDAC) +2.7V V CC +3.6V Input-Voltage High VIH +4.5V V CC +5.5V x V CC V +2.7V V CC +3.6V.6 Input-Voltage Low V IL +4.5V V CC +5.5V.8 V Input Capacitance Input Current (Note ) DIGITAL OUTPUT (DOUT) C +2.7V V CC +3.6V +4.5V V CC +5.5V all digital inputs V CC, +2.7V V CC +3.6V all digital inputs V CC, +4.5V V CC +5.5V Output-Voltage High V OH I SOURCE = 2mA Output-Voltage Low V OL I SINK = 2mA.4 V Tri-State Leakage Current.2 µa Tri-State Capacitance pf DYNAMIC PERFORMANCE Voltage-Output Slew Rate 2.5 V/µs Output Settling Time To ±.5 LSB of full scale, code to code FFF V CC -.5 ± ± pf µa V µs Digital Feedthrough = high, f SCLK = MHz, = V nv-s Output-Noise Spectral Density at khz POWER SUPPLIES 3 nv/ Hz Positive Analog-Supply Voltage V DD V Negative Analog-Supply Voltage V SS V Positive Digital-Supply Voltage V CC V Positive Analog-Supply Current I DD Output unloaded, = FS.8 4 ma Negative Analog-Supply Current I SS Output unloaded, = FS.75-2 ma Digital-Supply Current I CC All digital inputs = or V CC 3 2 µa Power-Supply Rejection Ratio (Note 2) Shutdown Current PSRR Positive analog supply.4 Negative analog supply.6 Positive analog supply.7 5 Negative analog supply Digital supply 3.5 LSB/V µa 3

4 ELECTRICAL CHARACTERISTI (SINGLE SUPPLY) (V DD = +5V ±5%, V SS = V, V CC = +5V ±%, AGND = DGND = SGND = V, V REF = 5V, R LOAD = kω, C LOAD = 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS STATIC ACCURACY Resolution N 2 Bits Integral Nonlinearity INL (Note 3) ± LSB Differential Nonlinearity DNL Guaranteed monotonic ± LSB Unipolar Zero-Scale Error Code = 4hex ±2 LSB Unipolar Zero-Scale Temperature Coefficient Code = 4hex.5 Gain Error No load ±2 LSB Gain-Error Temperature Coefficient ANALOG OUTPUT (OUT) No load 2 Output Voltage Range Resistive Load to GND R LOAD kω Capacitive Load to GND C LOAD 25 pf DC Output Resistance.5 Ω SGND INPUT (SGND) Input Impedance 92 kω REFERENCE INPUT (REF) Reference-Voltage Input Range V Input Resistance Code = 555hex, worst-case code 5 22 kω Reference Input Bandwidth V REF = 2mV P-P + 5V DC 5 khz DIGITAL INPUTS (SCLK, DIN,, SHDN, UNI/BIP, CLR, LDAC) +2.7V V CC +3.6V Input-Voltage High VIH +4.5V V CC +5.5V x V CC +2 x V REF ppm FSR/ C ppm FSR/ C V V +2.7V V CC +3.6V.6 Input-Voltage Low V IL +4.5V V CC +5.5V V V CC +3.6V Input Capacitance C IN +4.5V V CC +5.6V V IN V CC, +2.7V V CC +3.6V ± Input Current I IN V IN V CC, +4.5V V CC +5.5V ± V pf µa DIGITAL OUTPUT (DOUT) Output-Voltage High V OH I SOURCE = 2mA Output-Voltage Low V OL I SINK = 2mA.4 V Tri-State Leakage Current.2 µa V CC -.5 V 4

5 ELECTRICAL CHARACTERISTI (SINGLE SUPPLY) (continued) (V DD = +5V ±5%, V SS = V, V CC = +5V ±%, AGND = DGND = SGND = V, V REF = 5V, R LOAD = kω, C LOAD = 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Tri-State Capacitance pf DYNAMIC PERFORMANCE Voltage-Output Slew Rate 2.5 V/µs Output Settling Time To ±.5 LSB of full scale, code 4hex to code FFF µs Digital Feedthrough = high, f SCLK = MHz, = V nv-s Output-Noise Spectral Density at khz POWER SUPPLIES 3 nv/ Hz Positive Analog-Supply Voltage V DD V Negative Analog-Supply Voltage V SS V Positive Digital-Supply Voltage V CC V Positive Analog-Supply Current I DD Output unloaded, =.8 4 ma Negative Analog-Supply Current I SS Output unloaded, =.75-2 ma Digital-Supply Current I CC All digital inputs = or V CC 3 2 µa Power-Supply Rejection Ratio PSRR V DD = 4.5V to 5.5V, code FFF.4 LSB/V Shutdown Current Analog supply.7 5 Digital supply 3.5 µa 5

6 TIMING CHARACTERISTI (V DD = +5V, V SS = -5V or V, V CC = +2.7V to +5.5V, AGND = DGND = SGND =, V REF = 5V, R LOAD = 2kΩ, C LOAD = 25pF, T A = T MIN to T MAX, unless otherwise noted. Typical values are at T A = +25 C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Frequency MHz SCLK Clock Period t CP ns SCLK Pulse-Width High t CH For nondaisy-chain use 45 ns SCLK Pulse-Width Low t CL For nondaisy-chain use 45 ns Fall to SCLK Rise Setup Time t S 4 ns +2.7V V CC +3.6V 5 SCLK Rise to Rise Hold Time t H +4.5V V CC +5.5V ns DIN Setup Time t DS 2 ns DIN Hold Time t DH ns LDAC Pulse Width t LD 5 ns +2.7V V CC +3.6V Rise to LDAC Low Setup Time t LDS +4.5V V CC +5.5V 5 SCLK Fall to DOUT Valid Propagation Delay C LOAD = 2pF, +2.7V V CC +3.6V t DO C LOAD = 2pF, +4.5V V CC +5.5V 8 SCLK Rise to Fall Delay t ns Low to DOUT Valid Time t E C LOAD = 2pF 2 ns High to DOUT Disabled Time t D 2 ns Rise to SCLK Rise Hold Time t 5 ns +2.7V V CC +3.6V 2 Pulse-Width High t W +4.5V V CC +5.5V CLR Pulse-Width Low t CLR 5 ns Note : Output unloaded, digital inputs = V CC or DGND. Note 2: V DD = +4.5V to +5.5V, V SS = -5.5V to -4.5V, code = FFF. Note 3: Measured from code 4hex to FFFhex. ns ns ns 6

7 Typical Operating Characteristics (V DD = +5V, V SS = -5V for bipolar graphs, V SS = for unipolar graphs, V CC = +5V, AGND = DGND = SGND =, V REF = +5.V, output unloaded, T A = +25 C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) INL (LSB) INTERGRAL NONLINEARITY vs. INPUT CODE INPUT CODE (DECIMAL) toc INL (LSB) INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE V REF (V) toc2 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. INPUT CODE INPUT CODE (DECIMAL) toc3 DNL (LSB) DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE V REF (V) toc4 INL (LSB) INTEGRAL NONLINEARITY toc5 DNL (LSB) DIFFERENTIAL NONLINEARITY (WORST-CASE CODES)..8.6 CODE = 9FFhex CODE = 7FFhex toc6 UNIPOLAR SETTLING TIME (C LOAD = 25pF, R LOAD = 2kΩ) toc7 BIPOLAR SETTLING TIME (C LOAD = 25pF, R LOAD = kω) toc8 BIPOLAR MAJOR CARRY GLITCH ENERGY, C LOAD = 25pF toc9 2V/div mv/div t =.µs/div t =.µs/div t = 4.µs/div 7

8 Typical Operating Characteristics (continued) (V DD = +5V, V SS = -5V for bipolar graphs, V SS = for unipolar graphs, V CC = +5V, AGND = DGND = SGND =, V REF = +5.V, output unloaded, T A = +25 C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) BIPOLAR MAJOR CARRY GLITCH C LOAD = pf toc UNIPOLAR ZERO-SCALE VOLTAGE CODE = 4hex toc BIPOLAR MIDSCALE VOLTAGE CODE = 8hex toc2 mv/div VOUT (mv) VOUT (mv) t = 4.µs/div UNIPOLAR FULL-SCALE VOLTAGE CODE = FFFhex toc BIPOLAR POSITIVE FULL-SCALE VOLTAGE CODE = FFFhex toc BIPOLAR NEGATIVE FULL-SCALE VOLTAGE CODE = hex toc VOUT (mv) VOUT (mv) VOUT (mv) V SS = V UNIPOLAR SUPPLY CURRENT vs. SUPPLY VOLTAGE toc BIPOLAR POSITIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE V SS = -5V toc7 IDD (ma) IDD (ma) V DD (V) V DD (V) 8

9 Typical Operating Characteristics (continued) (V DD = +5V, V SS = -5V for bipolar graphs, V SS = for unipolar graphs, V CC = +5V, AGND = DGND = SGND =, V REF = +5.V, output unloaded, T A = +25 C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) ISS (ma) BIPOLAR NEGATIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE V DD = 5V toc8 IDD (ma) V SS = V UNIPOLAR SUPPLY CURRENT toc9 IDD (ma) BIPOLAR POSITIVE SUPPLY CURRENT toc2a V SS (V) ISS (ma) BIPOLAR NEGATIVE SUPPLY CURRENT VOUT (V) toc2b SHUTDOWN CURRENT (µa) UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT CODE = FFFhex I OUT (ma) UNIPOLAR SHUTDOWN CURRENT I CC I DD I SS toc23a VOUT (V) toc2 SHUTDOWN CURRENT (µa) BIPOLAR SHUTDOWN CURRENT I CC I DD -3 I SS UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT CODE = 4hex I OUT (ma) toc23b toc22 9

10 Typical Operating Characteristics (continued) (V DD = +5V, V SS = -5V for bipolar graphs, V SS = for unipolar graphs, V CC = +5V, AGND = DGND = SGND =, V REF = +5.V, output unloaded, T A = +25 C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) VOUT (V) BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT CODE = hex I OUT (ma) toc24a VOUT (V) BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT CODE = FFFhex I OUT (ma) toc24b REF INPUT RESISTANCE (MΩ).. UNIPOLAR REF INPUT RESISTANCE vs. INPUT CODE INPUT CODE (DECIMAL) toc25 REF INPUT RESISTANCE (MΩ). BIPOLAR REF INPUT RESISTANCE vs. INPUT CODE toc26 RESPONSE (db) UNIPOLAR REFERENCE INPUT BANDWIDTH REF =.2V P-P + 5.VDC toc27 RESPONSE (db) BIPOLAR REFERENCE INPUT BANDWIDTH REF =.2V P-P + 5.VDC toc INPUT CODE (DECIMAL) -5.. FREQUENCY (khz) -5.. FREQUENCY (khz) UNIPOLAR STARTUP RESPONSE, C LOAD = pf toc29a UNIPOLAR STARTUP RESPONSE, C LOAD = 25pF toc29b 2V/div V DD 2V/div V DD V CC V CC V REF V REF 2V/div V/div t =.µs/div t =.µs/div

11 Typical Operating Characteristics (continued) (V DD = +5V, V SS = -5V for bipolar graphs, V SS = for unipolar graphs, V CC = +5V, AGND = DGND = SGND =, V REF = +5.V, output unloaded, T A = +25 C, all graphs apply to both unipolar and bipolar, unless otherwise noted.) 2V/div BIPOLAR STARTUP RESPONSE, C LOAD = pf toc3a V DD 2V/div BIPOLAR STARTUP RESPONSE, C LOAD = 25pF toc3b V DD V CC V CC V/div V/div V SS V SS 2V/div V/div t =.µs/div t =.µs/div UNIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE toc3 BIPOLAR RELEASE FROM HARDWARE-SHUTDOWN RESPONSE toc32 V SHDN V SHDN 2V/div 2V/div t = µs/div t = µs/div UNIPOLAR SOFTWARE-SHUTDOWN RESPONSE toc33a BIPOLAR SOFTWARE-SHUTDOWN RESPONSE toc33b V/div t = 4.µs/div t = 4.µs/div

12 PIN NAME FUNCTION SCLK Serial-Clock Input. Data is shifted from DIN into the internal register on the rising edge of SCLK. Data is clocked out at DOUT on the falling edge of SCLK. SCLK is active only while is low. 2 DIN S er i al - D ata Inp ut. D IN i s the d ata i np ut p or t for the ser i al i nter face. C l ock d ata i n on the r i si ng ed g e of S C LK. 3 Acti ve- Low C hi p - S el ect Inp ut. acti vates the ser i al i nter face. D r i ve l ow to i ni ti ate ser i al com m uni cati on. 4 DOUT 5 DGND Digital Ground Serial-Data Output. DOUT is the data output port for the serial interface. Data shifted into DIN appears at DOUT 6.5 clock cycles later, valid on the falling edge of SCLK. DOUT is high impedance when is high. 6 V CC Digital Power Input. V CC ranges from +2.7V to +5.5V. Bypass V CC with a.µf and.µf capacitor to 7 SHDN Active-Low Shutdown Input. SHDN places the device into low-power shutdown mode. When shut down REF and DOUT are high impedance, drive SHDN low to place the device into shutdown mode. 8 UNI/BIP Unipolar/Bipolar-Select Input. UNI/BIP selects unipolar or bipolar output. In unipolar mode, the analog output range is to (+2 x V REF ). In bipolar mode, the analog output range is (-2 x V REF ) to (+2 x V REF ). Drive UNI/BIP high for unipolar output. Drive UNI/BIP low for bipolar output. Dual supplies are required for bipolar operation. 9 OUT Analog Output. OUT is the output port for the DAC. Read OUT relative to SGND. SGND Signal Ground. SGND is the ground-reference node for the output amplifier s internal feedback resistors. Connect SGND directly to AGND. (See Figure.) AGND Analog Ground. AGND is the ground return for V DD and V SS. 2 V SS Negative Power Input. Bypass V SS with a.µf and.µf capacitor to AGND. If operating with a single supply, connect V SS to AGND. 3 REF External Reference Input. Apply an external reference voltage of +2V to +5.25V to REF to determine the output voltage range. In unipolar mode, the output range is from to (+2 x V REF ). In bipolar mode, the output range is from (-2 x V REF ) to (+2 x V REF ). 4 V DD Positive Power Input. Bypass V DD with a.µf and.µf capacitor to AGND. 5 CLR Pin Description Active-Low Clear Input. CLR clears input and DAC registers and resets the DAC output to V. Drive CLR low to assert the clear condition. 6 LDAC Active-Low Load Input. Use LDAC to update the DAC register. LDAC is an asynchronous control input. Drive low to force an update. 2

13 Detailed Description The 2-bit DAC operates from either single or dual supplies. Dual ±2V to ±5V power supplies provide a bipolar ±5V to ±V output, or a unipolar to V output. Single 2V to 5V power supplies provide only a unipolar to V output. The reference input accepts voltages from 2V to 5.25V. The DAC features INL and DNL less than ± LSB (max), a fast µs settling time, and a hardware-shutdown mode that reduces current consumption to 3.5µA (max). The device features a MHz SPI-/QSPI-/MICROWIRE-compatible serial interface that operates with 3V or 5V logic, an asynchronous load input, and a serial-data output. The device offers a CLR that sets the DAC output to V. Figure shows the functional diagram of the. Serial Interface An SPI-/QSPI-/MICROWIRE-compatible serial interface allows complete control of the DAC through a 6-bit control word. The first 4 bits form the control bits that determine register loading and software-shutdown functions. The last 2 bits form the DAC data. The 6- bit word is entered MSB first. Table shows the serial-data format. Table 2 shows the interface commands. The can be programmed while in shutdown. The serial interface contains three registers: a 6-bit shift register, a 2-bit input register, and a 2-bit DAC register (Figure ). The shift register accepts data from the serial interface. The input register acts as a holding register for data going to the DAC register and isolates the shift register from the DAC register. The DAC register controls the DAC ladder and thus the output voltage. Any update in the DAC register updates the output voltage. 2R 2R V CC V DD REF 2-BIT DAC SW A SW2 A2 OUT 2 SW3 2R LDAC DAC REGISTER CLR 2 2R INPUT REGISTER SGND 2 DIN 6-BIT SHIFT REGISTER DOUT SCLK UNI/BIP SERIAL INTERFACE AND CONTROL AGND SHDN DGND V SS Figure. Functional Diagram 3

14 Data in the shift register is transferred to the input register during the appropriate software command only. Data in the input register is transferred to the DAC register in one of two ways: using the software command, or through external logic control using the asynchronous load input (LDAC). Table 2 shows the software commands that transfer the data from the shift register to the input and/or DAC registers. The CLR, an external logic control, asynchronously forces the input and DAC registers to zero code, and the output to V, in both unipolar and bipolar modes. The interface timing is shown in Figures 2 and 3. Wait a minimum of ns after goes high before implementing LDAC or CLR. If either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. For software control only, connect LDAC and CLR high. DAC Architecture The uses an inverted DAC ladder architecture to convert the digital input into an analog output voltage. The digital input controls weighted-switches that connect the DAC ladder nodes to either REF or GND (Figure 4). The sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output. Table. Serial-Data Format MSB CONTROL BITS DATA BITS C3 C2 C C D D D9 D8 D7 D6 D5 D4 D3 D2 D D Table 2. Serial-Interface Programming Commands CONTROL BITS* INPUT DATA C3 C2 C C D D XXXXXXXXXXXX No operation; command is ignored. FUNCTION 2-bit DAC data Load input register from shift register; DAC output unchanged. 2-bit DAC data Load input and DAC registers from shift register; DAC output updated. XXXXXXXXXXXX Load D AC r eg i ster fr om i np ut r eg i ster ; D AC outp ut up d ated ; i np ut r eg i ster unchang ed. XXXXXXXXXXXX Enter shutdown; input and DAC registers unchanged. XXXXXXXXXXXX Exit shutdown; input and DAC registers unchanged. X = Don t care. *All unlisted commands are reserved commands. Do not use. LSB COMMAND EXECUTED SCLK () DIN C3 C2 C C D D D9 D8 D7 D6 D5 D4 D3 D2 D D Figure 2. Serial-Interface Signals 4

15 SCLK t t S t CP t H t t CH t CL t DS t DH t W DIN MSB LSB t E t DO t D DOUT LDAC t LDS t LD Figure 3. Serial-Interface Timing Diagram 2R 2R R R R 2R 2R 2R 2R 2R SW SW2 OUT D D D D SW3 2R REF AGND 2R SGND DAC REGISTER UNI/BIP CONTROL LOGIC Figure 4. Basic Inverted DAC Ladder 5

16 External Reference and Transfer Functions Connect an external 2V to 5.25V reference to REF (the MAX635 is recommended). Set the output voltage range with the reference and the input code by using the equations below. Unipolar Output Voltage: where Bipolar Output Voltage: where VOUT_ UNI = LSBUNI CODE 2 V LSB REF UNI = 2 2 VOUT_ BIP = ( LSBBIP CODE) ( 2 VREF) V LSB REF BIP = where _UNI is the unipolar output voltage, _BIP is the bipolar output voltage, LSB UNI is the unipolar LSB step size, LSB BIP is the bipolar LSB step size, V REF is the reference voltage, and CODE is the decimal equivalent of the binary, 2-bit, DAC input code. In either case, a hex input code produces the minimum output (-2 x V REF for bipolar and for unipolar), an 8hex input code produces the midscale output ( for bipolar and V REF for unipolar), and a FFFhex input code produces the full-scale output (2 x V REF for bipolar and unipolar). Output Amplifiers The output-amplifier section can be configured as either unipolar or bipolar by the UNI/BIP logic input. With UNI/BIP forced low, SW and SW2 in Figure 4 are closed, and SW3 is open. This configuration channels the DAC output through two output stages to generate the ±2 x V REF output swing. The first amplifier generates the ±V REF voltage range and the second amplifier increases it by two. When configured for bipolar operation, the must be driven with dual ±2V to ±5V power supplies. With UNI/BIP forced high, switches SW and SW2 are open, and SW3 is closed. This configuration channels the DAC output through only a single gain stage to generate a to (2 x V REF ) output swing. Daisy Chaining SPI-/QSPI-/MICROWIRE-compatible devices can be daisy chained to reduce I/O lines from the host controller (Figure 7). Daisy chain devices by connecting the DOUT of one device to the DIN of the next, and connect the SCLK of all devices to a common clock. Data is shifted out of DOUT 6.5 clock cycles after it is shifted into DIN, and is available on the rising edge of the 7th clock cycle. The SPI-/QSPI-/MICROWIRE-compatible serial interface normally works at up to MHz, but must be slowed to 6.MHz if daisy chaining. DOUT is high impedance when is high. Shutdown Shutdown is controlled by software commands or by the SHDN logic input. The SHDN logic input can be implemented at any time. The SPI-/QSPI-/MICROWIRE-compatible serial interface remains fully functional, and the device is programmable while shut down. When shut down, the supply current reduces to 3.5µA, DOUT is high impedance, and OUT is pulled to SGND through the internal feedback resistors of the output amplifier (Figure ). When coming out of shutdown, or during device powerup, allow 35µs for the output to stabilize. Table 3. Output Voltage as Input Code Examples BINARY DAC CODE ANALOG OUTPUT MSB LSB UNIPOLAR (UNI/BIP_ = HIGH) BIPOLAR (UNI/BIP_ = LOW) +2 x V REF (495 / 496) +2 x V REF (247 / 248) +2 x V REF (249 / 496) +2 x V REF ( / 248) +2 x V REF (248 / 496) = V REF +2 x V REF (247 / 496) -2 x V REF ( / 248) +2 x V REF ( / 496) -2 x V REF (247 / 248) -2 x V REF (248 / 248) = -2 x V REF 6

17 ANALOG OUTPUT VOLTAGE (LSB) LSB = 2 x V REF 496 ANALOG OUTPUT VOLTAGE (LSB) LSB = 4 x V REF x VREF FF 8 8 FFC FFD FFE FFF 2 3 7FF 8 8 FFC FFD FFE FFF 2 x VREF hex DIGITAL INPUT CODE (LSB) hex DIGITAL INPUT CODE (LSB) Figure 5. Unipolar Transfer Function Figure 6. Bipolar Transfer Function Applications Information Power Supplies A single +2V to +5V supply is required to realize a to V output swing. A dual ±2V to ±5V supply is required to realize a ±V output swing, and allows unipolar, to +V output if UNI/BIP is forced high. A +3V to +5V digital power supply and a +2.V to +5.25V external reference voltage are also required. Always bring up the reference voltage last. The other power supplies do not require sequencing. Power-Supply Bypassing and Ground Management Bypass V DD and V SS with.µf and.µf capacitors to AGND, and bypass V CC with.µf and.µf capacitors to DGND. Minimize trace lengths to reduce inductance. Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a lowinductance ground plane or star connect all groundreturn paths back to AGND. Carefully lay out the traces between channels to reduce AC crosscoupling and crosstalk. Wire-wrapped boards, sockets, and breadboards are not recommended. 7

18 SCLK TO OTHER SERIAL DEVICES SCLK SCLK SCLK DIN DIN DOUT DIN DOUT DIN DOUT Figure 7. Daisy Chaining Devices Chip Information TRANSISTOR COUNT: 328 TECHNOLOGY: BiCMOS 8

19 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to 2 E H DIM A A B C D E e H L INCHES MILLIMETERS MIN MAX MIN MAX SEE VARIATIONS BSC.65 BSC D D D D D INCHES MIN MAX MILLIMETERS MIN MAX N 4L 6L 2L 24L 28L SSOP.EPS N A e D B A L C NOTES:. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED.5 MM (.6"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO5. 5. LEADS TO BE COPLANAR WITHIN. MM. PROPRIETARY INFORMATION TITLE: PACKAGE OUTLINE, SSOP, 5.3 MM APPROVAL DOCUMENT CONTROL NO. REV C Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 2 San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.