+1.2V to +5.5V, ±15kV ESD-Protected, 0.1µA, 35Mbps, 8-Channel Level Translators

Transcription

1 9-67; Rev ; /6 General Description The 8-channel level translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. Logic signals present on the side of the device appear as a higher voltage logic signal on the side of the device, and vice-versa. The MAXE/MAXE/MAX/MAX use an architecture specifically designed to be bidirectional without the use of a directional pin. The MAXE/MAXE/MAX/MAX MAX feature an input that, when low, reduces the and supply currents to < µa. The MAXE/MAXE also have ±kv ESD protection on the I/O side for greater protection in applications that route signals externally. The MAXE operates at a guaranteed data rate of kbps. The MAXE operates at a guaranteed data rate of Mbps. The MAX MAX operate at a guaranteed data rate of Mbps over the entire specified operating voltage range. The accept voltages from +.V to +.V and voltages from +.6V to +.V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAXE/MAXE/MAX MAX are available in -bump UCSP, -pin TQFN (mm x mm), and -pin TSSOP packages. Applications CMOS Logic-Level Translation Cellphones SPI and MICROWIRE Level Translation Low-Voltage ASIC Level Translation Smart Card Readers Cellphone Cradles Portable POS Systems Portable Communication Devices Low-Cost Serial Interfaces GPS Telecommunications Equipment UCSP is a trademark of Maxim Integrated Products, Inc. SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor. Features Guaranteed Data Rate Options kbps (MAXE) Mbps (MAXE) Mbps (MAX MAX) Bidirectional Level Translation Without Using a Directional Pin (MAXE/MAXE/MAX/ MAX) Unidirectional Level Translation (MAX MAX) Operation Down to +.V on ±kv ESD Protection on I/O Lines (MAXE/MAXE) Ultra-Low.µA Supply Current in Shutdown Low Quiescent Current (< µa) UCSP, TQFN, and TSSOP Packages PART +.8V +.8V SYSTEM CONTROLLER DATA Ordering Information TEMP RANGE Typical Operating Circuit I/O _ MAXE MAXE MAX MAX I/O _ PIN- PACKAGE DATA +.V +.V SYSTEM PKG CODE MAXEEUP - C to +8 C TSSOP U- MAXEEBP-T - C to +8 C x UCSP B- Ordering Information continued at end of data sheet. Note: All devices operate over the - C to +8 C operating temperature range. Pin Configurations and Functional Diagrams appear at end of data sheet. Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at , or visit Maxim s website at

2 ABSOLUTE MAXIMUM RATINGS (All voltages referenced to.)...-.v to +6V... -.V to +6V I/O _...-.V to ( +.V) I/O _...-.V to ( +.V), A/B...-.V to +6V Short-Circuit Duration I/O _, I/O _ to...continuous Continuous Power Dissipation (T A = +7 C) -Pin TSSOP (derate 7.mW/ C above +7 C)...9mW -Bump UCSP (derate mw/ C above +7 C)...8mW -Pin mm x mm TQFN (derate.mw/ C above +7 C)...667mW Operating Temperature Ranges MAXEAUP...- C to + C MAX_EE_P...- C to +8 C MAX E_P...- C to +8 C Junction Temperature...+ C Storage Temperature Range...-6 C to + C Lead Temperature (soldering, s)...+ C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS ( = +.6V to +.V, = +.V to, = (MAXE/MAXE/MAX/MAX MAX), A/B = or (MAX), T A = T MIN to T MAX. Typical values are at = +.6V, = +.V, and T A = + C.) (Notes, ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES Supply Range. V Supply Range.6. V I/O _ =, I/O _ = or I/O _ =, I/O _ =, MAXE/MAX MAX CC QVCC I/O _ =, I/O _ = or I/O _ =, I/O _ =, MAXE I/O _ =, I/O _ = or I/O _ =, I/O _ =, MAXE/MAX MAX Supply Current from I QVL I/O _ =, I/O _ = or I/O _ =, I/O _ =, MAXE T A = + C, =, MAXE/MAXE/MAX/ MAX MAX Shutdown Supply Current I SHDN-VCC T A = + C, A/B =,..... µa µa µa MAX Shutdown Supply Current I SHDN-VL T A = + C, =, MAXE/MAXE/MAX/ MAX MAX T A = + C, A/B =, MAX... µa

3 ELECTRICAL CHARACTERISTICS (continued) ( = +.6V to +.V, = +.V to, = (MAXE/MAXE/MAX/MAX MAX), A/B = or (MAX), T A = T MIN to T MAX. Typical values are at = +.6V, = +.V, and T A = + C.) (Notes, ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS I/O _ Three-State Output Leakage Current I/O _ Three-State Output Leakage Current I/O _ Pulldown Resistance During Shutdown T A = + C, =, MAXE/MAXE/MAX/ MAX MAX T A = + C, A/B =, MAX.. A/B =, MAX. µa =, MAXE/MAXE/MAX/ MAX MAX µa.9 8. kω E N or A/B Inp ut Leakag e C ur rent T A = + C µa LOGIC-LEVEL THRESHOLDS I/O _ Input-Voltage High Threshold I/O _ Input-Voltage Low Threshold I/O _ Input-Voltage High Threshold I/O _ Input-Voltage Low Threshold, A/B Input-Voltage High Threshold, A/B Input-Voltage Low Threshold V IHL / x V V ILL / x V V IHC / x V V ILC / x V V IH -. V V IL. V I/O _ Output-Voltage High V OHL I/O _ source current = µa, I/O _ -.V I/O _ Output-Voltage Low V OLL I/O _ sink current = µa, I/O _.V I/O _ Output-Voltage High V OHC I/O _ source current = µa, I/O _ -.V V. V V I/O _ Output-Voltage Low V OLC I/O sink current = µa, I/O _.V. V ESD PROTECTION I/O _ Human Body Model, MAXE/MAXE ± kv

4 TIMING CHARACTERISTICS ( = +.6V to +.V, = +.V to, = (MAXE/MAXE/MAX/MAX MAX), A/B = or (MAX), T A = T MIN to T MAX. Typical values are at = +.6V, = +.V, and T A = + C.) (Notes, ) I/O _ Rise Time I/O _ Fall Time I/O VL _ Rise Time I/O VL _ Fall Time Propagation Delay (Driving I/O VL _) PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS t RVCC t FVCC t RVL t FVL I/O VL-VCC R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX M AX, Fi g ur es a, b R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX M AX, Fi g ur es a, b R S = Ω, C VL = p F, M AX E, Fi g ur es a, b R S = Ω, C VL = p F, M AX E, Fi g ur es a, b R S = Ω, C VL = p F, M AX M AX, Fi g ur es a, b R S = Ω, C VL = p F, M AX E, Fi g ur es a, b R S = Ω, C VL = p F, M AX E, Fi g ur es a, b R S = Ω, C VL = p F, M AX M AX, Fi g ur es a, b R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX E, Fi g ur es a, b R S = Ω, C VCC = p F, M AX M AX, Fi g ur es a, b ns ns ns ns ns R S = Ω, C VL = p F, M AX E, Fi g ur es a, b Propagation Delay (Driving I/O _) I/O VCC-VL R S = Ω, C VL = p F, M AX E, Fi g ur es a, b ns R S = Ω, C VL = p F, M AX M AX, Fi g ur es a, b Note : All units are % production tested at T A = + C. Limits over the operating temperature range are guaranteed by design and not production tested. Note : For normal operation, ensure that <. During power-up, > does not damage the device.

5 TIMING CHARACTERISTICS (continued) ( = +.6V to +.V, = +.V to, = (MAXE/MAXE/MAX/MAX MAX), A/B = or (MAX), T A = T MIN to T MAX. Typical values are at = +.6V, = +.V, and T A = + C.) (Notes, ) PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS Channel-to-Channel Skew Part-to-Part Skew Propagation Delay from I/O _ to I/O _ after Propagation Delay from I/O _ to I/O _ after Maximum Data Rate t SKEW t PPSKEW R S = Ω, C VCC = p F, C VL = p F, M AX E R S = Ω, C VCC = p F, C VL = p F, M AX E R S = Ω, C VCC = p F, C VL = p F, M AX M AX R S = Ω, C V C C = p F, C = p F, T A = + C, MAXE (N ote ) 8 R S = Ω, C VCC = p F, C VL = p F, T A = + C, M AX E ( N ote ) R S = Ω, C VCC = p F, C VL = p F, T A = + C, M AX M AX ( N ote ) t -VCC C VCC = p F, M AX E /M AX E, M AX M AX, Fi g ur e t -VL C VL = p F, M AX E /M AX E / M AX /M AX M AX, Fi g ur e C VL = p F, M AX, Fi g ur e R S = Ω, C VCC = p F, C VL = p F, M AX E R S = Ω, C VCC = p F, C VL = p F, M AX E R S = Ω, C VCC = p F, C VL = p F, M AX M AX Note : from device must equal of device ; from device must equal of device. ns ns µs µs kbps Mbps

6 TIMING CHARACTERISTICS MAX MAX ( = +.6V to +.V, = +.V to, = (MAX/MAX MAX), A/B = or (MAX), T A = T MIN to T MAX. ) (Notes, ) PARAMETER SYM B O L CONDITIONS MIN TYP MAX UNITS +.V +.V I/O _ Rise Time t RVCC ns I/O _ Fall Time t FVCC ns I/O _ Rise Time t RVL ns I/O _ Fall Time t FVL ns Propagation Delay I/O VL-VCC Driving I/O _ I/O VCC-VL Driving I/O _ Channel-to-Channel Skew t SKEW Each translator equally loaded ns Maximum Data Rate Mbps +.V +.V I/O _ Rise Time t RVCC 8. ns I/O _ Fall Time t FVCC 8. ns I/O _ Rise Time t RVL 8. ns I/O _ Fall Time t FVL 8. ns Propagation Delay I/O VL-VCC Driving I/O _ 8. I/O VCC-VL Driving I/O _ 8. Channel-to-Channel Skew t SKEW Each translator equally loaded ns Maximum Data Rate Mbps +.8V +.V I/O _ Rise Time t RVCC ns I/O _ Fall Time t FVCC ns I/O _ Rise Time t RVL ns I/O _ Fall Time t FVL ns Propagation Delay I/O VL-VCC Driving I/O _ I/O VCC-VL Driving I/O _ Channel-to-Channel Skew t SKEW Each translator equally loaded ns Maximum Data Rate Mbps ns ns ns 6

7 (T A = + C, unless otherwise noted.) VL SUPPLY CURRT (µa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING I/O, =.8V) 6 DATA RATE = Mbps DATA RATE = Mbps DATA RATE = kbps SUPPLY VOLTAGE (V) VCC SUPPLY CURRT (µa) VCC SUPPLY CURRT (µa) MAXE/E/- toc VCC SUPPLY CURRT (µa) SUPPLY CURRT vs. SUPPLY VOLTAGE (DRIVING I/O, =.8V), 8 6 SUPPLY CURRT vs. TEMPERATURE (DRIVING I/O, =.V, =.8V) DATA RATE = Mbps DATA RATE = Mbps TEMPERATURE ( C) DATA RATE = kbps DATA RATE = Mbps SUPPLY CURRT vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 7 6 DATA RATE = Mbps DATA RATE = Mbps DATA RATE = kbps MAXE/E/- toc MAXE/E/- toc6 SUPPLY VOLTAGE (V) Typical Operating Characteristics DATA RATE = Mbps DATA RATE = kbps VL SUPPLY CURRT (µa) RISE/FALL TIME (ns) 8 6 MAXE/E/- toc VL SUPPLY CURRT (µa) SUPPLY CURRT vs. TEMPERATURE (DRIVING I/O, =.V, =.8V) DATA RATE = Mbps DATA RATE = Mbps TEMPERATURE ( C) SUPPLY CURRT vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) DATA RATE = Mbps DATA RATE = Mbps DATA RATE = kbps MAXE RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) t LH t HL DATA RATE = kbps DATA RATE = kbps MAXE/E/- toc MAXE/E/- toc7 MAXE/E/- toc 7

8 (T A = + C, unless otherwise noted.) RISE/FALL TIME (ns) RISE/FALL TIME (ns) RISE/FALL TIME (ns) MAXE RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 6 t LH t HL DATA RATE = Mbps MAXE RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) DATA RATE = kbps MAX MAX RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) t HL t LH t LH t HL Typical Operating Characteristics (continued) MAXE/E/- toc8 MAXE/E/- toc MAXE/E/- toc RISE/FALL TIME (ns) RISE/FALL TIME (ns) MAX MAX RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 8 6 t LH t HL DATA RATE = Mbps MAXE RISE/FALL TIME vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 6 PROPAGATION DELAY (ns) t HL t LH DATA RATE = Mbps MAXE PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) t PLH t PHL MAXE/E/- toc9 MAXE/E/- toc MAXE/E/- toc DATA RATE = Mbps DATA RATE = kbps 8

9 (T A = + C, unless otherwise noted.) MAXE PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) PROPAGATION DELAY (ns) PROPAGATION DELAY (ns) t PLH MAXE PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 9 6 t PHL DATA RATE = Mbps t PHL MAXE RAIL-TO-RAIL DRIVING (DRIVING I/O, =.V, =.8V, C = pf, DATA RATE = kbps) MAXE/E/- toc9 MAXE/E/- toc PROPAGATION DELAY (ns) t PLH DATA RATE = Mbps Typical Operating Characteristics (continued) MAX MAX PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 8 6 MAXE/E/- toc7 t PLH t PHL DATA RATE = Mbps PROPAGATION DELAY (ns) MAXE RAIL-TO-RAIL DRIVING (DRIVING I/O, =.V, =.8V, C = pf, DATA RATE = Mbps) PROPAGATION DELAY (ns) MAXE PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) 6 t PHL MAX MAX PROPAGATION DELAY vs. CAPACITIVE LOAD ON I/O (DRIVING I/O, =.V, =.8V) MAXE/E/- toc MAXE/E/- toc t PHL t PLH DATA RATE = Mbps t PLH DATA RATE = kbps MAX MAX RAIL-TO-RAIL DRIVING (DRIVING I/O, =.V, =.8V, C = pf, DATA RATE = Mbps) MAXE/E/- toc8 MAXE/E/- toc MAXE/E/- toc6 I/O _ V/div I/O _ V/div I/O _ V/div I/O _ V/div I/O _ V/div I/O _ V/div µs/div ns/div ns/div 9

10 MAXE/MAXE/MAX PIN TSSOP UCSP TQFN NAME B 9 I/O Input/Output, Referenced to FUNCTION Pin Description A Logic Input Voltage, +.V. Bypass to with a.µf capacitor. A I/O Input/Output, Referenced to B I/O Input/Output, Referenced to A I/O Input/Output, Referenced to 6 B I/O Input/Output, Referenced to 7 A I/O 6 Input/Output 6, Referenced to 8 B 6 I/O 7 Input/Output 7, Referenced to 9 A 7 I/O 8 Input/Output 8, Referenced to B 8 C 9 Ground D I/O 8 Input/Output 8, Referenced to C I/O 7 Input/Output 7, Referenced to D I/O 6 Input/Output 6, Referenced to C I/O Input/Output, Referenced to 6 D I/O Input/Output, Referenced to 7 C I/O Input/Output, Referenced to 8 D 6 I/O Input/Output, Referenced to Enable Input. If is pulled low, I/O to I/O 8 are in three-state, while I/O to I/O 8 have internal 6kΩ pulldown resistors. Drive high ( ) for normal operation. 9 C 7 Input Voltage, +.6V +.V. Bypass to with a.µf capacitor. D 8 I/O Input/Output, Referenced to EP EP Exposed Pad. Connect to.

11 MAX PIN TSSOP UCSP TQFN NAME B 9 I/O A Input/Output A, Referenced to Pin Description (continued) FUNCTION A Logic Input Voltage, +.V. Bypass to with a.µf capacitor. A I/O A Input/Output A, Referenced to B I/O A Input/Output A, Referenced to A I/O A Input/Output A, Referenced to 6 B I/O B Input/Output B, Referenced to 7 A I/O B Input/Output B, Referenced to 8 B 6 I/O B Input/Output B, Referenced to 9 A 7 I/O B Input/Output B, Referenced to B 8 A/B C 9 Ground D I/O B Input/Output B, Referenced to C I/O B Input/Output B, Referenced to D I/O B Input/Output B, Referenced to C I/O B Input/Output B, Referenced to 6 D I/O A Input/Output A, Referenced to 7 C I/O A Input/Output A, Referenced to 8 D 6 I/O A Input/Output A, Referenced to Enable Input. If A/B is pulled low, channels B through B are active, and channels A through A are in three-state. If A/B is driven high to, channels A through A are active, and channels B through B are in three-state. 9 C 7 Input Voltage, +.6V +.V. Bypass to with a.µf capacitor. D 8 I/O A Input/Output A, Referenced to EP EP Exposed Pad. Connect to.

12 MAX MAX NAME FUNCTION (Note ) (MAX) (MAX) (MAX6) (MAX7) (MAX8) (MAX9) (MAX) (MAX) (MAX) Pin Description (continued) Input Voltage, +.6V < < +.V. Bypass to with a.µf capacitor. Logic Input Voltage, +.V. Bypass to with a.µf capacitor. Ground Enable Input. If is pulled low, O O 8 are in three-state, while I I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I and O O 8 are in three-state, while O and I I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I, I, and O O 8 are in three-state, while O, O, and I I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I, I, I, and O O 8 are in three-state, while O, O, O, and I I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I I and O O 8 are in three-state, while O O and I I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I I, O 6, O 7, and O 8 are in three-state, while O O, I 6, I 7, and I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I I 6, O 7, and O 8 are in three-state, while O O 6, I 7, and I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I I 7 and O 8 are in three-state, while O O 7 and I 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. Enable Input. If is pulled low, I I 8 are in three-state, while O O 8 have 6kΩ pulldown resistors. Drive high ( ) for normal operation. I I 8 Inputs Referenced to, Numbers to 8 O O 8 Outputs Referenced to, Numbers to 8 I I 8 Inputs Referenced to, Numbers to 8 O O 8 Outputs Referenced to, Numbers to 8 Note : For specific pin numbers, see the Pin Configurations.

13 Test Circuits/Timing Diagrams SOURCE R S I/O Figure a. Driving I/O I/O C VL Figure a. Driving I/O MAXE/MAXE/ MAX/MAX MAXE/MAXE/ MAX/MAX R S I/O I/O C VCC SOURCE I/O 9% % % I/O 9% % % I/O 9% % % I/O 9% % % t RISE/FALL ns I/O VL-VCC I/O VCC-VL t FVCC Figure b. Timing for Driving I/O t RISE/FALL ns t FVL Figure b. Timing for Driving I/O I/O VL-VCC t RVCC I/O VCC-VL t RVL

14 Test Circuits/Timing Diagrams (continued) SOURCE I/O SOURCE I/O MAXE/MAXE/ MAX/MAX MAXE/MAXE/ MAX/MAX Figure. Propagation Delay from I/O to I/O After C VL SOURCE I/O SOURCE MAXE/MAXE/ MAX/MAX MAXE/MAXE/ MAX/MAX I/O I/O I/O C VCC C VCC I/O I/O I/O I/O t' -VCC t" -VCC t -VCC IS WHICHEVER IS LARGER BETWE t' -VCC AND t" -VCC I/O I/O t' -VL t" -VL I/O I/O I/O C VL I/O t -VL IS WHICHEVER IS LARGER BETWE t' -VL AND t" -VL Figure. Propagation Delay from I/O to I/O After

15 Detailed Description The logiclevel translators provide the level shifting necessary to allow data transfer in a multivoltage system. Externally applied voltages, and, set the logic levels on either side of the device. Logic signals present on the side of the device appear as a higher voltage logic signal on the side of the device, and vice-versa. The MAXE/MAXE/MAX/MAX are bidirectional level translators allowing data translation in either direction ( ) on any single data line. These devices use an architecture specifically designed to be bidirectional without the use of a direction pin. The MAX MAX unidirectional level translators level shift data in one direction ( or ) on any single data line. The MAXE/MAXE/ MAX MAX accept from +.V to +.V. All devices have ranging from +.6V to +.V, making them ideal for data transfer between low-voltage ASICs/PLDs and higher voltage systems. The MAXE/MAXE/MAX/MAX MAX feature an output enable mode that reduces supply current to less than µa, and supply current to less than µa when in shutdown. The MAXE/MAXE have ±kv ESD protection on the side for greater protection in applications that route signals externally. The MAXE operates at a guaranteed data rate of kbps; the MAXE operates at a guaranteed data rate of Mbps and the MAX MAX are guaranteed with a data rate of Mbps of operation over the entire specified operating voltage range. Level Translation For proper operation, ensure that +.6V +.V, +.V +.V, and. During power-up sequencing, does not damage the device. During power-supply sequencing, when is floating and is powering up, up to ma current can be sourced to each load on the side, yet the device does not latch up. The maximum data rate also depends heavily on the load capacitance (see the Typical Operating Characteristics), output impedance of the driver, and the operational voltage range (see the Timing Characteristics table). Input Driver Requirements The MAXE/MAX MAX architecture is based on a one-shot accelerator output stage. See Figure. Accelerator output stages are always in threestate except when there is a transition on any of the translators on the input side, either I/O or I/O. When there is such a transition, the accelerator stages become active, charging (discharging) the capacitances at the I/Os. Due to its bidirectional nature, both stages become active during the one-shot pulse. This can lead to some current feeding into the external source that is driving the translator. However, this behavior helps to speed up the transition on the driven side. For proper full-speed operation, the output current of a device that drives the inputs of the MAXE/ MAXE/MAX MAX should meet the following requirements: MAXE (kbps): i > ma, R drv < kω MAXE (Mbps): i > 7 x V x (C + pf) MAX MAX (Mbps): i > 8 x V x (C + pf) where i is the driver output current, V is the logic-supply voltage (i.e., or ) and C is the parasitic capacitance of the signal line. Enable Output Mode (, A/B) The MAXE/MAXE/MAX and the MAX MAX feature an input, and the MAX has an A/B input. Pull low to set the MAXE/ MAXE/MAX/MAX MAXs I/O through I/O 8 in three-state output mode, while I/O through I/O 8 have internal 6kΩ pulldown resistors. Drive to logic-high ( ) for normal operation. The MAX is intended for bus multiplexing or bus switching applications. Drive A/B low to place channels B through B in active mode, while channels A through A are in three-state mode. Drive A/B to logic-high ( ) to enable channels A through A, while channels B through B remain in three-state mode. ±kv ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The I/O lines have extra protection against static discharge. Maxim s engineers have developed state-of-the-art structures to protect these pins against ESD of ±kv without damage. The ESD structures withstand high ESD in all states: normal operation, three-state output mode, and powered down. After an ESD event, Maxim s E versions keep working without latchup, whereas competing products can latch and must be powered down to remove latchup.

16 I/O ESD protection can be tested in various ways. The I/O lines of the MAXE/MAXE are characterized for protection to ±kv using the Human Body Model. ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 7a shows the Human Body Model and Figure 7b shows the current waveform it generates when discharged into a low impedance. This model consists of a pf capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a.kω resistor. Machine Model The Machine Model for ESD tests all pins using a pf storage capacitor and zero discharge resistance. Its objective is to emulate the stress caused by contact that occurs with handling and assembly during manufacturing. Of course, all pins require this protection during manufacturing, not just inputs and outputs. Therefore, after PCB assembly, the Machine Model is less relevant to I/O ports. 6kΩ P ONE-SHOT N ONE-SHOT I/O _ TO I/O _ PATH P ONE-SHOT N ONE-SHOT 6kΩ I/O _ TO I/O _ PATH Figure. MAXE/MAX MAX Simplified Functional Diagram ( I/O Line) V TH_IN / 6kΩ -(V S - V TH_IN ) / 6kΩ I IN Figure 6. Typical I IN vs. V IN I/O V TH_IN V S V IN WHERE V S = OR 6

17 Applications Information Power-Supply Decoupling To reduce ripple and the chance of transmitting incorrect data, bypass and to ground with a.µf capacitor. To ensure full ±kv ESD protection, bypass to ground with a µf capacitor. Place all capacitors as close to the power-supply inputs as possible. IC Level Translation For I C level translation for I C applications, please refer to the MAX7E MAX79E/MAX9E MAX9E datasheet. Unidirectional vs. Bidirectional Level Translator The MAXE/MAXE/MAX/MAX bidirectional translators can operate as a unidirectional device to translate signals without inversion. The MAX MAX unidirecitional level translators, level-shift data in one direction ( or ) on any single data line (see the Ordering Information.) These devices provide the smallest solution (UCSP package) for unidirectional level translation without inversion. 7

18 HIGH- VOLTAGE DC SOURCE R C MΩ CHARGE-CURRT- LIMIT RESISTOR C S pf R D Ω DISCHARGE RESISTANCE STORAGE CAPACITOR Figure 7a. Human Body ESD Test Model DEVICE UNDER TEST AMPERES I P % 9% 6.8% % t RL TIME Ir t DL CURRT WAVEFORM Figure 7b. Human Body Current Waveform PART A/B Tx/Rx* DATA RATE PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) Selector Guide ESD PROTECTION (kv) MAXE 8/8 kbps ± MAXE 8/8 Mbps ± MAX 8/8 ** ± MAX 8/8 ** ± MAX 8/ ** ± MAX 7/ ** ± MAX6 6/ ** ± MAX7 / ** ± MAX8 / ** ± MAX9 / ** ± MAX /6 ** ± MAX /7 ** ± MAX /8 ** ± *Tx = VL ; Rx = **See Table. Table. Data Rate (V) MAX MAX GUARANTEED DATA RATE (Mbps)

19 I/O I/O I/O I/O I/O I/O 6 MAXE/MAXE/MAX Functional Diagram MAXE/ MAXE/MAX I/O I/O I/O I/O I/O I/O 6 I/O 7 I/O 7 I/O 8 I/O 8 9

20 A/B I/O A I/O A I/O A I/O A I/O B I/O B MAX Functional Diagram MAX I/O A I/O A I/O A I/O A I/O B I/O B I/O B I/O B I/O B I/O B

21 D C B A MAXE/MAXE/MAX MAX MAX I/O I/O I/O 6 I/O I/O I/O I/O 7 TOP VIEW I/O I/O I/O I/O 7 I/O I/O I/O 6 TOP VIEW UCSP (Bottom View) MAXE/MAXE/MAX I/O I/O I/O I/O I/O 6 I/O 6 7 I/O 7 8 I/O 8 9 TSSOP VL 9 I/O VL 8 I/O VCC 7 VCC 6 I/O VCC I/O 9 8 I/O 7 I/O 6 I/O I/O I/O 6 I/O 7 I/O 8 I/O 8 I/O 8 D C B A MAX I/O A I/O A I/O B I/O B I/O A I/O A I/O B I/O B I/O A I/O A I/O B I/O B A/B I/O A I/O A I/O B I/O B UCSP (Bottom View) MAX I/O A I/O A I/O A I/O A I/O B I/O B I/O B I/O B A/B I/O A I/O A I/O A I/O A I/O B I/O B I/O B I/O B TSSOP VL I/O VLA I/O VCCA VCC Pin Configurations 6 I/O VCCA I/O I/O I/O A I/O A I/O I/O I/O I/O 6 I/O A I/O A I/O B I/O B MAX *EXPOSED PADDLE I/O A I/O B I/O B I/O B I/O VLB 6 I/O VLB 7 A/B 8 9 I/O VCCB MAXE/ MAXE/ MAX *EXPOSED PADDLE I/O I/O I/O 6 I/O 7 I/O VL7 6 I/O VL I/O VCC8 mm mm THIN QFN mm mm THIN QFN

22 TOP VIEW I I I I I I 6 I 7 I 8 O O O I I I 6 I 7 I MAX TSSOP MAX7 TSSOP O O O O O O 6 O 7 O 8 I I I O O O 6 O 7 O 8 O I I I I I 6 I 7 I 8 O O O O I I 6 I 7 I MAX TSSOP MAX8 TSSOP Pin Configurations (continued) MAX I O O O O O 6 O 7 O O I I I I 6 I I I O O O O 6 O 7 O 8 I 8 9 O 8 TSSOP MAX9 I O I I O 8 I 7 I O 7 I 6 I O 6 I O O 6 I O 6 I 6 7 O 6 O 7 I 7 8 O 7 O 8 I 8 9 O 8 TSSOP

23 TOP VIEW PART O O O O O O 6 I 7 I MAX TSSOP TEMP RANGE I 9 8 I 7 I 6 I I I 6 O 7 O 8 PIN- PACKAGE O O O O O O 6 O 7 I PKG CODE MAXEEUP - C to +8 C TSSOP U- MAXEEBP-T* - C to +8 C x UCSP B- MAXEETP - C to +8 C TQFN T- MAXEAUP - C to + C TSSOP U- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAXETP - C to +8 C TQFN T- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAXETP - C to +8 C TQFN T- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAX6EUP - C to +8 C TSSOP U- MAX6EBP-T* - C to +8 C x UCSP B- MAX TSSOP Pin Configurations (continued) I 9 8 I 7 I 6 I I I 6 I 7 O 8 O O O O O O 6 O 7 O MAX TSSOP I 9 8 I 7 I 6 I I I 6 I 7 I 8 Ordering Information (continued) PART TEMP RANGE PIN- PACKAGE *Future product contact factory for availability. -T = Tape-and-reel package. PKG CODE MAX7EUP - C to +8 C TSSOP U- MAX7EBP-T* - C to +8 C x UCSP B- MAX8EUP - C to +8 C TSSOP U- MAX8EBP-T* - C to +8 C x UCSP B- MAX9EUP - C to +8 C TSSOP U- MAX9EBP-T* - C to +8 C x UCSP B- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- MAXEUP - C to +8 C TSSOP U- MAXEBP-T* - C to +8 C x UCSP B- TRANSISTOR COUNT: 8 PROCESS: BiCMOS Chip Information

24 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to x UCSP.EPS

25 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to QFN THIN.EPS

26 Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to PACKAGE OUTLINE, TSSOP.mm BODY -66 I TSSOP.mm.EPS Revision History Pages changed at Rev :,,,,,, 6,, 6 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 Maxim Integrated Products, San Gabriel Drive, Sunnyvale, CA Maxim Integrated Products is a registered trademark of Maxim Integrated Products.