PCM-FTL: A Write-Activity-Aware NAND Flash Memory Management Scheme for PCM-based Embedded Systems

Transcription

1 nd IEEE Real-Time Systems Symposium PCM-FTL: A Write-Activity-Aare NAND Flash Memory Management Scheme for PCM-based Embedded Systems Duo Liu, Tianzheng Wang, Yi Wang, Zhiei Qin and Zili Shao Department of Computing The Hong Kong Polytechnic University Hung Hom, Koloon, Hong Kong cszlshao@comp.polyu.edu.hk Abstract Due to its properties of high density, in-place update, and lo standby poer, phase change memory (PCM) becomes a promising main memory alternative in embedded systems. On the other hand, NAND ash memory is idely used as a secondary storage and has been integrated into PCM-based embedded systems. Since both NAND ash memory and PCM have limited lifetime, ho to effectively manage NAND ash memory in PCM-based embedded systems, hile considering the endurance issue is very important. In this paper, e present for the rst time a rite-activityaare NAND ash memory management scheme, called PCM- FTL, to effectively manage NAND ash memory and enhance the endurance of PCM-based embedded systems. The basic idea is to preserve each bit in ash mapping table, hich is stored in PCM, from being inverted frequently, i.e., e focus on minimizing the number of bit ips in a PCM cell hen updating the ash mapping table. PCM-FTL employs a to-level mapping mechanism, hich not only focuses on minimizing the rite activities of PCM but also considers the access behavior of I/O requests. We evaluate PCM-FTL using a variety of realistic I/O traces. Experimental results sho that the proposed technique can achieve an average reduction of 9.1% and a maximum reduction of 98.98% in the maximum number of bit ips for a PCM-based embedded system ith 1GB NAND ash memory. We hope this ork can serve as a rst step toards the design of rite-activity-aare FTL for the PCM-based embedded systems via simple and feasible modications. Keyords-NAND ash memory, phase change memory, endurance, ash translation layer. I. INTRODUCTION Due to its high density, in-place update, and lo standby poer, phase change memory (PCM) is considered as a DRAM alternative for designing main memory in embedded systems [1 6]. Hoever, compared to DRAM, PCM suffers from limited endurance (1 6 to 1 8 per cell) and high rite latency/energy [7]. These constraints impose challenges for using PCM as a complete replacement for DRAM, and thus motivate the emerging of a hybrid main memory ith a small-sized DRAM cache and a large-sized PCM [1, 6]. As main memory is one of the most heavily accessed components in embedded systems, the limited endurance of PCM leads to a shortened memory lifetime especially for rite-intensive requests. It is therefore necessary to eliminate redundant rite activities in PCM-based embedded systems. On the other hand, ith the advantages of small size, shock resistance, and lo poer, NAND ash memory is idely used as a secondary storage and has been integrated into PCM-based embedded systems [8 1]. As a result, ho to effectively manage NAND ash memory and avoid a fast orn-out of PCM-based embedded systems should be taken into account. Therefore, this paper focuses on exploring the management of NAND ash memory in a PCM-based embedded system, hile considering rite activities in PCM to increase the reliability of the system. NAND ash memory is partitioned into blocks and each block is further divided into multiple pages. Each page contains a area, and an OOB (Out Of Band) area for storing state information. A block is the smallest unit of erase operations, hile a page is the minimum unit of read/rite operations. These distinct characteristics introduce constraints for NAND ash memory management. First, NAND ash memory performs out-of-place updates, i.e., to be updated must be ritten to another ne page in NAND ash memory. Second, a block can only sustain 1 to 1 5 erase counts before orn-out []. Third, for some management schemes, not all blocks in NAND ash memory get erased at the same rate, so some specic blocks may ear out faster hich ould affect the reliability of the entire system. To conceal these constraints, an intermediate softare module called ash translation layer (FTL) is designed to emulate NAND ash memory as a disk drive [1, 1]. The main role of FTL is to redirect logical addresses of I/O requests from le system into physical addresses in NAND ash memory, and to maintain a mapping table for keeping track of the mapping information. Hoever, FTL mapping table is usually kept in main memory to provide fast lookup, and is updated continually according to I/O requests. Therefore, for effectively managing NAND ash memory in PCM-based embedded systems, it is crucial to carefully study the rite activities of the most frequently accessed FTL mapping table in PCM, and eliminate redundant rite operations that may degrade PCM endurance. These observations motivate us to propose a rite-activity-aare / $6. IEEE DOI 1.9/RTSS.. 57

2 FTL scheme for managing NAND ash memory in PCMbased embedded systems. The objective of this paper is to minimize rite activities of FTL mapping table in PCM, such that the reliability and performance of the entire PCMbased embedded system is enhanced. Over the past decade, many studies for FTL schemes have been proposed [1 ]. According to the granularity of mapping unit, there are three types of FTL schemes: page-level mapping, block-level mapping, and hybrid-level mapping [1]. Most of the previous ork, hoever, have not yet explored the management mechanism of NAND ash memory in the emerging PCM-based embedded systems. Kim et al. [8] propose a page-level mapping FTL (hftl) for managing NAND ash memory in the PCMbased embedded systems, here the page-level mapping table is stored in PCM and user is stored in NAND ash memory. Nevertheless, their approach does not consider rite activities of FTL mapping table in PCM, and the access behavior of I/O requests as ell. As FTL mapping table is updated frequently in PCM, a huge number of unnecessary rite operations on FTL mapping table ill degrade the endurance of PCM. Ne techniques, therefore, are needed to eliminate unnecessary rite operations on FTL mapping table and, at the same time, to enhance the endurance of PCM-based embedded systems. In this paper, e propose a rite-activity-aare FTL scheme, called PCM-FTL, to effectively manage NAND ash memory and enhance the endurance of PCM-based embedded systems, ith the advantage that no changes are required to the le system, or hardare implementation of the NAND/PCM chip. Our basic idea is to preserve each bit in FTL mapping table, hich is stored in PCM, from being inverted frequently, i.e., e focus on minimizing the number of bit ips in a PCM cell hen updating the FTL mapping table. PCM-FTL employs a to-level mapping mechanism, hich not only focuses on minimizing rite activities of PCM but also considers the access behavior of I/O requests. To achieve this, in PCM, e use a page-level mapping table to handle not frequently updated random requests, and allocate a tiny buffer of block-level mapping table to record most frequently updated sequential requests. To further minimize rite activities in PCM, PCM-FTL actively chooses a physical block in NAND ash memory hose physical block number incurs minimum number of bit ips. Consequently, the rite activities are eliminated and the endurance of PCM is enhanced. To the best of our knoledge, PCM-FTL is the rst technique proposed for effectively managing NAND ash memory in PCM-based embedded systems ith the consideration of rite activities. We conduct experiments on a set of realistic I/O traces. A representative FTL design hftl [8] for PCM-based embedded systems is selected as a baseline scheme. The proposed PCM-FTL is compared ith hftl in terms of PCM bit ips ith various congurations. The experimental results sho that our approach can achieve an average reduction of 9.1% and a maximum reduction of 98.98% in the maximum number of bit ips for a PCM-based embedded system ith 1GB NAND ash memory. In addition, the results also sho that PCM-FTL can achieve an even distribution of bit ips in PCM in comparison ith the baseline scheme. This paper makes the folloing contributions: We present for the rst time a rite-activity-aare FTL scheme to effectively manage NAND ash memory and enhance the endurance of PCM-based embedded systems by eliminating redundant rite activities. We demonstrate the effectiveness of our technique by comparing ith a representative FTL using a set of realistic I/O orkloads. The rest of this paper is organized as follos. Section II discusses the background and motivation. Section III presents our proposed PCM-FTL technique. Section IV presents the experimental results. Finally, in Section V, e conclude the paper and discuss future ork. II. BACKGROUND AND MOTIVATION In this section, e rst introduce the background knoledge of PCM-based embedded systems. Then e describe the issues of a representative FTL scheme. Finally, e present the motivation of our ork. A. PCM-Based Embedded Systems Figure 1 shos a typical PCM-based embedded system, in hich the FTL mapping table is stored in PCM and user is stored in NAND ash memory. In the system, the MTD layer provides primitive functions such as read, rite, and erase operations. The FTL layer emulates the ash memory as a disk device so that it can provide transparent storage service to le systems. Folloing the I/O requests, FTL translates addresses beteen logical page number (LPN) and physical page number (PPN), and keeps track of the mapping information by using an FTL mapping table in PCM. Then according to the mapping, can be directly read from (rite into) NAND ash memory. Unlike NAND ash memory, PCM supports bitaddressability and in-place update. A PCM cell is made of phase change material such as Ge Sb Te 5 (GST). By ejecting electrical pulses to heat up the GST region, each PCM cell can sitch beteen to states amorphous and crystalline, hich have high and lo electrical resistance, respectively. Reading a bit from a PCM cell is accomplished by sensing the resistance level of the cell. To represent binary 1, a SET operation is performed to turn a PCM cell into the crystalline state by applying a moderate poer, long duration pulses; To represent binary, a RESET operation is performed to turn a PCM cell into the amorphous state by applying a high poer, short duration pulses. Both of these operations impose heat stress to PCM cells, and thus 58

3 Application 1 Figure 1. memory. Address Translator LPN Operating System File System (e.g., FAT, NTFS) Flash Translation Layer (FTL) PPN Mapping Table in PCM Application Garbage Collector Wear-Leveler Memory Technology Device (MTD) Layer NAND Flash (user ) Application n Illustration of PCM-based embedded system ith NAND ash a PCM cell can only sustain a limited number of rite (SET/RESET) operations. Several techniques have been developed to reduce unnecessary rite operations in PCM. Zhou et al. [, 5] propose a set of hierarchical techniques, such as bit-rite removal, ro shifting and segment sapping, to tackle the redundant rite activities by eliminating a rite if its designated PCM cell holds the same value. Qureshi et al. [1] introduce a PCM-based hybrid memory architecture herein PCM is employed as a main memory hile a small-sized DRAM is employed as a cache buffer. Based on this architecture, Start- Gap is proposed to evenly distribute rite operations across various PCM cells for improving ear leveling, and linelevel rite scheme [] is developed to rite only the dirty lines in the cache buffer into the PCM. Dhiman et al. [] introduce a scheme herein a page manager is developed to allocate pages across PCM and DRAM for improving PCM lifetime and ear leveling. Hu et al. [, 5] propose a migration and recomputation technique to reduce the rite activities. Ferreira et al. [6] present three schemes, namely, N-Chance cache replacement policy, unnecessary rites reduction ith read-rite-read and a ear-leveling scheme to reduce rite activities and increase the PCM lifetime. Hoever, all of the above techniques are designed to reduce rite activities in PCM at the architecture/hardare level. This paper solves this problem at the level of ash translation layer for PCM-based embedded systems ith a NAND ash memory. B. A Representative FTL Scheme In this section, e briey revisit the hftl scheme hich is proposed for managing NAND ash memory in PCMbased embedded systems [8]. hftl is based on page-level mapping scheme [1], but it is optimized for PCM-based embedded systems. hftl stores meta such as FTL mapping table, physical page information, and physical block information in PCM. NAND ash memory is only used for storing user from the le system, and the blocks in NAND ash memory are categorized into three types, i.e., garbage blocks, blocks, and a buffer block. Different from the conventional pagelevel mapping FTL, hftl uses a buffer block to store the nely arrived. When the buffer block runs out of free pages, it is put into the block list and another empty buffer block is allocated from the garbage block list. If there is not enough number of garbage blocks, a garbage collection operation is performed to reclaim a block from theblocks.inhftl, a page-level mapping table in PCM keeps track of mappings beteen logical page number (LPN) and physical page number (PPN), in terms of the I/O requests. Consequently, the mapping table is updated frequently and thus imposes the endurance issue for PCM. A motivational example is illustrated in Figure. In the example, there are four blocks in NAND ash memory, and each block has 8 pages. Therefore, a pagelevel mapping table in PCM has entries to record the mapping information. To facilitate the comparison of hftl and our PCM-FTL scheme, the physical page number (PPN), physical block number (PBN), and the offset of each block are represented by binary number. We assume that each entry of the mapping table is empty at the beginning, and the binary number in an entry is the updated PPNs to reect the updates of mapping. The I/O access requests of rite operations () are listed in Figure (a). According to the given I/O requests, the status variation of the blocks in NAND ash memory is shon in Figure (b). For hftl, hen a rite operation is performed, the corresponding content is rst ritten to a free page of the current buffer block in a sequence order. As shon, the rst request is ritten to LPN (#18). A ne buffer block (PBN #) is allocated from the garbage block list, and the content A ith the corresponding LPN (#18) are stored in the rst page of current buffer block (PBN #). Meanhile, the mapping information of LPN (#18) and PPN (#) is stored into the mapping table shon in Figure (c). Note that PPN is the combination of PBN and the block offset. After serving the eighth request, buffer block (PBN #) is full and becomes a block. Likeise, the remaining garbage blocks (PBN #1, PBN #1, and PBN #) are allocated as a buffer block respectively, to serve the folloing rite operations. Finally, hen the content of N ith the corresponding LPN (#9) are rote into the last page of buffer block (PBN #), all garbage blocks become blocks and some entries of the mapping table have been updated by ne PPNs for several times. C. Motivation In the motivational example, several update operations are performed in the FTL page-level mapping table. For instance, the 1th request updates the old content in the 1st 59

4 I/O Requests Command Logical Page Number (LPN) Content 1 18 A 5 B 1 C D 5 8 E 6 9 F 7 1 G 8 H 9 1 I 1 1 J 1 K 1 15 L 1 18 A1 (a) 1 5 B B A 17 7 M 18 9 N 19 D1 O 1 9 N1 8 E1 9 F1 1 G1 5 H1 6 1 I1 7 1 J1 8 1 K L1 7 M1 1 O1 9 N I/O 1-8 I/O 9-16 I/O 17 - I/O - Buffer Block Buffer Block Buffer Block Buffer Block A Garbage Garbage Garbage Garbage Garbage 1 B 5 C 1 D E 8 F 9 G 1 H Buffer Block PBN # I M 7 1 N 9 D1 O N1 9 E1 8 F1 9 G1 1 Buffer Block PBN #1 1 H1 1 1 J 1 K 1 L 15 A1 18 B1 5 B 5 A 18 Buffer Block PBN #1 I1 1 J1 1 K1 1 L1 15 M1 7 O1 N 9 Buffer Block PBN # Data Free page Data A 18 B 5 C 1 D E 8 F 9 G 1 H PBN # PBN #1 PBN #1 PBN # (b) Valid page Data I 1 J 1 K 1 L 15 A1 18 B1 5 B 5 A 18 PBN #1 PBN #1 PBN # A 18 B 5 C 1 D E 8 F 9 G 1 H PBN # Data A 18 B 5 C 1 D E 8 F 9 G 1 H PBN # M 7 N 9 D1 O N1 9 E1 8 F1 9 G1 1 PBN #1 PBN # I 1 J 1 K 1 L 15 A1 18 B1 5 B 5 A 18 PBN #1 Invalid page Data A 18 B 5 C 1 D E 8 F 9 G 1 H PBN # I 1 J 1 K 1 L 15 A1 18 B1 5 B 5 A 18 PBN #1 M 7 N 9 D1 O N1 9 E1 8 F1 9 G1 1 PBN #1 H1 I1 1 J1 1 K1 1 L1 15 M1 7 O1 N 9 PBN # LPN PPN LOG FTL Page Mapping Table LPN: Logical Page Number PPN: Physical Page Number BF: Bit Flips (c) BF 5 5 Figure. Motivational example. (a) I/O access requests. (b) The status variation of blocks in NAND ash memory. (c) The status variation of FTL page-level mapping table in PCM. page of block (PBN #) by setting that page invalid, and rites the ne content to the current buffer block (PBN #1). Meanhile, the corresponding mapping information in the mapping table is updated as ell. In Figure (c), e use the bit ips (BF), shon on the right side of the mapping table, to reect the update frequency of each entry in the mapping table. As shon, the th and 9th entry have the maximum number of bit ips 5. Since PCM cell can only sustain limited number of rite cycles, frequent update operations in mapping table ill lead to the fast orn out of PCM. These observations motivate us to propose a rite-activity-aare FTL to effectively manage NAND ash memory and, at the same time, to improve the endurance of PCM-based embedded systems. As mentioned above, several hardare optimization techniques for PCM have been proposed [, 5], to tackle the redundant rite activities by eliminating a rite if its designated memory cell holds the same value. Then through utilizing such a ne-grained hardare feature, this ork actively chooses mapping information (e.g., PBN) hich 6

5 is almost the same as the mapping to be updated in the mapping table, such that the number of rite activities in PCM is minimized. III. PCM-FTL: WRITE-ACTIVITY-AWARE FTL In this section, e present the details of our PCM-FTL, a rite activity-aare FTL, that can effectively enhance the endurance of the PCM-based embedded systems. We rst present an overvie of PCM-FTL in Section III-A. We then provide a detailed description of PCM-FTL in Section III-B. A. Overvie The objective of PCM-FTL is to reduce rite activities in PCM-based embedded systems, and therefore, the endurance of PCM is enhanced. So the basic idea of PCM-FTL is to preserve each bit in FTL mapping table, hich is stored in PCM, from being inverted frequently, i.e., e focus on minimizing the number of bit ips in a PCM cell hen updating the FTL mapping table. Different from the previous ork [8], our PCM-FTL adopts a to-level mapping mechanism, hich not only focuses on minimizing rite activities in PCM but also considers the access behavior of I/O requests. PCM-FTL uses a page-level mapping table to record the mapping of rite requests not frequently updated, and allocates a tiny buffer of block-level mapping table to cache the mapping of those most frequently updated rite requests. With the consideration of rite activities, once a block is needed for incoming rite requests, PCM-FTL actively chooses a physical block in NAND ash memory hose physical block number incurs minimum number of bit ips. By applying PCM-FTL, the number of bit ips is reduced, and thus the number of rite activities in PCM is minimized. Consequently, the endurance of the PCM-based embedded system is enhanced. In this paper, e assume that the FTL mapping table is stored in a single-level cell (SLC) PCM (i.e., a PCM cell holds only one bit), and the user is stored in a multi-level cell (MLC) NAND ash memory, hich is idely used in embedded systems. B. PCM-FTL Description In general, a realistic I/O orkload is a mixture of random and sequential requests. By separating the random requests from the sequential requests, e can not only obtain the access behavior but also handle those frequently updated rite requests. Otherise, ithout considering the access behavior of I/O orkload, e can not effectively manage NAND ash memory and may aste lots of blocks in garbage collection due to frequent update operations. Therefore, in PCM-FTL, e design a behavior detector to separate the I/O orkload into random and sequential requests, according to the length of each request in the I/O orkload. The length is a user dened threshold, hich is determined by observing performance gains ith different threshold values (e.g., 8, Random Requests Logical Page LBN Number (LPN) Page-Level Mapping Table Physical Page Number (PPN) Block I/O Requests Behavior Detector PCM NAND Flash Memory Sequential Requests LPN Logical Block Number (LBN) Block-Level Mapping Table Buffer Block 1 Block Block N- Block N-1 Figure. Structure of PCM-FTL. 16, ) in the experiments. For example, if the length of a request is smaller than 8, then this request is treated as a random request; Otherise, if the length of a request is greater than or equal to 8, then it is treated as a sequential request. Figure shos the structure of PCM-FTL. As shon, PCM-FTL rst separates the I/O orkload into random requests and sequential requests. Then PCM-FTL adopts a to-level FTL mechanism to handle these to cases as follos: For random requests: PCM-FTL sequentially allocates physical pages from the rst page of a physical block in NAND ash memory, so that all pages in blocks are fully utilized. Accordingly, PCM-FTL adds LPN to PPN mapping of random requests into the page-level mapping table. For sequential requests: PCM-FTL allocates physical pages based on block offset as most sequential requests usually occupy a hole block, so that all pages in blocks are fully utilized as ell. Similarly, PCM-FTL adds an LBN to PBN mapping of sequential requests into the block-level mapping table buffer. In PCM-FTL, e only allocate a tiny buffer for temporary storing a part of the block-level mapping table. For example, the size of this block-level mapping buffer is set as 1% of the size of the original block-level mapping table. Therefore, a replacement policy should be considered hen the buffer is full. Similar as a cache, e only kick out the mapping of those not frequently updated blocks, hile maintaining the mapping of frequent updated blocks. The kicked out mapping information is put into the page-level mapping table. If a block in NAND ash memory has N p valid pages, and its corresponding block-level mapping is kicked 61

6 out to page-level mapping table, then N p entries in pagelevel mapping table should be lled ith the corresponding LPN to PPN mapping for each page in the block. On the contrary, the page-level mapping of a block can be re-added into the block-level mapping table buffer, once the block is updated again by sequential rite requests. Therefore, by observing the frequently updated requests, our technique can dynamically adjust the block-level mapping table buffer and the page-level mapping table, such that rite activities of frequently updated requests are only buffered in block-level mapping table buffer hich only contributes a small number of bit ips in PCM. The experimental results in Section IV conrms this fact. To further minimize rite activities in PCM, a riteactivity-aare strategy is proposed. In our technique, to allocate a ne block for the rite/update requests, the corresponding original physical block number (PBN) is rst obtained from page-level mapping table (by dividing PPN ith the number of pages in a block), or from block-level mapping table buffer ith the requested logical page number (LBN). Then according to the original PBN, e actively select a physical block in NAND ash memory hose PBN is almost the same as the original PBN, i.e., the ne PBN incurs minimum number of bit ips if the original PBN is updated by the ne PBN in the mapping table. As a result, a large number of redundant bit ips is reduced, and the endurance of PCM is enhanced. Algorithm III.1 shos the process of a rite operation of PCM-FTL. PCM-FTL rst divides the incoming I/O request into random rites or/and sequential rites according to a threshold. Then the random and sequential rite requests are processed separately. For random rite request (lines -17), if it is a ne rite, i.e., e cannot nd its corresponding LBN or LP N mapping in the block-level mapping table buffer or page-level mapping table. So PCM-FTL nds a ne block PBN, and rite the contents of the random rite request into the allocated ne block sequentially from the rst page. After that, e add the (LP N, PPN) mapping into the page-level mapping table. If the random rite request is an update, and there exists enough space in the updated block, then rite the update contents into the left space of the block sequentially, and invalid the old pages in the same block. Otherise, there does not exist enough space in the updated block, PCM-FTL ill actively nd a ne block hose block number is almost the same as PBN, and then rite the update contents in the ne block based on block offset. At last, e update the corresponding blocklevel mapping table buffer or page-level mapping table. For sequential rite request (lines 18-6), e process it in the similar ay as that for processing random rite request. Note that the block-level mapping table buffer is updated frequently by sequential rite requests,so it may become very hot and lead to an uneven distribution of bit ips in PCM. To avoid this scenario and enhance PCM endurance, a Algorithm III.1 The algorithm of PCM-FTL Input: I/O requests ith random request or/and sequential request. Output: Allocate pages for the I/O request. 1: Divide the I/O request into random rites or/and sequential rites according to a predened threshold. : if Random rite request arrives then : Obtain the LBN and LP N of the random rite request. : if LBN s mapping is not in block-level mapping table buffer or LP N s mapping is not in page-level mapping table then 5: This is a ne rite, allocate a ne block PBN, and rite the contents into the block sequentially from the rst page. 6: Add the mapping of (LP N, PPN) into the page-level mapping table. 7: end if 8: if LBN s mapping exists in block-level mapping table buffer or LP N s mapping exists in page-level mapping table then 9: This is an update, obtain the PBN of the updated block. 1: if There exists enough space in the PBN block for the update request then : Write the update contents in the left space of the PBN block sequentially, and invalid the old pages in the same block. 1: else 1: Actively nd a ne block hose block number is almost the same as PBN, rite the update contents in the ne block sequentially, and invalid the old pages in PBN block. 1: end if 15: Update block-level mapping table buffer or page-level mapping table. 16: end if 17: end if 18: if Sequential rite request arrives then 19: Obtain the LBN and LP N of the sequential rite request. : if LBN s mapping is not in block-level mapping table buffer or LP N s mapping is not in page-level mapping table then 1: This is a ne rite, allocate a ne block PBN, and rite the contents of the request into the block based on block offset. : if The block-level mapping table buffer is full then : Kick out least frequently used entry, add the kicked out mappings into page-level mapping table. : end if 5: Add the mapping of (LBN, PBN) into the block-level mapping table buffer. 6: end if 7: if LBN s mapping exists in block-level mapping table buffer or LP N s mapping exists in page-level mapping table then 8: This is an update, obtain the PBN of the updated block. 9: if There exists enough space in the PBN block for the update request then : Write the update contents in the left space of the PBN block based on block offset, and invalid the old pages in the same block. 1: else : Actively nd a ne block hose block number is almost the same as PBN, rite the update contents in the ne block based on block offset, and invalid the old pages in PBN block. : end if : Update block-level mapping table buffer or page-level mapping table. 5: end if 6: end if ear-leveling method is integrated into PCM-FTL. In PCM- FTL, during a period of time (e.g., every 1 I/O requests), the block-level mapping table buffer is moved across the hole mapping table area (block-level and page-level mapping table) in PCM. With acceptable copy operations of mapping information, an even distribution of bit ips in PCM is obtained. An example of PCM-FTL is shon in Figure. This example is based on the I/O requests and the NAND ash memory assumptions for the motivational example shon in Figure. As shon, for the rst random request ith LPN (#18), e nd a ne block (PBN #), and the content A is ritten sequentially into the rst page (#) of 6

7 1 1 1 A 18 C 1 A1 18 A 18 O O1 Block PBN # I/O Request 1, I/O Request 1, LRU 1 1 B B B M N 9 N1 9 M1 7 N 9 Block PBN #1 Free page LBN Replacement PBN 1 1 LRU LBN PBN Replacement FTL Block-Level Mapping Table Buffer LPN/PPN: Logical/Physical Page Number BF: Bit Flips (a) BF BF I/O Request LRU LBN PBN BF 1,, 1 16,, , (b) Valid page D D1 Block PBN #1 LPN PPN LOG E1 8 1 F1 9 1 G1 1 H1 1 I1 1 J1 1 K1 1 L1 15 Block PBN # FTL Page-Level Mapping Table Invalid page BF 1 LBN/PBN: Logical/ Number LRU: Least Recently Updated Figure. Illustration of PCM-FTL. (a) The status variation of blocks in NAND ash memory according to the access sequence in Figure. (b) The status variation of FTL page-level mapping table and block-level mapping table buffer in PCM. block (PBN #). For this request, there is no bit ip hen updating the mapping table. It can be seen that A is updated by a ne content A1 in the 1th request, and A1 is ritten into the physical page (#1) according to the update policy of PCM-FTL. When the 1th request arrives, e use the LPN (#18) to get the corresponding LBN (#1). Then e nd the LBN (#1) is already in the block-level mapping table buffer, so the 1th request is an update to the old page in the block (PBN #), then by checking the block (PBN #), e kno the old content A of this LPN (#18) is stored in the page PPN (#), thus this page is set as invalid. Since there exists enough space in block (PBN #), the ne update content A1 of LPN (#18) is ritten sequentially into the block. It is noticed that the 5th to 1th requests form a sequential rite, then e allocate a ne block (PBN #) for this request, and rite the contents into each page of the block based on offset. The corresponding LBN to PBN mapping (1, ) is added into the block-level mapping table buffer. Later, hen the folloing th to 9th sequential update requests arrive, then the old pages in the block (PBN #) are invalid. Since e cannot nd free block, the block (PBN #) is erased, and the ne update E1 to L1 is ritten into this block based on offset. Finally, e update the blocklevel mapping table buffer, and the value of corresponding LRU is updated as ell. After processing all requests, e found that the total number of bit ips in PCM is 16 by our PCM-FTL, hile the total number of bit ips in PCM are by hftl. Our scheme achieves a reduction of 6.6% in the total number of bit ips, hich conrms that our approach can effectively reduce rite activities in PCM. The experimental results in Section IV also sho that our scheme can effectively reduce the total number of bit ips. IV. EVALUATION To evaluate the effectiveness of the proposed PCM-FTL, e conduct a series of experiments and present the experimental results ith analysis in this section. We compare and evaluate our proposed PCM-FTL scheme over the representative page-level FTL scheme, hftl[8], based on the maximum and total number of bit ips in PCM cells. A. Experimental Setup Table I EXPERIMENTAL SETUP CPU Intel Dual Core GHz Hardare Disk Space GB RAM GB OS Kernel Linux.6.17 Simulation Flash Size 1GB & GB Environment PCM 6 MB OS Windos XP (NTFS) Trace Name Generator DiskMon Trace Web applications, MSN, Applications Word, Excel, PoerPoint Media Player, Emuler The performance evaluation is through a trace-driven simulation. The trace of request as collected from desktop running DiskMon [6] ith an Intel Pentium Dual Core GHz processor, a GB hard disk, and a GB DRAM. The trace reects the realistic orkload of the system in accessing the hard disk for daily use. Among these traces, CopyFiles is a trace collected by copying les from hard disk to an external hard drive; DonFiles represents a trace collected by donloading les from a netork server; Ofce represents a trace collected by running some ofce related applications; PP represents a trace collected by running a PP le-sharing application on an external hard drive; Table I summarizes our experimental platform and trace collection environment. The frameork of our simulation platform is shon in Figure 5. In our experiment, e use the same experimental conguration adopted by hftl [8], a 1GB NAND ash memory and a 6 MB PCM are congured in our simulator. The traces along ith various ash parameters, such as block size, page size, etc, are fed into our simulation frameork. 6

8 Table II THE MAXIMUM AND TOTAL NUMBER OF BIT FLIPS OF PCM-FTL VERSUS hftl. Total Num. of Bit ips Maximum Num. of Bit ips Trace Name % of Write % of Read PCM-FTL over PCM-FTL over hftl PCM-FTL hftl hftl PCM-FTL hftl PCM ith 1GB NAND Flash Memory CopyFiles 78.75% 1.5% 559,96,658 9,866,9 7.8% 9, % DonFiles 71.88% 8.1% 1,756,6,7 568,987, % 1, % Ofce 77.7%.6% 7,5,8,995,576,89, % 9,85 1,76 81.% PP 8.95% 71.5% 6,99,967,6 1,718,81,56 75.% 7, % Average 6.% 9.1% PCM ith GB NAND Flash Memory CopyFiles 78.75% 1.5% 1,65,5 9,56,5.77% 1,61, % DonFiles 71.88% 8.1% 8,1,6 191,579,9 77.6%,857, % Ofce 77.7%.6% 6,981,79,6 919,567, % 6,667 7, % PP 8.95% 71.5% 15,69,865,958 65,6,6 95.7% 86,8 7, % Average 7.9% 8.1% The page size, number of pages in a block, and size of the OOB for each page are set as KB, 6, and 6 Bytes, respectively. Therefore, the 1GB NAND ash memory used in the experiment has 8,19 physical blocks. To fully evaluate our scheme, e further conduct the experiments on a GB NAND ash memory ith the same congurations. In addition, the threshold for distinguishing random and sequential requests is set as 8. DiskMon Figure 5. Input Parameters Trace Flash Translation Layer PCM-based Embedded System With NAND flash The frameork of simulation platform. Results B. Results and Discussion In this section, e present the experimental results ith analysis. We rst present the endurance impact of PCM- FTL. Then e present the ear-leveling comparison of PCM-FTL and the baseline scheme. 1) PCM Endurance: The objective of this paper is to reduce rite activities to enhance the endurance of PCM-based embedded systems. Therefore, the endurance of PCM is one of the most important factors in analyzing the reliability of PCM-based embedded systems. The endurance of PCM is mainly affected by the orst case of bit ips in a PCM cell, i.e., the maximum number of bit ips in a PCM cell determines the endurance of PCM. For example, if PCM can only sustain 1 6 rite cycles, then a PCM cell is orn-out if it suffers from more than 1 6 bit ips. So our technique not only focuses on minimizing rite activities in PCM but also reducing the maximum number of bit ips. Table II presents the results for the maximum and total number of bit ips among all PCM cells hen managing 1GB and GB NAND ash memory in PCM-based embedded system. We observe that PCM-FTL can signicantly reduce rite activities of PCM in comparison ith the baseline scheme hftl. For the PCM-based embedded system ith 1GB NAND ash memory, PCM-FTL can achieve an average reduction of 9.1% and a maximum reduction of 98.98% in the maximum number of bit ips. Similarly, for the PCMbased embedded system ith GB NAND ash memory, PCM-FTL can achieve an average reduction of 8.1% and a maximum reduction of 91.18% in the maximum number of bit ips. As shon, PCM-FTL eliminates almost half of rite activities in PCM. In the total number of bit ips, PCM-FTL can achieve an average reduction of 6.% (7.9%) and a maximum reduction of 75.% (95.7%) for the 1GB (GB) NAND ash memory. Therefore, in the PCM-based embedded systems, by applying PCM-FTL, the endurance of PCM is prolonged. ) PCM Wear-Leveling: Wear-leveling is another factor that inuences the endurance of PCM. Figure 6 shos the distribution of the maximum number of bit ips among all mapping table entries in a PCM-based embedded system ith 1GB NAND ash memory. For each subgure, the x-axis shos the number of page-level and block-level mapping table entries in PCM, hile the y-axis shos the maximum number of bit ips extracted from each mapping table entry. To present the distributions clearly, e restrict the maximum number of bit ips on y-axis to 5,. For hftl scheme, e observe that the distribution of bit ips varies a lot, and this may impose a fast orn-out of PCM. Compared ith hftl, PCM-FTL distributes rite activities more evenly among all PCM cells. The experimental results in Table II also illustrate this fact. In summary, PCM- FTL delivers dramatically better reliability than the baseline scheme. V. CONCLUSION AND FUTURE WORK In this paper, e have proposed a rite-activity-aare NAND ash memory management scheme PCM-FTL hich takes the rst step to reduce rite activities in PCMbased embedded systems. In our PCM-FTL, the performance improvement is achieved by preserving a bit in 6

9 (a) hftl / CopyFiles (b) PCM-FTL / CopyFiles (c) hftl / DonFiles (d) PCM-FTL / DonFiles (e) hftl / Ofce (f) PCM-FTL / Ofce (g) hftl / PP (h) PCM-FTL / PP Figure 6. The ear-leveling comparison of hftl and PCM-FTL in a PCM-based embedded system ith 1GB NAND ash memory over four traces. 65

10 a PCM cell from being inverted frequently. Through a to-level mapping mechanism, and a rite-activity-aare strategy, unnecessary rite activities in PCM are directly eliminated. We conducted experiments on a set of realistic I/O orkload collected from daily-life. For a PCM-based embedded system ith 1GB (GB) NAND ash memory, the experimental results sho that the maximum number of bit ips among PCM cells can be reduced by 8.1% (9.1%) on average, and the total number of bit ips of all PCM cells can be reduced by 6.% (7.9%) on average. Furthermore, the results sho that PCM-FTL can evenly distribute rite activities among PCM cells in comparison ith a representative baseline FTL scheme. In our future ork, e ill investigate the energy consumption and thermal issues of PCM to design an energyaare or thermal-aare scheme to improve the performance and reliability of PCM-based embedded systems. ACKNOWLEDGMENT We ould like to thank the anonymous revieers for their valuable feedback and improvements to this paper. The ork described in this paper is partially supported by the grants from the Research Grants Council of the Hong Kong Special Administrative Region, China (GRF PolyU 56/7E and GRF PolyU 569/8E), the Innovation and Technology Support Programme of Innovation and Technology Fund of the Hong Kong Special Administrative Region, China (ITS/8/1), and the Hong Kong Polytechnic University (A-PJ17 and 1-ZV5S). REFERENCES [1] M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, Enhancing lifetime and security of PCM-based main memory ith start-gap ear leveling, in Proceedings of the nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 9), 9, pp. 1. [] M. K. Qureshi, V. Srinivasan, and J. A. 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