Ultra-low power, Single-chip SRAM FPGA Targets Handheld Consumer Applications
|
|
|
- Primrose McBride
- 5 years ago
- Views:
Transcription
1 Hot Chips August 2009
2 Ultra-low power, Single-chip SRAM FPGA Targets Handheld Consumer Applications PMP / Games Netbooks Pico Projectors Smart Phones Power? DSC Cost? New Features? Size? epaper ebook Time to Market? Smart Cards MID POS / ipda GPS 2 Hot Chips August 2009
3 What Solutions does FPGA provide? Cellular Frame Buffer DBB App µp Touch Screen Controller Frame Buffer Interface / Timing Controller Projector Keyboard 1 SiliconBlue ice65 Flash Memory Controller Zoom Motor Ctlr PWM Camera 5-15M Keyboard 2 SDI/MMC/CF+ SD Other New Functions Smart lighting control Quick launch buttons Accelerometer 3 Hot Chips August 2009
4 ice65 FPGA Architecture Ultra low power Array of Programmable Logic Blocks (PLBs) Surrounded by four I/O Banks 4Kbit RAM Blocks Programmable interconnect Non-Volatile Configuration Memory (NVCM) SPI interface 4 Hot Chips August 2009
5 Programmable Logic Block (PLB) Eight 4-input Look-up Tables (LUT4) Eight D flip-flops with shared clock, clock enable, set/reset control Fast carry logic Familiar, well supported by logic synthesis tools 5 Hot Chips August 2009
6 RAM 4K Memory Block Implements variety of functions: Random-access memory (RAM) Single-port RAM with a common address, enable, and clock control lines Two-port RAM with separate read and write control lines, address inputs, and enable Register file and scratchpad RAM First-In, First-Out (FIFO) memory for data buffering applications Circuit buffer 256-deep by 16-wide ROM with registered outputs, contents loaded during configuration Sixteen different 8-input look-up tables Function or waveform tables such as sine, cosine, etc. Correlators or pattern matching operations Counters, sequencers 6 Hot Chips August 2009
7 Programmable Input/Output (PIO) I/O Standards: LVCMOS33 LVCMOS25, LVDS LVCMOS18 LVCMOS18 SubLVDS LVCMOS15 SSTL25 SSTL18 MDDR Connects external components to the PLBs and RAM4K blocks via programmable interconnect Individual pins grouped into 1-of-4 I/O banks Multi-functions I/O Bank #3 has add l functionality LVDS differential I/O Mobile DDR memory interface 7 Hot Chips August 2009
8 Programmable Interconnect Hierarchy of resources: Nearest Neighbor Connections between a PLB and its surrounding neighbors Span4 Connections & switchboxes Span12 Connections & switchboxes 8 Hot Chips August 2009
9 Span4 Connection Resourses 9 Hot Chips August 2009
10 Span12 Connection Resources 10 Hot Chips August 2009
11 Global Routing Resources 11 Hot Chips August 2009
12 Unique Self-Configuration Option (NVCM) Industry s only single chip, SRAM FPGA Reprogrammable, reconfigurable as any SRAM FPGA thru SPI port in milliseconds NVCM configures on power up Secure Uses TSMC 65LP 1 standard CMOS process Smallest die, lowest cost Rapidly ramp volume WLP n WLR n WLR n+1 WLP n+1 VDDIO VDD 0V 0V 1 0 Non-Volatile Configuration Memory (NVCM) Note 1. Two generation competitive lead versus Flash FPGAs 12 Hot Chips August 2009
13 icecube Design Tool Suite Verilog & VHDL Timing driven physical synthesis Magma tools Windows or Linux Power Analysis & Management tools 13 Hot Chips August 2009
14 Power, mw Static Power Required 0for Handheld Power Consumption vs Clock Rate 32kHz Clock Frequency, MHz 3.5K LUTs 12.5% toggle 14 Hot Chips August 2009
15 ice65 mobilefpga Family Features ice65l02 ice65l04 ice65l08 ice65l16 FPGA System Gates ~100K ~200K ~400K ~800K Logic Cells 1,792 3,520 7,680 16,896 Programmable I/O(max I/O / LVDS channels) 128/18 176/20 222/25 384/54 Embedded RAM Bits 64K 80K 128K 384K Sleep current (0 KHz, Vcc=0.8V) 3 µa 5 µa 11 µa 50 µa Dynamic current (32 KHz) 1 8 µa 15 µa 30 µa 75 µa Dynamic current (32 MHz) 1 3 ma 6 ma 12 ma 24 ma Availability NOW NOW NOW Hot Chips August 2009
16 ice65 Small Form Factor Solutions ice DiCE Known Good Die CB132 L02, L04 (95/11) CB196 L04, L08 (150/18) CC72 L08 (55/8).5 mm pitch 4x5 mm CS63 L04 (48/4).4 mm pitch 3x4 mm VQ100 L04 (72/9) 1 CB284 L04, L08, L16 (222/25).5 mm pitch 8x8 mm.5 mm pitch 8x8 mm.5 mm pitch 12x12 mm.5 mm pitch 14x14 mm 1 (Max I/O / Diff Pairs) 16 Hot Chips August 2009
17 Wafer Level Chip Scale Packages Optimized for Small Handheld Products 4.4mm x 4.8mm 72 balls; 0.5mm ball pitch 3.2mm x 3.9mm 63 balls; 0.4mm ball pitch 17 Hot Chips August 2009
18 Small Form Factor WLCSP:.4mm pitch Key Features: ~200K System Gates 48 I/Os; 4 diff pairs Icc0 sleep = 5µA Icc32K = 32KHz 3.2mm x 3.9mm 63 balls Picture of CS63 0.4mm ball pitch 18 Hot Chips August 2009
19 ice65l04 & ice65l08 FPGAs Known Good Die 19 Hot Chips August 2009
20 New Products, New Features, More Revenue 1 st Gen ASSP with Stacked FPGAs Well known ASSP functionality Add new features/capabilities 2 nd Gen ASSP Features Feature Freeze 1 st Gen ASSP Feature Freeze 6 mths 9 mths mths Time 20 Hot Chips August 2009
21 Example SiliconBlue IP: Smartphone Resources Turn-Key Solutions FFs LUTs IOs RAMs 48 Channel PWM Controller with I2C Interface Backlighting Controller with Ambient Light Awareness I2C Port Expansion Demo Decoded Keyboard Output Display on Character LCD Digital Picture Frame with Touch Screen Interactive Control of Tri- Color LEDs with PWM Channel PWM Controller with SPI Interface Voltage Level Translation Demo SPI Port Expansion Demo Processors 8051 Processor Embedded Processor Configuration Interfaces I2C Master I2C Slave IrDA Fast IrDA Standard SPI Master SPI Master for OMAP SPI Slave UART Voltage Level Translation LVDS Serializer LVDS De-Serializer Resources Peripherals FFs LUTs IOs RAMs I2C to GPIO Port Expander Keyboard Matrix Decoder Multi-Function Port Expander PWM Generation SPI to GPIO Port Expander SPI to UART Port Expander Touch Screen Controller UART to UART Port Expander Audio Data Buffer Capacitive Button/Slider Controller MDDI Controller MP3 Decoder Storage MemoryStick Pro Interface SD Interface and Controller SDIO Interface and Controller SD to SD Card Copy SD Full Featured Controller Displays Graphics LCD Controller (320x240, 18-bit color) Capacitive Touchscreen Controller CMOS Imager Interface Dual Display Controller Preview/Review Display Controller SVGA Frame Buffer Memories Cellular RAM Controller NAND Flash Interface MDDR Controller SL to ML NAND Flash Converter MLC NAND Flash Controller 21 Hot Chips August 2009
22 Summary: Best FPGA for Consumer Handheld mobilefpga Green solution Ultra-low power High density Smallest footprint Low price Single chip Key Functions Interfaces Controllers Peripherals Glue logic More.. High Value Benefits Quickly customize offthe-shelf chips Create end product differentiation Simplify functional convergence Improve time-to-market Maximum design flexibility 22 Hot Chips August 2009
I/O Bank 3. 4Kbit RAM 4Kbit RAM NVCM. Nonvolatile Configuration Memory (NVCM)
Handheld ice: ice65 Ultra Low-Power Programmable Logic Family January 26, 2009 (1.4) SiliconBlue Preliminary (SUBJECT TO CHANGE) R First high-density, ultra low-power programmable logic family specifically
NVCM. Nonvolatile Configuration Memory (NVCM)
ice65 Ultra Low-Power mobilefpga Family May 13, 2011 (2.4) SiliconBlue R Data Sheet First high-density, ultra low-power singlechip, SRAM mobilefpga family specifically designed for hand-held applications
ice65 P-Series Ultra-Low Power mobilefpga Family
ice65 P-Series Ultra Low-Power mobilefpga Family April 22, 2011 (1.31) High-density, ultra low-power single-chip, SRAM mobilefpga family specifically designed for hand-held applications and long battery
Field Programmable Gate Array (FPGA)
Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems
AT-501 Cortex-A5 System On Module Product Brief
AT-501 Cortex-A5 System On Module Product Brief 1. Scope The following document provides a brief description of the AT-501 System on Module (SOM) its features and ordering options. For more details please
icecube2 Software Release Notes
July 2012 Version 2012.06 Contents icecube2 Version 2012.06... 2 icecube2 Version 2012.03... 2 icecube2 Version 2011.12... 2 icecube2 Version 2011.09 SP2... 2 icecube2 Version 2011.09 SP1... 3 icecube2
Product Technical Brief S3C2413 Rev 2.2, Apr. 2006
Product Technical Brief Rev 2.2, Apr. 2006 Overview SAMSUNG's is a Derivative product of S3C2410A. is designed to provide hand-held devices and general applications with cost-effective, low-power, and
Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
Product Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006 Overview SAMSUNG's S3C2412 is a Derivative product of S3C2410A. S3C2412 is designed to provide hand-held devices and general applications with cost-effective,
Zynq-7000 All Programmable SoC Product Overview
Zynq-7000 All Programmable SoC Product Overview The SW, HW and IO Programmable Platform August 2012 Copyright 2012 2009 Xilinx Introducing the Zynq -7000 All Programmable SoC Breakthrough Processing Platform
Advanced Digital Design Using FPGA. Dr. Shahrokh Abadi
Advanced Digital Design Using FPGA Dr. Shahrokh Abadi 1 Venue Computer Lab: Tuesdays 10 12 am (Fixed) Computer Lab: Wednesday 10-12 am (Every other odd weeks) Note: Due to some unpredicted problems with
ECE 189A Senior Capstone December 16, 2014 Team Leader: Will Miller Charles Crain, Isaac Flores, Brian Phan, Sarah Pilkington
ECE 189A Senior Capstone December 16, 2014 Team Leader: Will Miller Charles Crain, Isaac Flores, Brian Phan, Sarah Pilkington Agenda Project Overview Parts Power Distribution Schematic and Bill of Materials
MYD-IMX28X Development Board
MYD-IMX28X Development Board MYC-IMX28X CPU Module as Controller Board Two 1.27mm pitch 80-pin SMT Connectors for Board-to-Board Connections 454MHz Freescale i.mx28 Series ARM926EJ-S Processors 128MB DDR2
Solving Today s Interface Challenge With Ultra-Low-Density FPGA Bridging Solutions
Solving Today s Interface Challenges With Ultra-Low- Density FPGA Bridging Solutions August 2013 Lattice Semiconductor 5555 Northeast Moore Ct. Hillsboro, Oregon 97124 USA Telephone: (503) 268-8000 www.latticesemi.com
DATA SHEET. Low power and low cost CPLD. Revision: 1.0. Release date: 10/10/2016. Page 1 of 14
DATA SHEET Revision: 1.0 Release date: 10/10/2016 AG1280 Low power and low cost CPLD Page 1 of 14 General Description AG1280 family provides low cost, ultra-low power CPLDs, with density is 1280 Look-Up
SiliconBlue. SiliconBlue Technologies iceman65 Board. Programmable Solutions for Consumer Handheld. 7-MAY-2008 (v1.
February 2008 1 SiliconBlue SiliconBlue Technologies iceman65 Board Programmable Solutions for Consumer Handheld 7-MAY-2008 (v1.1) February 2008 2 Agenda iceman65 Kit Programming Options More Information
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003 S3C2440X is a derivative product of Samsung s S3C24XXX family of microprocessors for mobile communication market. The S3C2440X s main enhancement
Virtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued)
Virtex-II Architecture SONET / SDH Virtex II technical, Design Solutions PCI-X PCI DCM Distri RAM 18Kb BRAM Multiplier LVDS FIFO Shift Registers BLVDS SDRAM QDR SRAM Backplane Rev 4 March 4th. 2002 J-L
Field Programmable Gate Array
Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational
INTRODUCTION TO FPGA ARCHITECTURE
3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)
Summary. Introduction. Application Note: Virtex, Virtex-E, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro. XAPP152 (v2.1) September 17, 2003
Application Note: Virtex, Virtex-E, Spartan-IIE, Spartan-3, Virtex-II, Virtex-II Pro Xilinx Tools: The Estimator XAPP152 (v2.1) September 17, 2003 Summary This application note is offered as complementary
Outline. Field Programmable Gate Arrays. Programming Technologies Architectures. Programming Interfaces. Historical perspective
Outline Field Programmable Gate Arrays Historical perspective Programming Technologies Architectures PALs, PLDs,, and CPLDs FPGAs Programmable logic Interconnect network I/O buffers Specialized cores Programming
MYD-IMX28X Development Board
MYD-IMX28X Development Board MYC-IMX28X CPU Module as Controller Board Two 1.27mm pitch 80-pin SMT Male Connectors for Board-to-Board Connections 454MHz Freescale i.mx28 Series ARM926EJ-S Processors 128MB
DevKit7000 Evaluation Kit
DevKit7000 Evaluation Kit Samsung S5PV210 Processor based on 1GHz ARM Cortex-A8 core Onboard 512MByte DDR2 and 512MByte NAND Flash 4 UART, 4 USB Host, USB Device, Ethernet, Audio, TF, RTC,... Supports
Field Programmable Gate Array (FPGA) Devices
Field Programmable Gate Array (FPGA) Devices 1 Contents Altera FPGAs and CPLDs CPLDs FPGAs with embedded processors ACEX FPGAs Cyclone I,II FPGAs APEX FPGAs Stratix FPGAs Stratix II,III FPGAs Xilinx FPGAs
S2C K7 Prodigy Logic Module Series
S2C K7 Prodigy Logic Module Series Low-Cost Fifth Generation Rapid FPGA-based Prototyping Hardware The S2C K7 Prodigy Logic Module is equipped with one Xilinx Kintex-7 XC7K410T or XC7K325T FPGA device
INTRODUCTION TO FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
INTRODUCTION TO FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) Bill Jason P. Tomas Dept. of Electrical and Computer Engineering University of Nevada Las Vegas FIELD PROGRAMMABLE ARRAYS Dominant digital design
An Introduction to Programmable Logic
Outline An Introduction to Programmable Logic 3 November 24 Transistors Logic Gates CPLD Architectures FPGA Architectures Device Considerations Soft Core Processors Design Example Quiz Semiconductors Semiconductor
MAX 10 FPGA Device Overview
2014.09.22 M10-OVERVIEW Subscribe MAX 10 devices are the industry s first single chip, non-volatile programmable logic devices (PLDs) to integrate the optimal set of system components. The following lists
The Xilinx XC6200 chip, the software tools and the board development tools
The Xilinx XC6200 chip, the software tools and the board development tools What is an FPGA? Field Programmable Gate Array Fully programmable alternative to a customized chip Used to implement functions
AT45DB041E. 4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory. Features
4-Mbit DataFlash (with Extra 128-Kbits), 1.65V Minimum SPI Serial Flash Memory Features Single 1.65V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Supports RapidS
ECE 189A Senior Capstone October 29, 2014 Team Leader: Will Miller Charles Crain, Isaac Flores, Brian Phan, Sarah Pilkington
ECE 189A Senior Capstone October 29, 2014 Team Leader: Will Miller Charles Crain, Isaac Flores, Brian Phan, Sarah Pilkington Product Description InfiniTable is a fully interactive, multifunctional table
HotChips An innovative HD video and digital image processor for low-cost digital entertainment products. Deepu Talla.
HotChips 2007 An innovative HD video and digital image processor for low-cost digital entertainment products Deepu Talla Texas Instruments 1 Salient features of the SoC HD video encode and decode using
icecube2 Software Release Notes
December, 2016 Version 2016.12 Contents icecube2 Version 2016.12... 4 icecube2 Version 2016.08... 4 icecube2 Version 2016.02... 4 icecube2 Version 2015.08... 4 icecube2 Version 2015.04... 4 icecube2 Version
Smart, simple solutions for the 12 most common design concerns
Smart, simple solutions for the 12 most common design concerns NXP I 2 C-bus solutions 2H 2011 I 2 C-bus: The serial revolution By replacing complex parallel interfaces with a straightforward yet powerful
Low Power Design Techniques
Low Power Design Techniques August 2005, ver 1.0 Application Note 401 Introduction This application note provides low-power logic design techniques for Stratix II and Cyclone II devices. These devices
CrossLink Hardware Checklist Technical Note
FPGA-TN-02013 Version 1.1 August 2017 Contents Acronyms in This Document... 3 Introduction... 4 Power Supplies... 5 CrossLink MIPI D-PHY and PLL Power Supplies... 5 Power Estimation... 6 Configuration
Digital Audio Broadcasting. Xilinx Solutions for DAB Receiver Systems
Digital Audio Broadcasting Xilinx Solutions for DAB Receiver Systems Portable DAB Receiver Issues Adding DAB functionality to existing units Interfacing DAB chipsets to processors Adding other features
Cannon Mountain Dr Longmont, CO LS6410 Hardware Design Perspective
LS6410 Hardware Design Perspective 1. S3C6410 Introduction The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, lowpower capabilities, high performance Application
6.893 Pervasive Computing. Larry Rudolph
6.893 Pervasive Computing Larry Rudolph Course Overview Two sets of students -- MIT and SMA Two parts to class Individual technologies (PS & Quiz) Group projects Materials ipaq, backpaq, cricket,?? Slides,
Today. Comments about assignment Max 1/T (skew = 0) Max clock skew? Comments about assignment 3 ASICs and Programmable logic Others courses
Today Comments about assignment 3-43 Comments about assignment 3 ASICs and Programmable logic Others courses octor Per should show up in the end of the lecture Mealy machines can not be coded in a single
Xynergy It really makes the difference!
Xynergy It really makes the difference! STM32F217 meets XILINX Spartan-6 Why Xynergy? Very easy: There is a clear Synergy achieved by combining the last generation of the most popular ARM Cortex-M3 implementation
Power Solutions for Leading-Edge FPGAs. Vaughn Betz & Paul Ekas
Power Solutions for Leading-Edge FPGAs Vaughn Betz & Paul Ekas Agenda 90 nm Power Overview Stratix II : Power Optimization Without Sacrificing Performance Technical Features & Competitive Results Dynamic
Introduction to ASIC Design
Introduction to ASIC Design Victor P. Nelson ELEC 5250/6250 CAD of Digital ICs Design & implementation of ASICs Oops Not these! Application-Specific Integrated Circuit (ASIC) Developed for a specific application
Intel MAX 10 FPGA Device Overview
Intel MAX 10 FPGA Device Overview Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents...3 Key Advantages of Intel MAX 10 Devices... 3 Summary of Intel MAX 10 Device Features...
Zynq AP SoC Family
Programmable Logic (PL) Processing System (PS) Zynq -7000 AP SoC Family Cost-Optimized Devices Mid-Range Devices Device Name Z-7007S Z-7012S Z-7014S Z-7010 Z-7015 Z-7020 Z-7030 Z-7035 Z-7045 Z-7100 Part
MAX 10 FPGA Device Overview
2016.05.02 M10-OVERVIEW Subscribe MAX 10 devices are single-chip, non-volatile low-cost programmable logic devices (PLDs) to integrate the optimal set of system components. The highlights of the MAX 10
Introduction to Sitara AM437x Processors
Introduction to Sitara AM437x Processors AM437x: Highly integrated, scalable platform with enhanced industrial communications and security AM4376 AM4378 Software Key Features AM4372 AM4377 High-performance
Cyclone III low-cost FPGAs
Cyclone III low-cost FPGAs Unlimited possibilities Your design ideas have the potential to prosper. But, in the end, they are only as good as your ability to execute. Cyclone III FPGAs deliver the value
Introduction. PURPOSE: - List and explain the 15 i.mx1 modules that are also used on the i.mx21 device.
Introduction PURPOSE: - List and explain the 15 i.mx1 modules that are also used on the device. OBJECTIVES: - Identify the similarities and differences between the two devices. - Describe the enhancements
Copyright 2016 Xilinx
Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building
Programmable Logic Devices FPGA Architectures II CMPE 415. Overview This set of notes introduces many of the features available in the FPGAs of today.
Overview This set of notes introduces many of the features available in the FPGAs of today. The majority use SRAM based configuration cells, which allows fast reconfiguation. Allows new design ideas to
The World Leader in High Performance Signal Processing Solutions. DSP Processors
The World Leader in High Performance Signal Processing Solutions DSP Processors NDA required until November 11, 2008 Analog Devices Processors Broad Choice of DSPs Blackfin Media Enabled, 16/32- bit fixed
SAM A5 ARM Cortex - A5 MPUs
SAM A5 ARM Cortex - A5 MPUs Industry s lowest-power MPUs Ideal for secure industry, IoT, wearable applications Operating at 600MHz/945DMIPS with low power consumption, the SAMA5 ARM Cortex-A5 based MPU
Capacitive Touch Based User Interfaces and Hardware-based Solutions
Capacitive Touch Based User Interfaces and Hardware-based Solutions Renesas Electronics America Inc. Renesas Technology & Solution Portfolio 2 Microcontroller and Microprocessor Line-up 2010 2013 32-bit
FPGA VHDL Design Flow AES128 Implementation
Sakinder Ali FPGA VHDL Design Flow AES128 Implementation Field Programmable Gate Array Basic idea: two-dimensional array of logic blocks and flip-flops with a means for the user to configure: 1. The interconnection
8. Migrating Stratix II Device Resources to HardCopy II Devices
8. Migrating Stratix II Device Resources to HardCopy II Devices H51024-1.3 Introduction Altera HardCopy II devices and Stratix II devices are both manufactured on a 1.2-V, 90-nm process technology and
DevKit8000 Evaluation Kit
DevKit8000 Evaluation Kit TI OMAP3530 Processor based on 600MHz ARM Cortex-A8 core Memory supporting 256MByte DDR SDRAM and 256MByte NAND Flash UART, USB Host/OTG, Ethernet, Camera, Audio, SD, Keyboard,
Introduction to Microprocessor
Introduction to Microprocessor Slide 1 Microprocessor A microprocessor is a multipurpose, programmable, clock-driven, register-based electronic device That reads binary instructions from a storage device
INTRODUCTION. icegate
Using icegate in Ultra Low Power ice FPGA INTRODUCTION In today s handheld and portable applications market, power price and space form the crux of the competition, especially with FPGAs and CPLDs playing
Company Profile. Mobile Display. Smart TFT LCD Driver Controller. AV TFT LCD Driver Controller. Capacitive Touch Panel Controller
Content Company Profile Be the dominant provider of display IC products 01 Mobile Display Smart TFT LCD Driver Controller AV TFT LCD Driver Controller Capacitive Touch Panel Controller STN/CSTN LCD Driver
COL862 - Low Power Computing
COL862 - Low Power Computing Power Measurements using performance counters and studying the low power computing techniques in IoT development board (PSoC 4 BLE Pioneer Kit) and Arduino Mega 2560 Submitted
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Lec 26: November 9, 2018 Memory Overview Dynamic OR4! Precharge time?! Driving input " With R 0 /2 inverter! Driving inverter
User s Manual iceprogm1050, icecablem100 and SAB-XXXXX-X V 1.2
09-00156-00 User s Manual iceprogm1050, icecablem100 and SAB-XXXXX-X V 1.2 SiliconBlue Technologies Corporation 2 Table of Contents PROGRAMMING BASICS... 4 CRAM Configuration... 4 NVCM Programming... 4
Basic FPGA Architecture Xilinx, Inc. All Rights Reserved
Basic FPGA Architecture 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Identify the basic architectural resources of the Virtex -II FPGA List the differences
Product specification
MJIOT-AMB-03 Product specification 1 MJIOT-AMB-03module appearance 2 目录 1. Product overview...4 1.1 Characteristic... 5 1.2 main parameters...6 1.2 Interface definition... 7 2. appearance and size... 8
Scheme G. Sample Test Paper-I
Sample Test Paper-I Marks : 25 Times:1 Hour 1. All questions are compulsory. 2. Illustrate your answers with neat sketches wherever necessary. 3. Figures to the right indicate full marks. 4. Assume suitable
ESP-01 WiFi Module Version1.0
ESP-01 WiFi Module Version1.0 sherry@aithinker.com Disclaimer and Copyright Notice. Information in this document, including URL references, is subject to change without notice. THIS DOCUMENT IS PROVIDED
FPGA Implementations
FPGA Implementations Smith Text: Chapters 4-8 Online version at: http://www10.edacafe.com/book/asic/asics.php Topic outline Chapter 4 Programmable ASIC technologies Chapter 5 Programmable logic cells Chapter
The Next Generation 65-nm FPGA. Steve Douglass, Kees Vissers, Peter Alfke Xilinx August 21, 2006
The Next Generation 65-nm FPGA Steve Douglass, Kees Vissers, Peter Alfke Xilinx August 21, 2006 Hot Chips, 2006 Structure of the talk 65nm technology going towards 32nm Virtex-5 family Improved I/O Benchmarking
Abbas El Gamal. Joint work with: Mingjie Lin, Yi-Chang Lu, Simon Wong Work partially supported by DARPA 3D-IC program. Stanford University
Abbas El Gamal Joint work with: Mingjie Lin, Yi-Chang Lu, Simon Wong Work partially supported by DARPA 3D-IC program Stanford University Chip stacking Vertical interconnect density < 20/mm Wafer Stacking
VIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION
VIDEO BRIDGING SOLUTION PROMISES NEW LEVEL OF DESIGN FLEXIBILITY AND INNOVATION May 2016 Lattice Semiconductor 111 5 th Ave., Suite 700 Portland, Oregon 97204 USA Telephone: (503) 268-8000 www.latticesemi.com
Low Power Design. Renesas Electronics America Inc Renesas Electronics America Inc. All rights reserved.
Low Power Design Renesas Electronics America Inc. Renesas Technology & Solution Portfolio 2 Microcontroller and Microprocessor Line-up 2010 2012 32-bit 8/16-bit 1200 DMIPS, Superscalar Automotive & Industrial,
! Program logic functions, interconnect using SRAM. ! Advantages: ! Re-programmable; ! dynamically reconfigurable; ! uses standard processes.
Topics! SRAM-based FPGA fabrics:! Xilinx.! Altera. SRAM-based FPGAs! Program logic functions, using SRAM.! Advantages:! Re-programmable;! dynamically reconfigurable;! uses standard processes.! isadvantages:!
Incorporating a Capacitive Touch Interface into Your Design
Incorporating a Capacitive Touch Interface into Your Design Renesas Electronics America Inc. Renesas Technology & Solution Portfolio 2 Microcontroller and Microprocessor Line-up 2010 2012 32-bit 8/16-bit
MYC-C437X CPU Module
MYC-C437X CPU Module - Up to 1GHz TI AM437x Series ARM Cortex-A9 Processors - 512MB DDR3 SDRAM, 4GB emmc Flash, 32KB EEPROM - Gigabit Ethernet PHY - Power Management IC - Two 0.8mm pitch 100-pin Board-to-Board
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history
Semiconductor Memory Classification. Today. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. CPU Memory Hierarchy.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec : April 4, 7 Memory Overview, Memory Core Cells Today! Memory " Classification " ROM Memories " RAM Memory " Architecture " Memory core " SRAM
Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?
EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic
S1C33E07 CMOS 32-bit Application Specific Controller
CMOS 32-bit Application Specific Controller DESCRIPTIONS 32-bit RISC CPU-Core Optimized for SoC (EPSON S1C33 PE) Built-in 8KB RAM SDRAM Controller with Burst Control Generic DMA Controller (HSDMA/IDMA)
Tim Chin Omar Gonzalez Ward Huang. Critical Design Review
Tim Chin Omar Gonzalez Ward Huang Critical Design Review » Music player that plays custom songs and playlists based on multiple factors including: Lighting (artificial, natural, brightness) Time of day
Age nda. Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications
Intel PXA27x Processor Family: An Applications Processor for Phone and PDA applications N.C. Paver PhD Architect Intel Corporation Hot Chips 16 August 2004 Age nda Overview of the Intel PXA27X processor
ice65 mobilefpga Configuration & Programming Overview 05/12/2010
ice65 mobilefpga Configuration & Programming Overview 05/12/2010 Configuration vs. Programming CONFIGURATION ice65 is a standard SRAM FPGA (reconfigurable) During power up, a configuration image is loaded
MYD-SAMA5D3X Development Board
MYD-SAMA5D3X Development Board MYC-SAMA5D3X CPU Module as Controller Board DDR2 SO-DIMM 200-pin Signals Consistent with Atmel's Official Board 536MHz Atmel SAMA5D3 Series ARM Cortex-A5 Processors 512MB
Introduction to Microcontroller Apps for Amateur Radio Projects Using the HamStack Platform.
Introduction to Microcontroller Apps for Amateur Radio Projects Using the HamStack Platform www.sierraradio.net www.hamstack.com Topics Introduction Hardware options Software development HamStack project
Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications
Session 8D-2 Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi,
FIELD PROGRAMMABLE GATE ARRAYS (FPGAS)
FIELD PROGRAMMABLE GATE ARRAYS (FPGAS) 1 Roth Text: Chapter 3 (section 3.4) Chapter 6 Nelson Text: Chapter 11 Programmable logic taxonomy Lab Device 2 Field Programmable Gate Arrays Typical Complexity
EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007
EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200
Introduction to FPGAs. H. Krüger Bonn University
Introduction to FPGAs H. Krüger Bonn University Outline 1. History 2. FPGA Architecture 3. Current Trends 4. Design Methodology (short see other lectures) Disclaimer: Most of the resources used for this
Axcelerator Family FPGAs
Product Brief Axcelerator Family FPGAs u e Leading-Edge Performance 350+ MHz System Performance 500+ MHz Internal Performance High-Performance Embedded s 700 Mb/s LVDS Capable I/Os Specifications Up to
NXP Unveils Its First ARM Cortex -M4 Based Controller Family
NXP s LPC4300 MCU with Coprocessor: NXP Unveils Its First ARM Cortex -M4 Based Controller Family By Frank Riemenschneider, Editor, Electronik Magazine At the Electronica trade show last fall in Munich,
AT45DB321E. Features. 32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum SPI Serial Flash Memory
32-Mbit DataFlash (with Extra 1-Mbits), 2.3V Minimum SPI Serial Flash Memory Features Single 2.3V - 3.6V supply Serial Peripheral Interface (SPI) compatible Supports SPI modes 0 and 3 Supports RapidS operation
ProASIC PLUS FPGA Family
ProASIC PLUS FPGA Family Key Features Reprogrammable /Nonvolatile Flash Technology Low Power Secure Single Chip/Live at Power Up 1M Equivalent System Gates Cost Effective ASIC Alternative ASIC Design Flow
NXP Microcontrollers Selection Guide
November 2012 NXP Microcontrollers Selection Guide NXP LPC family of microcontrollers is changing the landscape for embedded applications. Featuring award-winning innovations in connectivity, flexibility,
FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011
FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level
Military Grade SmartFusion Customizable System-on-Chip (csoc)
Military Grade SmartFusion Customizable System-on-Chip (csoc) Product Benefits 100% Military Temperature Tested and Qualified from 55 C to 125 C Not Susceptible to Neutron-Induced Configuration Loss Microcontroller
ice40 LP/HX Family Data Sheet
FPGA-DS-02029-3.5 September 2018 Contents Acronyms in This Document... 5 1. General Description... 6 1.1. Features... 6 2. Product Family... 7 3. Architecture... 8 3.1. Architecture Overview... 8 3.1.1.
Introducing: New Low-Cost & Low Pin Count PIC Microcontrollers for the 8-, 16- & 32-bit Markets
Introducing: New Low-Cost & Low Pin Count PIC Microcontrollers for the 8-, 16- & 32-bit Markets PIC MCU and dspic DSC Family Portfolio 2 New Low Cost, Low Pin-Count 8-, 16-, 32-bit Offerings 3 What Are
FPGA for Software Engineers
FPGA for Software Engineers Course Description This course closes the gap between hardware and software engineers by providing the software engineer all the necessary FPGA concepts and terms. The course