Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications

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1 Session 8D-2 Development of Low Power and High Performance Application Processor (T6G) for Multimedia Mobile Applications Yoshiyuki Kitasho, Yu Kikuchi, Takayoshi Shimazawa, Yasuo Ohara, Masafumi Takahashi, Yoshio Masubuchi, Yukihito Oowaki Toshiba Corporation Semiconductor Company Jan. 28, 2011

2 Outline Background Chip Overview Stacked DRAM Architecture Multiple Power Domain Control Chip Power Consumption Summary 2

3 Background

4 Chip Concept Low Power Full-HD video 3D/2D graphics H.264, MPEG-4/2, VC-1, MP3, eaac+, WMA HW engine SCS Multiprocessor Hybrid application processor MPC HW engine : High performance (Full-HD video, 3D/2D graphics) & Low power Multiprocessor : Various multimedia applications (H.264, MPEG-4/2, VC-1, MP3, eaac+, WMA ) Stacked Chip SoC (SCS) : High memory bandwidth & Low power Multiple Power domain Control (MPC) : Low power 4

5 Chip Overview

6 Block Diagram Hybrid application T6G processor Host CPU NOR Flash NAND Flash Host I/F ARM Cortex -A9 MPCore Key I/F MEMC Display I/F MIPI DSI x3 Image composition HDMI Driver Full-HD TV LCD Panel Video/Audio multiprocessor JPEG OFDM/RF SCS-DRAM x4 DDR-SDRAM 3D/2D graphics engine Full-HD video H.264 Codec engine 128 bits x 4 ch 32 bits General controller TS I/F DMAC DRAMC x4 Camera I/F MIPI CSI2 x2 Audio I/F SDHC I2C SPI UART IR GPIO DDRC Sub Bus 32bits Main Bus 128bits x 4 Camera Module 6

7 Video/Audio Multiprocessor MPE MPE MPE I$ D$ MPE I$ D$ MPE I$ D$ MPE I$ D$ I$ D$ I$ D$ L2$ SRAM L2$ controller 8 Media Processing Engines (MPEs) L1$ (I$ 16KB / D$ 8KB) L2$ controller L2$ SRAM 256KB Others : Assistant logic for specific video codec MPE I$ D$ MPE I$ D$ Others 7

8 Camera High Speed I/O Micrograph Technology 40 nm CMOS, triple-well,7-layer-metal Chip size 6.0 mm x 6.2 mm PLL PLL PLL PLL Gate counts JPEG/ Scaling Video/Audio multiprocessor Main bus A ARM processor Micro Bump Main bus B Micro Bump Main bus C Main bus D Image composition Full-HD video H.264 Codec engine Display 3D/2D graphics engine PLL 18.5 M gates (Logic), 9 M bit (SRAM) Clock frequency 435 MHz(ARM), 400 MHz(HS I/O), 333 MHz(Video/Audio), 255MHz(H.264 dec.), 166 MHz(Main bus, HS peripheral), 83 MHz(Sub bus, LS peripheral) CPU ARM Cortex -A9 MPCore (I$:16 KB, D$:16 KB) x2 Video/Audio MPE x8 H.264 Full-HD Video CPU x2 TS CPU x1 General CPU x1 External memory I/F DRAM 128 bits x 4 ch. 166 MHz (SCS ) Mobile-DDR SDRAM 32 bit 166 MHz (SIP) 8

9 Stacked DRAM Architecture

10 SCS Technology RDL (Re-Distribution Layer) Wire Memory chip Micro bump Wire Logic chip Micro bump Logic chip Memory chip Base package Base package Type 1 Type 2 Logic Chip > Memory Chip Logic Chip < Memory Chip 10

11 Stacked DRAM Flow Logic wafer Memory wafer RDL RDL Micro bump Micro bump Dicing CoC Logic Memory 11

12 Using the same memory chip with different logic chip RDL Memory chip Micro bump RDL Memory chip Memory chip Logic chip (A) Memory chip Logic chip (B) Memory chip Various products used same memory chip 12

Memory Density [bit] 32M 64M 256M edram Process edram Solution 512M 1G

(1Gbit) Next Generation This Product (512Mbit) SCS-DRAM (Type2) Next

DRAM Process Previous Product (48Mbit) SCS-DRAM (Type1) 90nm Commodity

SCS Solution by 90nm Toshiba edram Process One Chip Solution by 65nm

13 Memory Density [bit] 32M 64M 256M edram Process edram Solution 512M 1G Commodity DRAM Process SCS Solution 2G SCS Roadmap Next Product (A) (1Gbit) Next Generation This Product (512Mbit) SCS-DRAM (Type2) Next Product (B) (512Mbit) SCS-DRAM (Type2) SCS-DRAM (Type2) 65nm Commodity DRAM Process Previous Product (48Mbit) SCS-DRAM (Type1) 90nm Commodity DRAM Process SCS-DRAM (Type1) SCS Solution by 65nm Toshiba edram Process SCS Solution by 90nm Toshiba edram Process One Chip Solution by 65nm Toshiba edram One Chip Solution by 90nm Toshiba edram Calendar Year

14 Multiple Power Domain Control

Chip Power Domain 3 4 5 6 7 12 21 22 2 8 9 10 11 1 20 24 a 13 a 18 15 23 16 17 14 19 25 (2)-(11) Video/Audio multiprocessor (17) Full-HD video H.

15 Chip Power Domain a 13 a (2)-(11) Video/Audio multiprocessor (17) Full-HD video H.264 Codec engine (19) 3D/2D graphics engine (20)-(22) ARM processor (15) Camera I/F (14) Display I/F (16) Image composition (12) JPEG/Video scaling (1)(13)(18)(23) Main bus (24) Control bus / Peripheral I/F (25) I/O (a) SCS-DRAM I/F 15

Chip power domain by Use Case 3 4 5 6 7 12 21 22 Audio playback 2 8 9 10 1 20 11 24 13 18 1 5 23 16 17 14 19 25 Audio playback + Video decoding + LCD

16 Chip power domain by Use Case Audio playback Audio playback + Video decoding + LCD out L2$ SRAM & controller (2) + 1MPE (3) L2$ SRAM & controller(2) + 8MPEs (3)-(10) 16

17 Power Supply System Chart VDD1D(1.1 V) On-chip LV-PMOS switch VDD1P(1.1 V) (24) (1) (2) (23) (25) VSS System I/O 23 power domains are controlled by on-chip switches 17

18 Chip Power Consumption

19 Leakage Current All On Mode Sleep Mode Standby Mode Power Mode Turn On Domain Power Standby Mode 25 15μW Sleep Mode 24,25 1.7mW All On Mode 1,2,3,4,5,6,7,8,,24,25 22mW Vdd = 1.1 V, Process = center, Temp. = 25 deg.c. 19

20 Measured power (mw) Comparison with previous work nm vs. 65nm HW vs. SW This work H p Enc. 40 nm, 1.1 V 333 MHz Previous work A H p Enc. 40 nm, 1.1 V 333 MHz Previous work B H p Enc. 65 nm, 1.2 V 333 MHz The HW engine achieves low power compare with SW 20

21 Hardware Based Solution Application Scenario Resolution Frame Rate Power 1920x fps 222 mw High Profile Decoding 640x fps 71 mw H x fps 232 mw High Profile Encoding 1280x fps 132 mw 3D OpenGL ES M polygon/s 124 mw Vdd = 1.1 V, Process = center, Temp. = 25deg.C. The HW engine achieves high performance with low power consumption 21

22 Software Based Solution Application Scenario Audio Option Resolution Frame Rate MPEG-4 H.264 Number of Active MPE Power Simple Profile Dec. None 640x fps 7 MPEs 79 mw Main Profile at High Level Dec. AAC Dec. 48 khz 256 kbps stereo x 2 854x480x2 30 fps 8 MPEs None 960x fps 8 MPEs 237 mw 249 mw Simple Profile Enc. None 320x fps 7 MPEs 72 mw Baseline Profile Dec. None 320x fps 3 MPEs 37 mw AAC Dec. 48 khz 128 kbps stereo 320x fps 3 MPEs 42 mw High Profile Dec. None 640x fps 2 MPEs 70 mw Baseline Profile Enc. AAC Enc. 48 khz 64 kbps stereo 320x fps 7 MPEs 79 mw None 854x fps 8 MPEs 315 mw Vdd = 1.1 V, Process = center, Temp. = 25deg.C. The multiprocessor achieves the same degree of low power as the HW engine using 2 MPEs by multiple power domain control at H.264 VGA 15fps decoding. 22

23 Summary

24 Summary Hybrid application processor HW Solution H.264 Full-HD 30fps decoding : 222mW 3D / 2D graphics : 40M polygons/s, 300M pixels/s SW solution H.264 VGA 15fps decoding : 71mW SCS technology Peak memory bandwidth : 10.6GB/s Four 128-bit channels at 2.4GB/s : 3.9mW Multiple power domain control Power domains : controllable 23 of 25 power domains Total leakage power : 1.7mW (sleep mode) The chip achieves low power at high performance for Mobile Market. 24

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