Cover Page. The following handle holds various files of this Leiden University dissertation:

Transcription

1 Cover Page The following handle holds various files of this Leiden University dissertation: Author: Spasic, J. Title: Improved hard real-time scheduling and transformations for embedded Streaming Applications Issue Date:

2 Improved Hard Real-Time Scheduling and Transformations for Embedded Streaming Applications Jelena Spasić

3

4 Improved Hard Real-Time Scheduling and Transformations for Embedded Streaming Applications PROEFSCHRIFT ter verkrijging van de graad van Doctor aan de Universiteit Leiden, op gezag van Rector Magnificus Prof.mr. C.J.J.M. Stolker, volgens besluit van het College voor Promoties te verdedigen op dinsdag 14 november 2017 klokke 13:45 uur door Jelena Spasić geboren te Trgovište, Servië in 1984

5 Promotor: Prof. dr. Joost N. Kok Universiteit Leiden Co-Promotor: Dr. Todor P. Stefanov Universiteit Leiden Promotion Committee: Prof. dr. Alix Munier Kordon Université de Paris - LIP6 Prof. dr. Petru Eles Linköpings Universitet Dr. Andy Pimentel Universiteit van Amsterdam Prof. dr. Aske Plaat Universiteit Leiden Prof. dr. Jaap van den Herik Universiteit Leiden Prof. dr. Harry Wijshoff Universiteit Leiden Improved Hard Real-Time Scheduling and Transformations for Embedded Streaming Applications Jelena Spasić. - Dissertation Universiteit Leiden. - With ref. - With summary in Dutch. Copyright c 2017 by Jelena Spasić. All rights reserved. Cover designed by Miloš Ačanski. This dissertation was typeset using L A TEX. ISBN Printed by Ridderprint, Ridderkerk, The Netherlands.

6 Mojoj porodici To my family

7

8 Contents Table of Contents List of Figures List of Tables List of Abbreviations vii xi xiii xv 1 Introduction Trends in the Design of Embedded Streaming Systems Platform Trend: Multi-Processor System-on-Chip (MPSoC) Design Trend: Model-based Design Methodology Design Requirements and Basic Approaches to Meet the Requirements Timing Requirements Energy Requirements Problem Statement Problem Problem Problem Problem Research Contributions Thesis Outline Background Dataflow Models-of-Computations (MoCs) Cyclo-Static Dataflow (CSDF) Polyhedral Process Network (PPN) Real-Time Scheduling Theory Task Model

9 viii Contents System Model Real-Time Scheduling Algorithms Uniprocessor Schedulability Analysis Multiprocessor Schedulability Analysis Hard Real-Time Scheduling Framework Problem Statement Contributions Related Work Motivational Example Improved Hard Real-Time Scheduling of CSDF Deriving Periods of Tasks Deriving the Earliest Start Time of Actor s First Phase Deriving Channel Buffer Sizes Hard Real-Time Schedulability Performance Analysis Deriving the Number of Processors Evaluation Performance of the ISPS Approach Time Complexity of the ISPS Approach Reducing Latency under ISPS Discussion Exploiting Parallelism in Hard Real-Time Systems to Maximize Performance Problem Statement Contributions Related Work Motivational Example New Unfolding Transformation for SDF Graphs The Algorithm for Finding Proper Unfolding Factors Evaluation Efficiency of the Proposed Unfolding Transformation Performance of Algorithm Time Complexity of Algorithm Discussion Exploiting Parallelism in Hard Real-Time Systems to Minimize Energy Problem Statement

10 Contents ix 5.2 Contributions Related Work Motivational Example System Model Energy Model The Proposed Energy Minimization Approach The Data-Parallel Energy Minimization Algorithm Task Classification for Energy Minimization Task Mapping for Energy Minimization Evaluation Comparison with [CKR14], [LSCS15], [SDK13] on Heterogeneous MPSoCs Comparison with [Lee09] on Heterogeneous MPSoCs Comparison on Homogeneous MPSoC Overhead and Time Complexity Analysis Discussion An Accurate Energy Modeling of Streaming Systems Problem Statement Contributions Related Work System Model Application Model Platform Model Application-to-Platform Mapping Energy Model Model Formulation Derivation of Model Parameters Evaluation of the Energy Model Discussion Summary and Conclusions 133 Bibliography 137 Samenvatting 153 List of Publications 156 Curriculum Vitae 159

11 x Contents Acknowledgments 161

12 List of Figures 1.1 An MPSoC platform example Motion JPEG encoder application A CSDF graph G Example of a PPN (a) and the structure of process P3 (b) (a) The SPS and (b) ISPS of graph G in Figure The periodic schedule σ for the CSDF graph G shown in Figure Production and consumption curves on edge e u = (v i, v j ) An SDF graph G Equivalent graphs of the SDF graph in Figure 4.1 by unfolding actor v 2 by factor 2 and v 3 by factor Unfolding channel e 2 from the graph in Figure 4.1 by using Algorithm 3 when f = [1, 2, 3, 1, 1] Comparison of our unfolding transformation to the approaches in [KM08], [FKBS11], [SLA12], [ZBS13] Results of performance evaluation of our proposed approach in comparison to the approach in [ZBS13] Results of time evaluation of our proposed approach in comparison to the approach in [ZBS13] An SDF graph G A CSDF graph G obtained by unfolding SDF graph G in Figure 5.1 with f = [1, 2, 2, 1] Comparison of our proposed DPEM approach with related approaches on heterogeneous MPSoCs Comparison between DPEM and WYL on heterogeneous MP- SoCs Comparison on homogeneous MPSoC

13 xii List of Figures 6.1 The read primitive implemented in software (a) and hardware (b) The architecture template of MPSoC platforms

14 List of Tables 2.1 Summary of mathematical notations Throughput, latency and number of processors for G under different scheduling schemes Benchmarks used for evaluation Comparison of different scheduling approaches Time complexity (in seconds) of different scheduling approaches Time complexity (in seconds) for the calculation of number of processors Performance of the ISPS approach under different latency constraints Results for G transformed by different transformation approaches Results for G transformed and mapped on 2 processors by different approaches Benchmarks used for evaluation Different MPSoC designs for G in Figure Benchmarks used for evaluation Accuracy of the energy model for CB, ShB and P2P MPSoC platforms Accuracy of the energy estimation when contention is not considered in the model

15

16 List of Abbreviations ADF BF BFD CDP CPU CSDF DCT DLP DM DPEM DSE EDF EE ESL FF FFD FFID FIFO Affine Dataflow Best-Fit Best-Fit Decreasing Constrained-Deadline Periodic Central Processing Unit Cyclo-Static Dataflow Discrete Cosine Transform Data-Level Parallelism Deadline Monotonic Data Parallel Energy Minimization Design Space Exploration Earliest Deadline First Energy Efficient Electronic System-Level First-Fit First-Fit Decreasing First-Fit Increasing Deadlines First-In First-Out xv

17 xvi List of Tables FPGA GPU HSDF ICP IDP ILP ISA ISPS ISS ITRS KPN LLF LP LTE MIDCP MJPEG MoC MPSoC NoC NP PE PLP PM PPN Field-Programmable Gate Array Graphics Processing Unit Homogeneous SDF Integer Convex Programming Implicit-Deadline Periodic Integer Linear Programming Instruction-Set Architecture Improved Strictly Periodic Scheduling Instruction Set Simulators International Technology Roadmap for Semiconductors Kahn Process Network Least Laxity First Linear Programming Long-Term Evolution Mixed Integer Disciplined Convex Programming Motion JPEG Model of Computation Multi-Processor System-on-Chip Network-on-Chip Non-deterministic Polynomial-time Performance Efficient Pipeline-Level Parallelism Power Management Polyhedral Process Network

18 List of Tables xvii PS RM RSD RTA RTL SDF SPS STS TLP VFS VLE WCET WF WFD Periodic Scheduling Rate Monotonic Reed Solomon Decoder Response Time Analysis Register-Transfer-Level Synchronous Data Flow Strictly Periodic Scheduling Self-timed Scheduling Task-Level Parallelism Voltage-Frequency Scaling Variable Length Encoder Worst-Case Execution Time Worst-Fit Worst-Fit Decreasing

19