Programming Heterogeneous Embedded Systems for IoT

Transcription

1 Programming Heterogeneous Embedded Systems for IoT Jeronimo Castrillon Chair for Compiler Construction TU Dresden Get-together toward a sustainable collaboration in IoT April 18 th, Tunis, Tunisia

2 Internet of things Distributed Energy efficient Real time Resource constrained Highly heterogeneous Source: Open clipart Multiple domains 2 J. Castrillon. Get-together for IoT, Apr. 2016

3 Internet of things Distributed Energy efficient Real time IoT/Systems-of-Systems: Extremely hard to program and reason about Resource constrained Highly heterogeneous Source: Open clipart Multiple domains 3 J. Castrillon. Get-together for IoT, Apr. 2016

4 Independent nodes: Trends PE Count in SoCs MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Number of PEs OMAP1 OMAP Family Snapdragon Family OMAP2 OMAP4470 OMAP4430 OMAP3640 OMAP3530 S3 MSM8060 S1 QSD8650 S2 MSM8255 OMAP5430 S4 APQ8064 S4 MSM Year [Castrill14] Single node: HW complexity SW complexity Increasing heterogeneity Complex interconnect Increasing number of cores Not anymore a simple control loop Need expressive programming models 4 J. Castrillon. Get-together for IoT, Apr. 2016

5 Independent nodes: Trends PE Count in SoCs MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Number of PEs OMAP1 OMAP Family Snapdragon Family OMAP2 OMAP4470 OMAP4430 OMAP3640 OMAP3530 S3 MSM8060 S1 QSD8650 S2 MSM8255 OMAP5430 S4 APQ8064 S4 MSM Year [Castrill14] Single node: HW complexity SW complexity Increasing heterogeneity Complex interconnect Increasing number of cores Not anymore a simple control loop Need expressive programming models 5 J. Castrillon. Get-together for IoT, Apr. 2016

6 Outline Introduction Models of computation Tool flows Outlook for IoT Summary 6 J. Castrillon. Get-together for IoT, Apr. 2016

7 Outline Introduction Models of computation Tool flows Outlook for IoT Summary 7 J. Castrillon. Get-together for IoT, Apr. 2016

8 What is a MoC? A model of computation is the definition of the set of allowable operations used in computation and their respective costs. It is used for measuring the complexity of an algorithm in execution time and or memory space Wikipedia: From computational theory Model of computations are abstract specifications of how a computation can progress OfComputation A Model of computation is a collection of rules that govern the interaction of components 8 J. Castrillon. Get-together for IoT, Apr Ptolemaeus, C. (Ed.). System Design, Modeling, and Simulation using Ptolemy II Ptolemy.org, 2014

9 (Parallel) Models of Computation (MoCs): Rules A Model of computation is a collection of rules that govern the interaction of components What are the components Threads, processes, actors, tasks or procedures Execution and concurrency Order and determinism Communication mechanisms: How do components exchange data Asynchronous or rendezvous, perfect or lossy Ptolemaeus, C. (Ed.). System Design, Modeling, and Simulation using Ptolemy II Ptolemy.org, J. Castrillon. Get-together for IoT, Apr. 2016

10 Why MoCs? Depending on the rules, MoCs feature different properties Properties Relate to the power: what can be computed with the model Makes it easier for automatic tools to understand and synthesize code E.g., compile-time optimization, support resource constraints, Examples Can the application run on bounded memory? Can we compute the maximal throughput? Is the execution deterministic? 10 J. Castrillon. Get-together for IoT, Apr. 2016

11 MoCs: Overview For IoT in general: Mixture of MoCs interacting (across different domains. In this talk: Software (concurrent, dataflow + PN + time) Ptolemaeus, C. (Ed.). System Design, Modeling, and Simulation using Ptolemy II Ptolemy.org, J. Castrillon. Get-together for IoT, Apr. 2016

12 Homogeneous Synchronous Dataflow (HSDF) Graph with simple execution semantics e4 e4 e4 a1 a2 a3 e1 e3 e2 a1 a2 a3 e1 e3 e2 a1 a2 a3 e1 e3 e2 Functional, graph model can be extended to model Bounded buffers Schedules a1 a2 c 12 J. Castrillon. Get-together for IoT, Apr. 2016

13 HSDF: schedules Overlapping schedule How to delay the execution of a3?, how to prevent a4 from executing earlier? a2 a3 PE2 a3 a2 a3 a2 a3 a2 a1 a4 PE1 a4 a1 a4 a1 a4 a1 Time 13 J. Castrillon. Get-together for IoT, Apr. 2016

14 Outline Introduction Models of computation Tool flows Outlook for IoT Summary 14 J. Castrillon. Get-together for IoT, Apr. 2016

15 Programming flow: Overview MoC-based Application Non-functional specification Architecture model MEM subsystem DMAs, semaphores PMU L2 Analysis Synthesis Code generation VLIW DSP,L2 NoC Peripherals [Castrill11a] Communication support HW ueues Network Processor Packet DMA PNargs_ifft_r.ID = 6U; PNargs_ifft_r.PNchannel_fre_coef = filtered_coe PNargs_ifft_r.PNnum_fre_coef = 0U; PNargs_ifft_r.PNchannel_time_coef = sink_right; PNargs_ifft_r.channel = 1; sink_left = IPCllmrf_open(3, 1, 1); sink_right = IPCllmrf_open(7, 1, 1); PNargs_sink.ID = 7U; PNargs_sink.PNchannel_in_left = sink_left; PNargs_sink.PNnum_in_left = 0U; PNargs_sink.PNchannel_in_right = sink_right; PNargs_sink.PNnum_in_right = 0U; taskparams.arg0 = (xdc_uarg)&pnargs_src; taskparams.priority = 1; ti_sysbios_knl_task_create((ti_sysbios_knl_task_func &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_fft_l; taskparams.priority = 1; ti_sysbios_knl_task_create((ti_sysbios_knl_task_func ft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_ifft_r; taskparams.priority = 1; ti_sysbios_knl_task_create((ti_sysbios_knl_task_func fft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_sink; taskparams.priority = 1; 15 J. Castrillon. Get-together for IoT, Apr. 2016

16 Application model: Beyond HSDF SDF: Popular model for static applications Possible to derive euivalent HSDF Dynamic DF (DDF): For dynamic applications Flexible firing rules (even non-determinism) 2 e a1 a2 a3 e1 e3 6 2 e2 i1 a1 a2 a3 1 Kahn Process Networks (KPN): Also dynamic Deterministic No firing semantics i2 e4 p1 p2 p3 e1 e3 16 J. Castrillon. Get-together for IoT, Apr e2

17 Non/extra-functional: Constraints Timing constraints Process throughput Latencies along paths 1 ms 3 ms 1 ms Time triggering Mapping constraints Processes to processors Channels to primitives Platform constraints Subset of resources (processors or memories) Utilization 17 J. Castrillon. Get-together for IoT, Apr. 2016

18 Architecture model Key for retargetable tool flows Abstract for speed Relevant components: processors (types), interconnect and memories MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA Why? Understand effect of executing an actor on the different resources for a schedule PE2 PE1 a4 a3 a1 a2 a4 a3 a1 a2 a4 a3 a1 a2 Time 18 J. Castrillon. Get-together for IoT, Apr. 2016

19 Modeling processors Abstract models with functional units, latencies [Eusse14] Execution counts, branch stats and execution traces 19 J. Castrillon. Get-together for IoT, Apr. 2016

20 Modeling communication High-level: Available APIs for implementing application channels Benchmarking for different platforms Duo-PE3 VDSP RISC Duo-PE2 VDSP RISC FPGA- Interface ADPLL Router (1,0) hs-serial Router (0,0) Duo-PE0 VDSP RISC Duo-PE1 VDSP RISC FEC Tomahawk2_core hs-serial hs-serial CM APP Duo-PE7 VDSP RISC Router (1,1) hs-serial Router (0,1) UART- GPIO parallel Duo-PE4 VDSP RISC ADPLL DDR- SDRAM- Interface [Oden13] AVS Contr. [Arnold13] SD Duo-PE6 VDSP RISC hs-serial Duo-PE5 VDSP RISC 20 J. Castrillon. Get-together for IoT, Apr. 2016

21 Modeling communication High-level: Available APIs for implementing application channels Benchmarking for different platforms Duo-PE3 VDSP RISC Duo-PE2 VDSP RISC FPGA- Interface ADPLL AVS Contr. Router (1,0) hs-serial Router (0,0) [Arnold13] Duo-PE0 VDSP RISC Duo-PE1 VDSP RISC FEC SD Tomahawk2_core hs-serial hs-serial CM APP Duo-PE7 VDSP RISC Duo-PE6 VDSP RISC hs-serial Router (1,1) hs-serial Router (0,1) UART- GPIO parallel Duo-PE4 VDSP RISC Duo-PE5 VDSP RISC ADPLL DDR- SDRAM- Interface [Oden13] J. Castrillon. Get-together for IoT, Apr. 2016

22 Analysis and synthesis: Overview For dynamic models! Application specification Analysis: Instrumentation, profiling, tracing Seuential performance estimation Time-annotated traces Architecture model Mapping and scheduling Parallel perf. estimation Mapping configuration Non-functional specification Increase resources 22 J. Castrillon. Get-together for IoT, Apr. 2016

23 Tracing: Dealing with dynamic behavior KPNs do not have firing semantics White model of processes: source code analysis and tracing Tracing: instrumentation, token logging and event recording Tracing Mapping Resources Se. perf. estimation Par. perf. estimation Elapsed time from processor models 23 J. Castrillon. Get-together for IoT, Apr. 2016

24 Trace-based synthesis Non-functional specification Mapping, scheduling, buffer sizing Mapping configuration Tracing Mapping Resources Se. perf. estimation Par. perf. estimation Time-annotated traces t t t Architecture model [Castrill10, Castrill10b, Castrill13] Synthesis based on code and trace analysis (using simple heuristics) Mapping of processes and channels Scheduling policies Buffer sizing 24 J. Castrillon. Get-together for IoT, Apr. 2016

25 Mapping, scheduling and buffer sizing Graph representation of event traces Reason about deadlocks Find critical path Tracing Mapping Resources Se. perf. estimation Par. perf. estimation... [Castrill12] Downside: For dynamic portions of the application, graph is input dependent 25 J. Castrillon. Get-together for IoT, Apr. 2016

26 Multiple traces (ongoing work) Different input à different behavior (traces) Characterize behaviors and impact on mapping performance Tracing Mapping Resources Se. perf. estimation Par. perf. estimation... Mapping configuration... Mapping configuration [Goens15]... Mapping configuration 26 J. Castrillon. Get-together for IoT, Apr. 2016

27 Multiple traces (2) Different input à different behavior (traces) Characterize behaviors and impact on mapping performance Tracing Mapping Resources Se. perf. estimation Par. perf. estimation... Mapping configuration Performance... Mapping configuration [Goens15] Behavior... Mapping configuration 27 J. Castrillon. Get-together for IoT, Apr. 2016

28 Parallel performance estimation Mapping configuration Trace Replay Module (TRM) Context switch Blocked time... Tracing Mapping Resources Se. perf. estimation Par. perf. estimation Time-annotated traces t t t Architecture model t Grantt Chart, platform utilization, channel profiles,... Discrete event simulator to evaluate a solution Replay traces according to mapping Extract costs from architecture file (NoC modeling, context switches, communication) 28 J. Castrillon. Get-together for IoT, Apr. 2016

29 Increasing resources Add resources to the synthesis until constraints are met Tracing Mapping Se. perf. estimation Par. perf. estimation Mapping and scheduling Parallel perf. estimation Resources Increase resources Add processors and memories Easy for homogeneous platforms Non trivial for heterogeneous platforms (ongoing work) 29 J. Castrillon. Get-together for IoT, Apr. 2016

30 Multiple mapping configurations In case multiple applications may run on the system (or system of systems) Need different configurations Adapt to resource and energy budgets Reason about mapping euivalences =? 30 [Goens15] J. Castrillon. Get-together for IoT, Apr. 2016

31 Analysis for Multi-applications Use utilization profiles from the discrete event simulator (TRM) Quickly separate good from bad implementations [Castrill14] 31 J. Castrillon. Get-together for IoT, Apr. 2016

32 Code generation CPN application Mapping configuration Code generation Architecture model PNargs_ifft_r.ID = 6U; PNargs_ifft_r.PNchannel_fre_coef = filtered_coef_right; PNargs_ifft_r.PNnum_fre_coef = 0U; PNargs_ifft_r.PNchannel_time_coef = sink_right; PNargs_ifft_r.channel = 1; sink_left = IPCllmrf_open(3, 1, 1); sink_right = IPCllmrf_open(7, 1, 1); PNargs_sink.ID = 7U; PNargs_sink.PNchannel_in_left = sink_left; PNargs_sink.PNnum_in_left = 0U; PNargs_sink.PNchannel_in_right = sink_right; PNargs_sink.PNnum_in_right = 0U; taskparams.arg0 = (xdc_uarg)&pnargs_src; taskparams.priority = 1;... Debugging info [Castrill11b, Murillo14] Take mapping configuration and generate code accordingly From architecture model: APIs, configuration parameters, Sample targets: experimental heterogenous systems, TI (Keysonte, TDA3x), Parallela/Ephiphany, ARM-based (Exynos, Snapdragon) 32 J. Castrillon. Get-together for IoT, Apr. 2016

33 Examples Same application(s) automatically compiled to different platforms Virtual platforms: SystemC models of full systems Bare metal Multi-RISC/VLIW platform Real platform: TI Keystone platform Speedup on commercial platforms Code generation against vendor stacks 33 J. Castrillon. Get-together for IoT, Apr. 2016

34 Example: multi-media applications Iterative mapping 34 J. Castrillon. Get-together for IoT, Apr. 2016

35 Manual vs. Automatic: TI Keystone Image processing Audio filtering application [Aguilar14] LTE digital receiver 35 J. Castrillon. Get-together for IoT, Apr. 2016

36 Outline Introduction Models of computation Tool flows Outlook for IoT Summary 36 J. Castrillon. Get-together for IoT, Apr. 2016

37 So far MoC-based Application Non-functional specification Analysis Synthesis Code generation PNargs_ifft_r.ID = 6U; PNargs_ifft_r.PNchannel_fre_coef = filtered_coe PNargs_ifft_r.PNnum_fre_coef = 0U; PNargs_ifft_r.PNchannel_time_coef = sink_right; PNargs_ifft_r.channel = 1; sink_left = IPCllmrf_open(3, 1, 1); sink_right = IPCllmrf_open(7, 1, 1); PNargs_sink.ID = 7U; PNargs_sink.PNchannel_in_left = sink_left; PNargs_sink.PNnum_in_left = 0U; PNargs_sink.PNchannel_in_right = sink_right; PNargs_sink.PNnum_in_right = 0U; taskparams.arg0 = (xdc_uarg)&pnargs_src; taskparams.priority = 1; ti_sysbios_knl_task_create((ti_sysbios_knl_task_func &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_fft_l; taskparams.priority = 1; Architecture model MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA ti_sysbios_knl_task_create((ti_sysbios_knl_task_func ft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_ifft_r; taskparams.priority = 1; ti_sysbios_knl_task_create((ti_sysbios_knl_task_func fft_templ, &taskparams, &eb); glob_proc_cnt++; hasprocess = 1; taskparams.arg0 = (xdc_uarg)&pnargs_sink; taskparams.priority = 1; 37 J. Castrillon. Get-together for IoT, Apr. 2016

38 What s missing? Reactivity Supported for periodic events (trigger) Enough for many applications (automotive) 1 ms 3 ms 1 ms Sporadic (I/O) events may break determinism Better execution guarantees Multi-SoC Supported if inter-soc communication is predictable (same cost-function approach) Scalability: Add a layer of geographic coarse mapping MEM subsystem DMAs, semaphores PMU L2 VLIW DSP,L2 NoC Peripherals Communication support HW ueues Network Processor Packet DMA 38 J. Castrillon. Get-together for IoT, Apr. 2016

39 Outline Introduction Models of computation Tool flows Outlook for IoT Summary 40 J. Castrillon. Get-together for IoT, Apr. 2016

40 Summary IoT complexity: heterogeneity, resource constraints, distributed, The need for formal MoC for programming and synthesis Sample tool flow Heterogeneity: High-level architecture models Support dynamic applications: Analysis and synthesis based on traces Extensions for: multiple traces Outlook Adaptivity at runtime Reactivity and multi-soc case studies 41 J. Castrillon. Get-together for IoT, Apr. 2016

41 Acknowledgements Silexica Software Solutions GmbH German Cluster of Excellence: Center for Advancing Electronics Dresden ( 42 J. Castrillon. Get-together for IoT, Apr. 2016

42 References [Castrill14] J. Castrillon, et al., Programming Heterogeneous MPSoCs: Tool Flows to Close the Software Productivity Gap, Springer, 2014 [Castrill11a] J. Castrillon, et al., Trends in embedded software synthesis, International Conference on Embedded Computer Systems (SAMOS) pp , 2011 [Oden13] M. Odendahl, et al., Split-cost communication model for improved MPSoC application mapping, In International Symposium on System on Chip pp. 1-8, 2013 [Arnold13] O. Arnold, et al. Tomahawk - Parallelism and Heterogeneity in Communications Signal Processing MPSoCs. TECS, 2013 [Eusse14] J.F. Eusse,, et al., "Pre-architectural performance estimation for ASIP design based on abstract processor models," In SAMOS 2014 pp , 2014 [Castrill10] J. Castrillon,, et al., Component-based waveform development: The nucleus tool flow for efficient and portable SDR, Wireless Innovation Conference and Product Exposition (SDR), 2010 [Castrill10b] J. Castrillon, et al., Trace-based KPN composability analysis for mapping simultaneous applications to MPSoC platforms, In DATE 2010, pp [Castrill13] J. Castrillon, et al., MAPS: Mapping concurrent dataflow applications to heterogeneous MPSoCs, IEEE Transactions on Industrial Informatics, vol. 9, 2013 [Castrill12] J. Castrillon, et al., Communication-aware mapping of KPN applications onto heterogeneous MPSoCs, in DAC 2012 [Goens15] A. Goens, et al., Analysis of Process Traces for Mapping Dynamic KPN Applications to MPSoCs, In IFIP International Embedded Systems Symposium (IESS), 2015, Foz do Iguaçu, Brazil (Accepted for publication), 2015 [Castrill11b] J. Castrillon, et al., Backend for virtual platforms with hardware scheduler in the MAPS framework, In LASCAS 2011 pp. 1-4, 2011 [Murillo14] L. G. Murillo, et al., Automatic detection of concurrency bugs through event ordering constraints, In DATE 2014, pp. 1-6, 2014 [Aguilar14] M. Aguilar, et al., "Improving performance and productivity for software development on TI Multicore DSP platforms," in Education and Research Conference (EDERC), th European Embedded Design in, vol., no., pp.31-35, Sept J. Castrillon. Get-together for IoT, Apr. 2016