Embedded Systems. Information. TDDD93 Large-Scale Distributed Systems and Networks

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1 TDDD93 Fö Embedded Systems - TDDD93 Fö Embedded Systems - 2 Information TDDD93 Large-Scale Distributed Systems and Networks Lectures on Lecture notes: available from the course page, latest 24 hours before the lecture. Embedded Systems Recommended literature: Petru Eles Peter Marwedel: "Embedded System Design", Springer, 2nd edition, 20. Institutionen för Datavetenskap (IDA) Linköpings Universitet petel@ida.liu.se phone: B building, 329:220 Edward Lee, Sanjit Seshia: Introduction to Embedded Systems - A Cyber-Physical Systems Approach, LeeSeshia.org, st edition 20, 2nd edition 205. TDDD93 Fö Embedded Systems - 3 TDDD93 Fö Embedded Systems - 4 Embedded Systems and Their Design That s how we use microprocessors. What is an Embedded System 2. Characteristics of Embedded Applications 3. Modeling of Embedded systems 4. The Traditional Design Flow 5. An Example 6. A New Design Flow 7. System Level Design 8. Power/Energy Consumption - a Major Issue

2 TDDD93 Fö Embedded Systems - 5 TDDD93 Fö Embedded Systems - 6 What is an Embedded System? There are several definitions around! Some highlight what it is (not) used for: An embedded system is any sort of device which includes a programmable component but itself is not intended to be a general purpose computer. Some focus on what it is built from: An embedded system is a collection of programmable parts surrounded by ASICs and other standard components, that interact continuously with an environment through sensors and actuators. What is an Embedded System? (cont d) Some of the main characteristics: Dedicated (not general purpose) Contains a programmable component Interacts (continuously) with the environment TDDD93 Fö Embedded Systems - 7 TDDD93 Fö Embedded Systems - 8 A Look at Two Typical Implementation Architectures Telecommunication System on Chip Distributed Embedded System (automotive application) Actuators Sensors Input/Output RF A/D & D/A DSP core RAM RISC core RAM High-Speed DSP Blocks Control Logic Interface LAN RAM CPU FLASH Network Interface Programmable processor ASIC block (Application Specific Integrated Circuit) Standard block Memory Reconfigurable logic (FPGA) dedicated electronics Gateway Gateway

3 TDDD93 Fö Embedded Systems - 9 TDDD93 Fö Embedded Systems - 0 The Software Component Software running on the programmable processors: Application tasks Real-Time Operating System I/O drivers, Network protocols, Middleware Characteristics of Embedded Applications What makes them special? Like with ordinary applications, functionality and user interfaces are often very complex. But, in addition to this: Time constraints Power constraints Cost constraints Safety Time to market TDDD93 Fö Embedded Systems - TDDD93 Fö Embedded Systems - 2 Characteristics of Embedded Applications (cont d) Characteristics of Embedded Applications (cont d) Time constraints: Embedded systems have to perform in real-time: if data is not ready by a certain deadline, the system fails to perform correctly. - Hard deadline: failure to meet leads to major hazards. - Soft deadline: failure to meet can be tolerated but quality of service is reduced. Power constraints: There are several reasons why low power/energy consumption is required: Cost aspects: High power consumption strong power supply expensive cooling system Battery life High energy consumption short battery life time

4 TDDD93 Fö Embedded Systems - 3 TDDD93 Fö Embedded Systems - 4 Characteristics of Embedded Applications (cont d) Cost constraints: Embedded systems are very often mass products in highly competitive markets and have to be shipped at a low cost. What we are interested in: - Manufacturing cost - Design cost Factors: design time, type of components used (processor, memory, I/O devices), technology, testing time, power consumption, etc. Non-recurring engineering (NRE) costs (such as design cost, masks, prototypes) are becoming very high - It is very difficult to come out with low quantity products; - Hardware and software platforms are introduced which are used for several products in a family; Characteristics of Embedded Applications (cont d) Safety critical: Embedded systems are often used in life critical applications: avionics, automotive electronics, nuclear plants, medical applications, military applications, etc. Reliability and safety are major requirements. In order to guarantee safety during design: - Formal verification: mathematics-based methods to verify certain properties of the designed system. - Automatic synthesis: certain design steps are automatically performed by design tools. TDDD93 Fö Embedded Systems - 5 TDDD93 Fö Embedded Systems - 6 Characteristics of Embedded Applications (cont d) Short time to market: In highly competitive markets it is critical to catch the market window: a short delay with the product on the market can have catastrophic financial consequences (even if the quality of the product is excellent). Design time has to be reduced! - Good design methodologies. - Efficient design tools. - Reuse of previously designed and verified (hardware and software) blocks. - Good designers who understand both software and hardware! Why is Design of Embedded Systems Difficult? High Complexity Strong time and power constraints Low cost Short time to market Safety critical systems In order to achieve all these requirements, systems have to be highly optimized. Both hardware and software aspects have to be considered simultaneously!

5 TDDD93 Fö Embedded Systems - 7 TDDD93 Fö Embedded Systems - 8 Modelling Embedded Systems The design flow starts from an informal description of the desired functionality and constraints. Before the actual design is performed, a more formal abstract model, capturing the required behaviour, is produced. This model is an abstraction, hiding many details and only capturing the aspects that are most relevant for starting the actual design flow. There are several modeling approaches (and modeling languages) used for embedded system design; we give two examples in the following: Dataflow Models and Finite State Machines. Dataflow Models Systems are specified as directed graphs where: - nodes represent computations (processes); - arcs represent totally ordered sequences (streams) of data (tokens). Dataflow models are suitable for signal-processing algorithms: - Code/decode, filter, compression, streaming video, etc. There are several models based on Dataflow: Kahn Process Networks (KPN), Synchronous Dataflow Models (SDF), etc. TDDD93 Fö Embedded Systems - 9 TDDD93 Fö Embedded Systems - 20 Dataflow Models (cont d) Dataflow Models (cont d) KPN model of an encoder for the Motion JPEG (M-JPEG) video compression format: HeaderInfo P Block DCT Block Block Packets Q VLE QTables P2 HuffTables StatisticsB BitRate CtrlF StatisticsF TablesInfo EndOfFrame Video Out SDF model of a Modem: Biq 2 2 Fork Add sc Fork Conj 2 Biq 2 2 Mul In Filt Hil Eq Mul Deci Deco 2 2 Out

6 TDDD93 Fö Embedded Systems - 2 TDDD93 Fö Embedded Systems - 22 Finite State Machines Finite State Machines (cont d) The system is characterised by explicitly depicting its states as well as the transitions from one state to another. One particular state is specified as the initial one States and transitions are in a finite number. Transitions are triggered by input events. Transitions generate outputs. FSMs are suitable for modeling control dominated reactive systems (react on inputs with specific outputs; not much computation) Elevator controller Input events {r, r 2, r 3 } - r i : request from floor i. Outputs {d 2, d, n, u, u 2 } - d i : go down i floors - u i : go up i floors - n: stay idle States {S, S 2, S 3 } - S i : elevator is at floor i. r /n S initial state input event r /d 2 r 3 /u 2 r 2 /u r /d S 3 output r 3 /n r 2 /d r 3 /u S 2 r 2 /n (In the model we have assumed that there are no two requests coming simultaneously) TDDD93 Fö Embedded Systems - 24 The Traditional Design Flow It works like this (or even worse): TDDD93 Fö Embedded Systems Start from some informal specification of functionality and a set of constraints (time and power constraints, cost limits, etc.) T T 2 T 3 T 5 T 6 T 4 T 7 T 8 A Design Example The system to be implemented is modelled as a synchronous dataflow model (a task graph): a node represents a task (a unit of functionality activated as response to a certain input and which generates a certain output). an edge represents a precedence constraint and data dependency between two tasks. Period: 42 time units The task graph is activated every 42 time units one activation has to be terminated in time less than 42. Cost limit: 8 The total cost of the implemented system has to be less than Generate a more formal model of the functionality, based on some modeling concept (finite state machine, data-flow, etc.). This model is in Matlab, Statecharts, C, UML, VHDL. Such a model is our task graph (slide 23). 3. Simulate the model in order to check the functionality. If needed make adjustments. 4. Choose an architecture (μprocessor, buses, etc.) such that the cost limits are satisfied and, you hope, that time and power constraints will be fulfilled. 5. Build a prototype and implement the system. 6. Verify the system: neither time nor power constraints are satisfied!!! Now you are in great trouble: you have spent a lot of time and money and nothing works! Go back to 4 and choose another architecture and start a new implementation. Or negotiate with the customer on the constraints.

7 TDDD93 Fö Embedded Systems - 25 The Traditional Design Flow (cont d) Informal Specification, Constraints TDDD93 Fö Embedded Systems - 26 Modeling System Model Select Architecture Functional Simulation More work should be done here! What are the consequences: The Traditional Design Flow (cont d) Delays in the design process - Increased design cost - Delays in time to market missed market window High cost of failed prototypes not OK Hardware and Software Implementation Bad design decisions taken under time pressure - Low quality, high cost products Testing Prototype OK Fabrication TDDD93 Fö Embedded Systems - 27 TDDD93 Fö Embedded Systems - 28 Example Let s come back to the example on slide 23. We have the system model (task graph) which has been validated by simulation. What next? We decide on a certain μprocessor μp, with cost 4. For each task the worst case execution time (WCET) when executed on μp is estimated. Task WCET T 4 T 2 6 T 3 4 T 4 7 T 5 8 T 6 2 T 7 7 T 8 0 task Estimator WCET μprocessor arch. model

8 TDDD93 Fö Embedded Systems - 29 TDDD93 Fö Embedded Systems - 30 A schedule: Time T T 2 T 4 T 3 T 5 T 6 T 7 T 8 We look after a μprocessor which is fast enough: μp2 For each task the WCET, when executed on μp2, is estimated. Using this architecture we got a solution with: Execution time: 58 > 42 Cost: 4 < 8 We have to try with another architecture! Using this architecture we got a solution with: Execution time: 28 < 42 Cost: 5 > 8 We have to try with another architecture! Task WCET T 2 T 2 3 T 3 2 T 4 3 T 5 4 T 6 6 T 7 3 T 8 5 TDDD93 Fö Embedded Systems - 3 TDDD93 Fö Embedded Systems - 32 Now we have to look to a multiprocessor solution. In order to meet cost constraints we try two cheap (and slow) μps: μp3: cost 3 : cost 2 interconnection bus: cost Task WCET μp3 For each task the WCET, when executed T 5 6 on μp3 and, is estimated. T T T μp3 T 5 0 T Bus T T Now we have to map the tasks to processors. μp3: T, T 3, T 5, T 6, T 7, T 8. : T 2, T 4. If communicating tasks are mapped to different processors, they have to communicate over the bus. Communication time has to be estimated; it depends on the amount of bits transferred between the tasks and on the speed of the bus. Estimated communication times: C -2 : C 4-8 :

9 TDDD93 Fö Embedded Systems - 33 TDDD93 Fö Embedded Systems - 34 A schedule: Time μp3 T T 3 T 5 T 6 T 7 T 8 bus T 2 T 4 C -2 C 4-8 We have exceeded the allowed execution time (42)! Try a new mapping; move T 5 to, in order to increase parallelism. Two new communications are introduced, with estimated times: C 3-5 : 2 C 5-7 : A schedule: Time μp3 bus T T 3 T 6 T 7 T 8 T 2 T 4 T 5 C -2 C 3-5 C 4-8 C 5-7 The execution time is still 62, as before! TDDD93 Fö Embedded Systems - 35 TDDD93 Fö Embedded Systems - 36 There exists a better schedule! Time μp3 T T 3 T 6 T 7 T 8 bus T 2 T 5 T 4 C -2 C 3-5 C 5-7 C 4-8 Using this architecture we got a solution with: Execution time: 52 > 42 Cost: 6 < 8 Possible solutions: Change μprocessor μp3 with a faster one cost limits exceeded Implement some part of the functionality in hardware as an ASIC New architecture Cost of ASIC: μp3 Mapping ASIC μp3: T, T 3, T 6, T 7. : T 2, T 4, T 5. ASIC: T 8 with estimated WCET= 3 New communication, with estimated time: C 7-8 : Bus

10 TDDD93 Fö Embedded Systems - 37 TDDD93 Fö Embedded Systems - 38 A schedule: Time μp3 T T 3 T 6 T 7 T 2 T 5 T 4 ASIC bus C -2 C 3-5 C 5-7 C 4-8 C 7-8 Using this architecture we got a solution with: Execution time: 4 < 42 Cost: 7 < 8 T 8 What did we achieve? We have selected an architecture. We have mapped tasks to the processors and ASIC. We have elaborated a a schedule. Extremely important!!! Nothing has been built yet. All decisions are based on simulation and estimation. Now we can go and do the software and hardware implementation, with a high degree of confidence that we get a correct prototype. TDDD93 Fö Embedded Systems - 39 The Design Flow Informal Specification, Constraints Modeling TDDD93 Fö Embedded Systems - 40 Arch. Selection System model Functional Simulation The Design Flow (cont d) What is the essential difference compared to the flow on slide 25? System architecture Estimation Mapping Scheduling It is the inner loop which is performed before the effective hardware/software implementation. This loop is performed several times as part of the design space exploration. Different architectures, mappings and schedules are explored, before the actual implementation and prototyping. not OK Mapped and scheduled model OK not OK We get highly optimized good quality solutions in short time. We have a good chance that the outer loop, including prototyping, is not repeated. Hardware and Software Implementation not OK Testing OK Fabrication Prototype

11 TDDD93 Fö Embedded Systems - 42 The Design Flow (cont d) Informal Specification, Constraints TDDD93 Fö Embedded Systems - 4 The Design Flow (cont d) Some additional remarks: Formal verification It is impossible to do an exhaustive verification by simulation! Especially for safety critical systems (but not only) formal verification is needed. Simulation Simulation is used not only for functional validation. It is used also after mapping and scheduling in order to test, for example, timing aspects. It is used also during the implementation steps; especially interesting: hardware/software cosimulation. System Level Arch. Selection System architecture Estimation Modeling System model Mapping Scheduling Functional Simulation Formal Verification not OK Mapped and scheduled model not OK Simulation OK Formal Verification The steps performed before the actual hardware and software implementation represent the System Level Design Phase! Softw. model Simulation Hardw. model Softw. Generation Hardw. Synthesis Lower Levels Softw. blocks not OK Testing OK Fabrication Simulation Prototype Hardw. blocks TDDD93 Fö Embedded Systems - 43 TDDD93 Fö Embedded Systems - 44 The Lower Levels The Lower Levels (cont d) Software generation: - Encoding in an implementation language (C, C++, assembler). - Compiling (this can include particular optimizations for application specific processors, DSPs, etc.). - Generation of a real-time kernel or adapting to an existing operating system. - Testing and debugging (in the development environment). Several courses are teaching this part: Programming related courses, Algorithms and data structures, Compilers, operating systems, real-time systems,... Hardware synthesis: - Encoding in a hardware description language (VHDL, Verilog) - Successive synthesis steps: high-level, register-transfer level, logic-level synthesis. - Testing and debugging (by simulation) Several courses are teaching this part: Digital design, Electronics and VLSI related courses, Computer Architectures,...

12 TDDD93 Fö Embedded Systems - 45 TDDD93 Fö Embedded Systems - 46 The System Level Bring Power Consumption into the Picture Why is power consumption an issue? TDTS07: System Design and Methodology (Modeling and Design of Embedded Systems) Portable systems - battery life time! Systems with a very limited power budget: Mars Pathfinder, autonomous helicopter,... Desktops and servers: high power consumption - raises temperature and deteriorates performance & reliability - increases the need for expensive cooling mechanisms One of the main difficulties with developing high performance chips is heat extraction. High power consumption has economical and ecological consequences. TDDD93 Fö Embedded Systems - 47 TDDD93 Fö Embedded Systems - 48 Sources of Power Dissipation in CMOS Devices dynamic static 2 P = -- C V 2 DD f N SW + Q SC V DD f N SW + I leak V DD Switching power Power required to charge/discharge circuit nodes Short-circ. power Dissipation due to short-circuit current Leakage power Dissipation due to leakage current Dynamic Power/Energy 2 P = -- C V 2 DD f N SW 2 E = P t = -- C V 2 DD N CY N SW N CY = number of cycles needed for the particular task. C = node capacitances N SW = switching activities (number of gate transitions per clock cycle) f = frequency of operation V DD = supply voltage Q SC = charge carried by short circuit current per transition I leak = leakage current In certain situations we are concerned about power consumption: - heath dissipation, cooling: - physical deterioration due to temperature. Sometimes we want to reduce total energy consumed: - battery life.

13 TDDD93 Fö Embedded Systems - 49 TDDD93 Fö Embedded Systems - 50 Reducing Power/Energy Consumption Reducing Power/Energy Consumption (cont d) The main sources: Reduce supply voltage (Voltage scaling) Reduce switching activity (Smart digital design) Reduce capacitance (Smart circuit design) Reduce number of cycles (Smart algorithms design) System Level Compilation for low power: instruction selection considering their power profile, data placement in memory, register allocation. Algorithm design: find the algorithm which is the most powerefficient. Task mapping and scheduling. Dynamic voltage/frequency scaling applied at run-time in order to reduce power consumption by exploiting idle or low-workload periods. TDDD93 Fö Embedded Systems - 5 TDDD93 Fö Embedded Systems - 52 Example: Mapping for Low Energy Mapping for Low Energy (cont d) τ τ 2 τ 3 τ 5 τ 4 τ 7 τ 8 μp3 τ 6 WCET Energy Task μp3 μp3 τ τ τ τ τ τ τ τ Consider a mapping: Communication times and energy: μp3: τ, τ 3, τ 6, τ 7, τ 8. C -2 : t = ; E = 3. C 3-5 : t = 2; E = 5. : τ 2, τ 4, τ 5. C 4-8 : t = ; E = 3. C 5-7 : t = ; E = 3. Execution time: 52; Energy consumed: 75. Time μp3 τ τ 3 τ 6 τ 7 τ 8 bus τ 2 τ 5 τ4 Bus C -2 C 3-5 C 5-7 C 4-8

14 TDDD93 Fö Embedded Systems - 53 TDDD93 Fö Embedded Systems - 54 Mapping for Low Energy (cont d) Mapping for Low Energy (cont d) Consider a mapping: Communication times and energy: μp3: τ, τ 3, τ 6, τ 7. C -2 : t = ; E = 3. C 3-5 : t = 2; E = 5. : τ 2, τ 4, τ 5, τ 8. C 7-8 : t = ; E = 3. C 5-7 : t = ; E = 3. Execution time: 57; Energy consumed: 70. The second mapping with τ 8 on consumes less energy; Assume that we have a maximum allowed delay = 60. τ 6 τ 7 Time μp3 τ τ 3 bus τ 2 τ 5 τ4 τ8 C -2 C 3-5 C 5-7 C 7-8 This second mapping is preferable, even if it is slower! TDDD93 Fö Embedded Systems - 55 TDDD93 Fö Embedded Systems - 56 Dynamic Power Management At run-time, the processor can be placed in different power states, depending on the current work-load. Switching among multiple power states: idle sleep run When in the run state: switching among multiple voltage levels. Energy consumption is proportional to V 2 (see slide 48)!!! Dynamic Power management (cont d) Hardware Support (e.g. Intel Xscale Processor) RUN: operational IDLE: Clocks to the CPU are disabled; recovery is through interrupt. SLEEP: Mainly powered off; recovery through wake-up event. Other intermediate states: DEEP IDLE, STANDBY, DEEP SLEEP 0.75V, 60mW 50MHz RUN.3V, 450mW RUNRUN 600MHz.6V, 900mW RUN 60μs RUN 800MHz 0μs IDLE 40mW 0μs 40ms 90μs.5ms SLEEP 60μW

15 TDDD93 Fö Embedded Systems - 57 TDDD93 Fö Embedded Systems - 58 Dynamic Power management (cont d) Switching between power states and voltage levels is not for free: you have to consider the switching overheads (in terms of delay and energy) For a given supply voltage there exists a maximal frequency at which the processor can run when you reduce the voltage the processor becomes slower! The goal of Dynamic Power management: switch between power states and voltage levels such that: Energy consumption is minimised QoS is not compromised Conclusions Embedded systems are everywhere. They have to satisfy strong timing, safety, power, and cost constraints. An efficient design flow, with iterations at the system level, is needed in order to support the design of complex embedded systems. System level design steps are performed before the start of the actual implementation of hardware and software components! The input to the actual design flow is an abstract model of the system. Power consumption becomes a central issue of the design process.