Fault-tolerant system design using novel majority voters of 5-modular redundancy configuration

Transcription

1 Fault-tolerant system design using novel majority voters of 5-modular redundancy configuration V.Elamaran, G.Rajkumar, N.Raju, K.Narasimhan, Har Narayan Upadhyay School of EEE, Department of ECE, SASTRA University, Thanjavur, Tamilnadu, India Abstract. Introduction: The highly reliable systems are often used in most critical applications like Bank transactions, Defense communications, Aerospace applications, etc. The loss will be enormous if these systems fail in the field, i.e., during the operating time. The circuit designers keep researching to build intelligent systems with reliability improvement by adding redundancy like hardware, software, information and time. In this study, the hardware redundancy is used to improve the reliability of the system. Methodology: The Triple Modular Redundancy (TMR) which can tolerate one error is the most common technique used to mitigate errors in the field of microelectronics reliability. This study primarily focuses on new majority voters of a 5- MR system which can tolerate two errors for the betterment of reliability. The optimization of the majority function of a 5-MR system is the key to the proposed ideas. Results & Conclusion: Simulation results show that the first proposed majority voter offers a lower delay as ns as compared to ns by existing majority voter and less layout area as µm 2. The secondly proposed majority voter dissipates less power as µw as compared to µw by the existing majority vote. It is also shown that the proposed majority voters offer a better figure-of-merit as compared to the current majority voting architecture by implementing them with the industry standard benchmark circuits. Keywords: Fault-tolerant, reliability, TMR, low power, high speed, voting. 1 Introduction In the current semiconductor technology evolution, the reliability of the microelectronic circuits is much more critical. The significance of fault-tolerant digital systems is its growth drastically in the field of VLSI design. Most of the applications like mission-critical demand accurate results nowadays. For example, Military systems and Banking systems should require better reliability since they should not halt their services while in the field [1]. So the reliability is an another most important specification for any system design. The circuit designers research in improving the reliability of a system even at the cost of the area and power. The redundant hardware logic is often used in the systems to avoid failure and to operate them continuously [2,3]. Since the redundancy method is incorporated to enhance the reliability, the circuit area and the power dissipation are the overhead issues for the designers. So it is essential to study the different kinds of faults likely occur to microelectronic circuits. These defects can appear due to design flaws, malfunction of the components, glitches, single event upset, single event transient, and manual operating error [4]. The redundant hardware logic is often used in systems to avoid failure and to operate them continuously. There are two kinds of redundancy which are Space redundancy and Time redundancy [2]. In space redundancy method, the components, subsystems, systems, functions, and data items are added additionally to obtain the fault-free output. Here, hardware components, software applications, and the information data are redundant and namely as Hardware, Software, and information redundancy respectively. In time redundancy, 318

2 the data transmission or the result computation is repeated until to reach the fault-free output. So the intelligent fault tolerant systems are obtained by adding merely appropriate redundancy. Since the information available in the mission-critical applications are highly valuable, the cost of failure system is too high. Apart from those applications, also the current System-on-Chip (SoC) based circuits have to be designed carefully with a fault-tolerant mechanism through nanometer technologies. So the reliability is now given top priority of speed, power, and an area in the current semiconductor chip design field. The reliability can mainly be improved either by fault-prevention technique or fault-tolerant method. In faultprevention or fault-intolerance method, the prior removal of faults is vital to obtain a correct output which becomes much difficult in practice [5]. The fault-diagnosis is another issue to be considered in this approach. In most of the real-time system, this method approach is difficult to adopt for the improvement of reliability. In TMR method, apart from an original module, two more similar modules are placed. If one module fails to work, the voter circuit will compute the majority as a fault-free output. Since one error from a faulty module is masked by the other two working modules, this fault becomes redundant. So the testing of the TMR configuration is not possible during the off-line process. To achieve the testing, the redundancy can be removed in the off-line process [7]. The system failure can happen due to the presence of a fault within it. The faults are occurred due to various reasons and classified depending upon the origin or the duration [8]. The faults which are occurred and remain stable till the detection and correction are undertaken are known as permanent faults [4, 9]. The faults which are appeared for a small duration due to the high energy particles radiation effects are known as transient faults [10]. These faults can change the actual state of the system even though it occurs only for a shorter period. A few faults are often occurred and may become permanent are known as intermittent faults [11]. Since the faults are expected to appear during the system operation, the effect of the fault should be nullified by incorporating the redundancy that is, adding additional resources to the system. This method is known as fault-tolerance approach. In real time circuits, there are many methods to improve the reliability of the system but at the cost of overheads such as area, power dissipation, and critical path delay. These overheads are mainly due to adding redundancy either by hardware, software, time, or information [12]. The most often used method to improve the reliability is by adding redundancy. In hardware redundancy, the actual hardware modules are duplicated so that if the faults occur, they are masked by other available modules. Similarly, the redundant information is added to the information redundancy approach through which the error detection and correction is applied to obtain the correct output. If the additional software is included, it is known as software redundancy. In the case of time redundancy, it consumes time so that if an error occurs, the receiver may ask the sender to retransmit it again [13]. So, the designer s responsibility is to choose the excellent one through which the overheads are minimized to some extent. The reliability of the system fails mainly due to the faults which occur due to the physical defects of components, circuit design errors, single event upsets from radiation effects or human errors during the operation of the system [14]. 2 Related Works In general, TMR architecture is capable of masking one module fault or failure out of 3 modules [15], i.e., it can tolerate one error. To cope with multiple errors, N-Modular Redundancy (NMR) architectures can be implemented [16]. If N = 5, this will become 5-MR, in which the architecture is capable of tolerating two errors out of five function modules using the majority voter circuit. This 5-MR should contain at least three 319

3 correctly operating modules to mask two failures [17]. In this section, we analyze the principle of the existing majority voter of a 5-MR configuration in detail. 2.1 The existing 5-MR system In NMR architecture, the N-1 duplicate copies of an actual module are placed, i.e., the hardware redundancy approach is implemented. Figure 1 depicts the actual majority voter of a 5-MR architecture to tolerate two errors [6]. If the inputs D and E are equal to logic 0, the majority function V is determined as ABC. If the inputs D and E are equal to logic 1, then the output will become A+B+C. If D and E are not equal, i.e., either D = 0 & E = 1, or D = 1 & E = 0, the output V will be evaluated as AB+BC+CA, which will be similar to the traditional TMR functionality. Figure. 1. The existing majority voter. 2.2 Motivation to construct novel 5MR systems The limitations of this existing majority voter of a 5-MR system have more number of transistors hence consume more power dissipation and have a significant amount of critical path delay. In current semiconductor technology evolution, there is a vast need to optimize the area, power, and delay. In the field of VLSI deign, the designers should understand the trade-off involved in the design or architecture. That is, if one design may dissipate less power at the cost of performance; another design would occupy more layout area at the expense of power. So, the circuit design engineers should find the optimal solution for the typical applications which need low power, less area, and high performance. The TMR portion available in the existing majority voter of a 5-MR system can be modified to a more efficient one with less number of transistors. There is also a possibility to replace a 4-to-1 multiplexer to a 2- to-1 multiplexer with suitable additional logic without violating the logic principle. This majority function (TMR) in the existing architecture can be replaced by the voter using NAND gates or NOR gates. Since this output is one similar to the carry out of full adder, this module can also be replaced with a carry out segment of a carry look-ahead adder which is a fast adder. This voter can be designed using multiplexers or using the combinations of the multiplexer and a XOR gate, i.e., if the inputs A and B are not equal, the majority function will be the input C. If the inputs A and B are equal, then the voter output will be either A or B. 320

4 3 The Proposed 5-MR Configurations In this section, we propose three majority voters of 5-MR architecture for the betterment of reliability in the field of microelectronic circuits. Finally, all these architectures are tested with a few industry standard benchmark circuits to compare the area, power, and performance results. 3.1 The first proposed 5-MR system The idea behind the first proposed majority voter of 5-MR architecture is to replace the 4-to-1 multiplexer with 2-to-1 multiplexers. Figure 2 shows the modified majority voter of a 5-MR architecture in which the TMR portion is placed to find the majority of the three inputs A, B, and C. i) If the inputs D and E are not equal, then the output V will be the majority function of the inputs A, B, and C. ii) If D = E & DE = 0, then the output V is evaluated as ABC. iii) If D = E & DE = 1, then the output V is expressed as A+B+C. Figure. 2. The first proposed majority voter. 3.2 The second proposed 5-MR system The motivation behind the secondly proposed majority voter of 5-MR architecture is discussed here, and the primary schematic is depicted in Figure 3. This structure contains two TMR configurations and one 2-to-1 multiplexer. This working scenario is explained as follows: i) The first TMR output is evaluated as V1 for the inputs A, B, and C. ii) The second TMR output is assessed as V2 for the inputs D, E, and V1. iii) The select signal for the 2-to-1 multiplexer is obtained as A = B = C. iv) If A = B = C, then the overall output V becomes the C, else the output V becomes V2. This idea is implemented and the second proposed 5-MR architecture is shown in Figure

5 Figure. 3. The schematic conceptual view for the secondly proposed majority voter. Figure. 4. The secondly proposed majority voter. 3.3 The third proposed 5-MR system The flowchart for the third proposed majority voter of 5-MR architecture is shown in Figure 5. This architecture would become easy to design the appropriate schematic as shown in Figure 6. The Yes and No available terms in the flowchart are readily implemented using 2-to-1 multiplexers. Figure. 5. A flow chart view of the third proposed majority voter. 322

6 Figure. 6. The third proposed majority voter. 4 Simulation Results and Discussion In this section, we discuss in detail the performances of all the proposed majority voter of 5-MR architectures with the existing one using the DSCH and Microwind Electronic Computer Aided Design (ECAD) software tools [18]. The DSCH tool is a schematic editor whereas a Microwind is a layout editor tool. 4.1 Area, power, and delay The comparison of area, power, and delay simulation results is made to find the optimal majority voter of 5- MR architectural design. Figure 7 shows the power consumption results which are determined using a Microwind layout editor tool for the 120 nm, 90 nm, 70 nm, and 50 nm process technologies. The power dissipation results for the existing, first, second and third majority voters of a 5-MR system with 120 nm process technology are µw, µw, µw, and µw respectively. The first and second proposed majority voters of 5-MR system obtain much low power dissipation as compared with the existing one. Similarly, the results of the layout are obtained as in Figure 8 for all the majority voting architectures. The layout area results for the current, first proposed, second proposed, and third proposed majority voters with 120 nm process technology are µm 2, µm 2, µm 2, and µm 2 respectively. The first proposed majority voter circuit occupies a less layout area as compared to the existing one. The number of transistors present in each majority voting 5-MR architecture is shown in Figure 9. The number of transistors for the existing, first proposed, second proposed and third proposed majority voters are 60, 66, 59, and 52 respectively. The second and third proposed majority voter circuits have less number of transistors as compared to the existing one. 323

7 Figure. 7. Power dissipation results. Figure. 8. Layout area results. Figure. 9. The number of transistors involved in all the 5-MR architectures. 324

8 4.2 Figure-of-merit results The sole objective of the VLSI design is to reduce power and area with high performance. But in real time, some circuits may produce better power dissipation results at the cost of the layout area. In some other case, circuits may offer a high performance or less delay at the expense of the layout area. So, an appropriate metric is needed to find an optimal architecture with the above-mentioned trade-offs. The figure-of-merit (FOM) metric is calculated as the reciprocal of the product of power, delay, and area to identify an optimal architecture. The industry standard benchmark circuits like ISCAS 85 combinational circuit (C17) and an ISCAS 89 sequential circuit (S27) are used to obtain the FOM results. The C17 and S27 circuits are shown in Figure 10 and 11 respectively. The FOM results for the existing and proposed majority voting circuits are obtained in the Table1; the FOM results with C17 and S27 benchmark circuits are obtained in Table 2 and Table 3 respectively. Since the designers look for the architecture which should provide a lower power consumption, less layout area, and lower delay, the reciprocal of a product of all the three (FOM) should be higher value. So, the circuit which offers a very high FOM is being considered as a good design compared to others. The critical path delay, power dissipation, and layout area values are determined with 120 nm technology process, which is used to calculate the FOM value. The test input vectors are applied at regular intervals of 10 ns (100 MHz) for the simulation with Microwind layout editor tool. The first proposed majority voter of 5-MR architecture provides the highest FOM as 52.55; the second best is the second recommended one with a FOM value of 48. The first proposed majority voter obtains less critical path delay as ns, low layout area as µm 2, and hence provide the highest FOM as with a C17 benchmark circuit. The secondly proposed majority voter obtains lower power consumption results compared to the remaining architectures with a value of µw. The first proposed majority voter obtains the highest FOM as for the S27 benchmark circuit. The number of logic gates involved in each design and the corresponding failure rate are obtained in Table 4. The failure rate of the system can be determined using approximately the square root of the total gates in the schematic. The first and second proposed majority voters contain only 16 logic gates, and hence the failure rates become 4, which is less compared to the existing one. Figure. 10. ISCAS s benchmark combinational circuit (C17). 325

9 Figure. 11. ISCAS 89 benchmark sequential circuit (S27). Table 1. Figure-of-merit results of majority voters of 5-MR Design Power Delay Area PDA FOM 10 5 (µw) (ns) (µm 2 ) Existing majority voter Proposed Proposed Proposed Table 2. Figure-of-merit results with C17 benchmark circuit Design Power Delay Area PDA FOM 10 6 (µw) (ns) (µm 2 ) Existing majority voter Proposed Proposed Proposed Table 3. Figure-of-merit results with S27 benchmark circuit Design Power (µw) Delay (ns) Area (µm 2 ) PDA FOM

10 Existing majority voter Proposed Proposed Proposed Table 4. Number of logic gates used in 5-MR architectures and their failure rate Design INV AND2 OR2 AND3 OR3 XOR2 Total (g) Failure rate ( g ) Existing majority voter Proposed Proposed Proposed Conclusion To sum up, the demand to design an intelligent fault-tolerant system grows enormously in the field of microelectronics due to the occurrence of soft errors in satellite equipment by radiation with cosmic rays and high energy particles in the space. The hardware redundancy is the most popular mitigation technique in the field of fault-tolerant intelligent system design. The TMR configurations are well-known methods to produce the fault-free response using the hardware redundancy approach with a capability of tolerating one error. We have demonstrated mainly with intelligent 5MR systems which can tolerate up to two errors. Three proposed intelligent majority voters of a 5-MR system are introduced, and the results are compared with the existing one. The figure-of-merit results help us to find the optimum voter among other architectures. The proposed voting architectures provide a detailed result analysis report with designs which have low power, low delay, and occupy less layout area. This study becomes handy for the designers to choose the best one according to their requirements. This study also obtains the failure rate of each architecture with the help of the number of logic gates involved in the design. Finally, this study conveys the first proposed majority voter circuit is the most excellent one and the secondly proposed majority voter is the second best design by considering all the performance metrics. References [1]. P.K. Lala, Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers, San Francisco, [2]. D. Elena, Fault-Tolerant Design. Springer Publishers, New York, [3]. V. Elamaran, and Har Narayan Upadhyay, CMOS VLSI design of low power SRAM cell architectures with new TMR: A layout approach, Asian Journal of Scientific Research 2015; 8(4):

11 [4]. R.V. Kshirsagar, and R.M. Patrikar, Design of a novel fault-tolerant voter circuit for TMR implementation to improve reliability in digital circuits, Microelectronics Reliability 2009; 49(12): [5]. F. Smith, A new methodology for single event transient suppression in flash FPGAs, Microprocessors and Microsystems 2013; 37(3): [6]. P. Balasubramanian, D.L. Maskell, A distributed minority and majority voting based redundancy scheme, Microelectronics Reliability 2015; 55(9-10): [7]. S. Xiaoxuan, and K.S. McElvain, Time Multiplexed Triple Modular Redundancy for Single Event Upset Mitigation, IEEE Transactions on Nuclear Science 2009; 56(4): [8]. R. Pradhisa, N. Iswarya, K.L.V. Gopinath Reddy, Har Narayan Upadhyay, and V. Elamaran, FPGA Implementation of Self-testing Logic gates, Adders, and Multipliers, Indian Journal of Science and Technology 2015; 8(22): 1-6. [9]. S. Almukhaizim, and O. Sinanoglu, Novel hazard-free majority voter for N-modular redundancy-based fault tolerance in asynchronous circuits, IET Computers & Digital Techniques 2011; 5(4): [10]. AK. Nieuwland, and RP. Kleihorst, IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors, Journal of Electronic Testing: Theory and Applications 2004; 20(5): [11]. T. Ban, and L. Naviner, A Simple Fault-tolerant Digital Voter Circuit in TMR Nanoarchitectures, In Proc. 8 th IEEE International NEWCAS Conference (2010), [12]. CG. Santos, EC. Marques, L. Naviner, and JF. Naviner, Using error tolerance of target application for efficient for efficient reliability improvement of digital circuits, Microelectronics Reliability 2010; 50(9-11): [13]. S. Mitra, M. Zhang, N. Seifert, TM. Mak, and KS. Kim, Soft Error Resilient System Design through Error Correction, In Proc. of the International Conference Federation for Information Processing (IFIP) on Very Large Scale Integration (2006), [14]. V. Ferlet-Cavrois, LW. Massengill, and P.Gouker, Single Event Transients in Digital CMOS A Review, IEEE Transactions on Nuclear Science (2013); 60(3): [15]. HM. Chou, MY. Hsiao, YC. Chen, KH Yang, and J.Tsao, Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2015; 23(9): [16]. IA. Danilov, MS. Gorbunov, and AA. Antonov, SET Tolerance of 65 nm CMOS Majority Voters: A Comparative Study, IEEE Transactions on Nuclear Science 2014; 61(4): [17]. X. Liu, Y.Han, and B.Zhang, An SET hardened dual modular majority voter circuit for TMR system, IEICE Electronics Express 2014; 11(4): 1-6. [18]. S. Hari Hara Subramani, K.S.S.K. Rajesh, and V. Elamaran, Low energy, low power adder logic cells: A CMOS VLSI implementation, Asian Journal of Scientific Research 2014; 7(2):