Heterogeneous Multicore Processor Technologies for Embedded Systems

Transcription

1 Heterogeneous Multicore Processor Technologies for Embedded Systems

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3 Kunio Uchiyama Fumio Arakawa Hironori Kasahara Tohru Nojiri Hideyuki Noda Yasuhiro Tawara Akio Idehara Kenichi Iwata Hiroaki Shikano Heterogeneous Multicore Processor Technologies for Embedded Systems

4 Kunio Uchiyama Research and Development Group Hitachi, Ltd Marunouchi, Chiyoda-ku Tokyo , Japan Hironori Kasahara Green Computing Systems Waseda University R&D Center 27 Waseda-machi, Shinjuku-ku Tokyo , Japan Hideyuki Noda Renesas Electronics Corp Mizuhara, Itami-shi Hyogo , Japan Akio Idehara Nagoya Works, Mitsubishi Electric Corp Yada-minami 5-chome Higashi-ku Nagoya , Japan Fumio Arakawa Renesas Electronics Corp Josuihon-cho, Kodaira-shi Tokyo , Japan Tohru Nojiri Central Research Lab. Hitachi, Ltd Higashi-koigakubo Kokubunji-shi Tokyo , Japan Yasuhiro Tawara Renesas Electronics Corp Josuihon-cho, Kodaira-shi Tokyo , Japan Kenichi Iwata Renesas Electronics Corp Josuihoncho, Kodaira Tokyo , Japan Hiroaki Shikano Central Research Lab. Hitachi, Ltd Higashi-koigakubo Kokubunji-shi Tokyo , Japan ISBN ISBN (ebook) DOI / Springer New York Heidelberg Dordrecht London Library of Congress Control Number: Springer Science+Business Media New York 2012 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (

5 Preface The expression Digital Convergence was coined in the mid-1990s and became a topic of discussion. Now, in the twenty- fi rst century, the Digital Convergence era of various embedded systems has begun. This trend is especially noticeable in digital consumer products such as cellular phones, digital cameras, digital players, car navigation systems, and digital TVs. That is, various kinds of digital applications are now converged and executed on a single device. For example, several video standards such as MPEG-2, MPEG-4, H.264, and VC-1 exist, and digital players need to encode and decode these multiple formats. There are even more standards for audio, and newer ones are continually being proposed. In addition, recognition and synthesis technologies have recently been added. The latest digital TVs and DVD recorders can even extract goal-scoring scenes from soccer matches using audio and image recognition technologies. Therefore, a System-on-a-Chip (SoC) embedded in the digital-convergence system needs to execute countless tasks such as media, recognition, information, and communication processing. Digital convergence requires, and will continue to require, higher performance in various kinds of applications such as media and recognition processing. The problem is that any improvements in the operating frequency of current embedded CPUs, DSPs, or media processors will not be suf fi cient in the future because of power consumption limits. We cannot expect a single processor with an acceptable level of power consumption to run applications at high performance. One solution that achieves high performance at low-power consumption is to develop special hardware accelerators for limited applications such as the processing of standardized formats such as MPEG videos. However, the hardware-accelerator approach is not ef fi cient enough for processing many of the standardized formats. Furthermore, we need to fi nd a more fl exible solution for processing newly developed algorithms such as those for media recognition. To satisfy the higher requirements of digitally converged embedded systems, this book proposes heterogeneous multicore technology that uses various kinds of lowpower embedded processor cores on a single chip. With this technology, heterogeneous parallelism can be implemented on an SoC, and we can then achieve greater v

6 vi Preface fl exibility and superior performance per watt. This book de fi nes the heterogeneous multicore architecture and explains in detail several embedded processor cores including CPU cores and special-purpose processor cores that achieve highly arithmetic-level parallelism. We developed three multicore chips (called RP-1, RP-2, and RP-X) according to the de fi ned architecture with the introduced processor cores. The chip implementations, software environments, and applications running on the chips are also explained in the book. We, the authors, hope that this book is helpful to all readers who are interested in embedded-type multicore chips and the advanced embedded systems that use these chips. Kokubunji, Japan Kunio Uchiyama

7 Acknowledgments A book like this cannot be written without the help in one way or another of many people and organizations. First, part of the research and development on the heterogeneous multicore processor technologies introduced in this book was supported by three NEDO (New Energy and Industrial Technology Development Organization) projects: Advanced heterogeneous multiprocessor, Multicore processors for real-time consumer electronics, and Heterogeneous multicore technology for information appliances. The authors greatly appreciate this support. The R&D process on heterogeneous multicore technologies involved many researchers and engineers from Hitachi, Ltd., Renesas Electronics Corp., Waseda University, Tokyo Institute of Technology, and Mitsubishi Electric Corp. The authors would like to express sincere gratitude to all the members of these organizations associated with the projects. We give special thanks to Prof. Hideo Maejima of Tokyo Institute of Technology, Prof. Keiji Kimura of Waseda University, Dr. Toshihiro Hattori, Mr. Osamu Nishii, Mr. Masayuki Ito, Mr. Yusuke Nitta, Mr. Yutaka Yoshida, Mr. Tatsuya Kamei, Mr. Yasuhiko Saito, Mr. Atsushi Hasegawa of Renesas Electronics Corp., Mr. Shiro Hosotani of Mitsubishi Electric Corp., and Mr. Toshihiko Odaka, Dr. Naohiko Irie, Dr. Hiroyuki Mizuno, Mr. Masaki Ito, Mr. Koichi Terada, Dr. Makoto Satoh, Dr. Tetsuya Yamada, Dr. Makoto Ishikawa, Mr. Tetsuro Hommura, and Mr. Keisuke Toyama of Hitachi, Ltd. for their efforts in leading the R&D process. Finally, the authors thank Mr. Charles Glaser and the team at Springer for their efforts in publishing this book. vii

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9 Contents 1 Background Era of Digital Convergence Heterogeneous Parallelism Based on Embedded Processors... 3 References Heterogeneous Multicore Architecture Architecture Model Address Space References Processor Cores Embedded CPU Cores SuperH TM RISC Engine Family Processor Cores Efficient Parallelization of SH Efficient Frequency Enhancement of SH-X Frequency and Efficiency Enhancement of SH-X Efficient Parallelization of SH-4 FPU Efficient Frequency Enhancement of SH-X FPU Multicore Architecture of SH-X Efficient ISA and Address-Space Extension of SH-X Flexible Engine/Generic ALU Array (FE GA) Architecture Overview Arithmetic Blocks Memory Blocks and Internal Network Sequence Manager and Configuration Manager Operation Flow of FE GA Software Development Environment Implementation of Fast Fourier Transform on FE GA ix

10 x Contents 3.3 Matrix Engine (MX) MX MX Video Processing Unit Introduction Video Codec Architecture Processor Elements Implementation Results Conclusion References Chip Implementations Multicore SoC with Highly Efficient Cores RP-1 Prototype Chip RP-1 Specifications SH-X3 Cluster Dynamic Power Management Core Snoop Sequence Optimization SuperHyway Bus Chip Integration Performance Evaluations RP-2 Prototype Chip RP-2 Specifications Power Domain and Partial Power-Off Synchronization Support Hardware Interrupt Handling for Multicore Chip Integration and Evaluation RP-X Prototype Chip RP-X Specifications Dynamically Reconfigurable Processor FE GA Massively Parallel Processor MX Programmable Video Processing Core VPU Global Clock Tree Optimization Memory Interface Optimization Chip Integration and Evaluation References Software Environments Linux on Multicore Processor Porting SMP Linux Power-Saving Features Physical Address Extension Domain-Partitioning System Introduction Trends in Embedded Systems

11 Contents xi Programming Model on Multicore Processors Partitioning of Multicore Processor Systems Multicore Processor with Domain-Partitioning Mechanism Evaluation References Application Programs and Systems AAC Encoding Target System Processing Flow of AAC Encoding Process Mapping on FE-GA Data Transfer Optimization with DTU Performance Evaluation on CPU and FE-GA Performance Evaluation in Parallelized Processing Real-Time Image Recognition MX Library MX Application Applications on SMP Linux Load Balancing on RP Power Management on RP Image Filtering on RP-X Video Image Search Implementation of Main Functions Implementation of Face Recognition and GUI Controls References Index

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