Digital VLSI Design with Verilog

Transcription

1 Digital VLSI Design with Verilog

2

3 John Michael Williams Digital VLSI Design with Verilog A Textbook from Silicon Valley Polytechnic Institute Second Edition

4 John Michael Williams Wilsonville, OR USA Additional material to this book can be downloaded from ISBN ISBN (ebook) DOI / Springer Cham Heidelberg New York Dordrecht London Library of Congress Control Number: Springer International Publishing Switzerland 2014 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (

5 To my loving grandparents, William Joseph Young (ne Jung) and Mary Elizabeth Young (nee Egan) who cared for my brother Kevin and me when they didn t have to.

6

7 Preface to the Second Edition Like the first edition, this book is based on the lab exercises and order of presentation of a course developed and given by the author over a period of years at what is now Silicon Valley Polytechnic Institute, San Jose, California. To the author s best knowledge, this course was and still is the only one ever given which (a) presented the entire verilog language; (b) involved implementation of a full-duplex serdes simulation model; or (c) included design of a synthesizable digital PLL. The author wishes to thank the owner and CEO of Silicon Valley Polytechnic Institute, Dr. Ali Iranmanesh, for his patience and encouragement during the course development and in the preparation of this book. In the second edition, many minor typographical errors have been corrected, as have been several other errors newly discovered in the text and figures. Major upgrades in the second edition are: Modified Day 1 presentation making it more useful to verilog beginners Dozens of new figures Expansion or clarification of explanations on almost every page Upgrade of the simulation figures to be in color New coverage of the features of SystemVerilog and VerilogA/MS A new summary introduction to each chapter and lab exercise IEEE Stds references including SystemVerilog as well as verilog A new, optional lab checklist for recording learning progress As was done for the first edition, corrections, changes, and teaching information will be posted online at Scribd.

8

9 Table of Contents Chapter 1: Introductory Material Course Description Using this book Textbook Extras Performing the lab exercises Proprietary Information and Licensing Limitations Textbook References Supplementary Textbooks Interactive Language Tutorial Recommended Free Verilog Simulator Reading References Lab Checklist... 9 Chapter 2: Week 1 Class Today's Agenda: Introductory Lab Lab 1 Postmortem and Lecture Verilog vectors Logical (Boolean) Operators Bitwise Operators: Vectors and Reduction Operator Lab Lab postmortem First-Day Wrapup VCD File Dump SDF File Dump The Importance of Synthesis Additional Study Chapter 3: Week 1 Class Today's Agenda: More Language Constructs Traditional module header format Modern module header format Header formats contrasted Verilog comments always blocks Initial blocks Continuous assignments Vectors and vector values Parameters Commenting with verilog macroes Parameter and Conversion Lab Lab postmortem Procedural control Procedural Control Constructs... 53

10 x Table of Contents Conditional Expression Operator Combinational and Sequential Logic Verilog Strings and Messages Shift Registers Reconvergence Design Note Nonblocking Control Lab Lab postmortem Additional Study Chapter 4: Week 2 Class Today's Agenda: Net Types, Simulation, and Scan Variables and Constants Identifiers Concurrent vs Procedural Blocks Miscellaneous Other Verilog Features Backus-Naur Format (BNF) Verilog Semantics Modelling Sequential Logic Design for Test (DFT): Scan Lab Introduction Simple Scan Lab Lab postmortem Additional Study Chapter 5: Week 2 Class Today's Agenda: PLLs and the SerDes Project Phase-Locked Loops A 1x Digital PLL Introduction to SerDes and PCI Express The SerDes of this course A 32 x Digital PLL PLL Clock Lab Note on Synthesis don t_touch Lab postmortem Additional Study Chapter 6: Week 3 Class Today's Agenda: Data Storage and Verilog Arrays Memory: Hardware and Software Description Definitions of Memory Size Verilog Arrays A Simple RAM Model Verilog Concatenation Memory Data Integrity Error Checking and Correcting (ECC) ECC from parity Parity for SerDes Frame Boundaries

11 Table of Contents xi 6.4 Memory Lab Lab postmortem Additional Study Chapter 7: Week 3 Class Today's Agenda: Counter Types and Structures Introduction to Counters Terminology: Behavioral, Procedural, RTL, Structural Adder Expression vs Counter Statement Counter Structures Ripple Counter Carry Look-Ahead (Synchronous) Counter One-Hot and Ring Counters Gray Code Counter Counter Lab Lab postmortem Additional Study Chapter 8: Week 4 Class Today's Agenda: Contention and Operator Precedence Verilog Net Types and Strengths Verilog Strength Usage Race Conditions, Again Unknowns in Relational Expressions Verilog Operators and Precedence Digital Basics: Decoder and Three-State Buffer Strength and Contention Lab Strength Lab postmortem Back to the PLL and the SerDes Named Blocks The PLL in a SerDes The SerDes Packet Format Revisited Behavioral PLL Synchronization (language digression) Unsynthesizability of the Behavioral PLL Code Synthesizable, Pattern-Based PLL Synchronization PLL Behavioral Lock-In Lab Lock-in Lab postmortem Additional Study Chapter 9: Week 4 Class Today's Agenda: State Machine and FIFO design Verilog Tasks and Functions A Function For Synthesizable PLL Synchronization Concurrency by fork-join Verilog State Machines FIFO Functionality FIFO Operational Details

12 xii Table of Contents A Verilog FIFO FIFO Lab Lab postmortem Additional Study Chapter 10: Week 5 Class Today's Agenda: Rise-Fall Delays and Event Scheduling Types of Delay Expression Verilog Simulation Event Queue Simple Stratified Queue Example Event Controls Event Queue Summary Scheduling Lab Lab postmortem Additional Study Chapter 11: Week 5 Class Today's Agenda: Built-in Gates and Net Types Verilog Built-in Gates Implied Wire Names Net Types and Their Default Structural Use of Wire vs Reg Port and Parameter Syntax Note A D Flip-flop from SR Latches Netlist Lab Lab postmortem Additional Study Chapter 12: Week 6 Class Today's Agenda: Verilog Procedural Control Statements Verilog case Variants Procedural Concurrency Verilog Name Space Concurrency Lab Lab postmortem Additional Study Chapter 13: Week 6 Class Today's Agenda: Hierarchical Name Access Verilog Arrayed Instances generate Statements Conditional Macroes and Conditional generates Looping generate Statements generate Blocks and Instance Names A Decoding Tree with generate

13 Table of Contents x iii 13.2 Generate Lab Lab postmortem Additional Study Chapter 14: Week 7 Class Today's Agenda: Serial-Parallel Conversion Simple Serial-Parallel Converter Deserialization by function and task Lab Preface: The Deserialization Decoder Some Deserializer Redesign An Early ECO A Partitioning Question Serial-Parallel Lab Lab postmortem Additional Study Chapter 15: Week 7 Class Today's Agenda: UDP's, Timing Triplets, and Switch-level Models User-Defined Primitives (UDP's) Delay Pessimism Gate-Level Timing Triplets Switch-Level Components Switch-Level Net: The trireg Component Lab Lab postmortem Additional Study Chapter 16: Week 8 Class Today's Agenda: Parameter Types and Module Connection Summary of Parameter Characteristics ANSI Header Declaration Format Traditional Header Declaration Format Instantiation Formats Parameter Format Values ANSI Port and Parameter Options Traditional Module Header Format and Options defparam Connection Lab Connection Lab postmortem Hierarchical Names and Design Partitions Hierarchical Name References Scope of Declarations Design Partitioning Synchronization Across Clock Domains Hierarchy Lab Lab postmortem Additional Study

14 xiv Table of Contents Chapter 17: Week 8 Class Today's Agenda: Verilog configurations Libraries Verilog Configuration Timing Arcs and specify Delays Arcs and Paths Distributed and Lumped Delays specify Blocks specparams Parallel vs. Full Path Delays Conditional and Edge-Dependent Delays Conflicts of specify with Other Delays Conflicts Among specify Delays Conflicts with SDF Delays Timing Lab Lab postmortem Additional Study Chapter 18: Week 9 Class Today's Agenda: Timing Checks Timing Checks and Assertions Timing Check Rationale The Twelve Verilog Timing Checks Negative Time Limits Timing Check Conditioned Events Timing Check Notifiers Pulse Filtering PATHPULSE Syntax specparam Improved Pessimism Miscellaneous time-related Types Timing Check Lab Additional Study Chapter 19: Week 9 Class Today's Agenda: The Sequential Deserializer PLL Redesign Improved VFO Clock Sampler Synthesizable Variable-Frequency Oscillator Synthesizable Frequency Comparator Modifications for a 400 MHz 1x PLL Wrapper Modules for Portability Sequential Deserializer I Lab Lab postmortem Additional Study

15 Table of Contents xv Chapter 20: Week 10 Class Today's Agenda: The Concurrent Deserializer Dual-porting the Memory Dual-clocking the FIFO State Machine Upgrading the FIFO for Synthesis Upgrading the Deserialization Decoder for Synthesis Concurrent Deserializer II Lab Lab postmortem Additional Study Chapter 21: Week 10 Class Today's Agenda: The Serializer and The SerDes The SerEncoder Module The SerialTx Module The SerDes SerDes Lab Lab postmortem Additional Study Chapter 22: Week 11 Class Today's Agenda: Design for Test (DFT) Design for Test Introduction Assertions and Constraints Observability Coverage Corner-Case vs. Exhaustive Testing Boundary Scan Internal Scan BIST Design For Test Summary Scan and BIST Lab Lab postmortem DFT for a Full-Duplex SerDes Full-Duplex SerDes Test Logic Questions Tested SerDes Lab Lab postmortem Additional Study Chapter 23: Week 11 Class Today's Agenda: SDF Back-Annotation Back-Annotation SDF Files in Verilog Design Flow Verilog Simulation Back-Annotation

16 xvi Table of Contents 23.2 SDF Lab Lab postmortem Additional Study Chapter 24: Week 12 Class Today's Agenda: Wrap-up: The Verilog Language Verilog-1995 vs 2001 (or 2005) Differences Verilog Synthesizable Subset Review Constructs Not Exercised in this Course List of all verilog system tasks and functions List of all verilog compiler directives Verilog PLI Continued Lab Work (Lab 23 or later) Additional Study Chapter 25: Week 12 Class Today's Agenda: Deep-Submicron Problems and Verification Deep Submicron Design Problems The Bigger Problem Modern Verification Formal Verification Nonlogical Factors On The Chip System Verilog Some Features of SystemVerilog SystemVerilog Conclusion Verilog-AMS Introduction Relationship to Other Languages Analogue Functionality Overview Analogue and Digital Interaction Example: VAMS DFF Benefits of VAMS Continued Lab Work (Lab 23 or later) Additional Study Index