MPSoC Approaches for Low-power Embedded Soc's

Transcription

1 MPSoC Approaches for Low-power Embedded Soc's Development Dept. 1 Toshihiro Hattori, June 26, 2007 Outline Approaches for Embedded MPSoC SH-MobileG1 : AP+BB Onechip SH-X3: SuperH SH-4A Quad-Core EXREAL Platform: Solution Platform for MPSoC Conclusion 2 1

2 Approaches for Embedded MPSoC Embedded MPSoC Specific : Optimized for the embedded systems Low Power: Less than 5W, Less than 1W Embedded Software: Optimized HW/SW for the embedded system (1)Heterogeneous AMP : Integration of subsystems SH-MobileG1 : One chip integration of & BB (2) Homogeneous AMP : Hetero-OS / Homo-OS SH-X3 : SuperH core for Multi-processor (3) Homogeneous SMP : SMP OS SH-X3 : SuperH core for Multi-processor (4) Automatic Parallelizing Compiler SH-X3 : SuperH core for Multi-processor 3 SH-MobileG1: AP+BB Onechip ref: T. Hattori, et. al., A power management scheme controlling 20 power domains for a single chip mobile processor. ISSCC Dig. Tech. pp , Feb 2006 M. Ito, et. al., SH-MobileG1: A Single-Chip and Dual-mode Baseband Processor., HOTCHIPS 18, Aug

3 3G Multi-Media Cellular Phone System HPA High Power Amplifier RFIC Radio Frequency IC Baseband Processor Processor Multi-Media Accelerator Previous System HPA High Power Amplifier RFIC Radio Frequency IC One Chip SH-MobileG1 New System Using G1 5 A Sample of System Architecture using G1 Video Camera Audio M/W M/W M/W Realtime OS (ITR, etc.) Camera Mail Video Phone Browser Telephone API File System JAVA Device Driver General Purpose OS (Symbian, Linux, etc.) GSM/WCDMA Protocol Stack Realtime OS (ITR, etc.) -Realtime domain AP-RT (SH) SuperHyway Bus Multi-Media Accelalators -System domain APSYS (ARM) Bridge SuperHyway Bus Bridge System Baseband domain BB- (ARM) W-CDMA IP GSM/GPRS IP SD SD 6 3

4 SH-MobileG1: Chip Overview CPG DDR Sound Die size 11.15mm x 11.15mm W-CDMA AP-Misc AP-SYS Process 90nm LP 8M(7Cu+1Al) CMOS dual-vth BB- 3D G MPEG Misc JPEG BB- Camera LCDCMedia APL-RT GSM S Supply voltage # of TRs, gate, memory 1.2V(internal), 1.8/2.5/3.3V(I/O) 181M TRs, 13.5M Gate 20.2 Mbit mem 7 G1 Module Diagram AHB Bus BB Core Block I- D- Cache Cache MMU DMAC INT ARM9 AP-SYS Block ARM9 I- D- Cache Cache MMU APB Bus WCDMA Block MODEM BB Main Bus BBSC GSM Block MODEM SYSC WUC AP-RT Block CPG BB INTC BB SH-X2 XY I- D- Cache Cache U MMU Media Bus LCDC VIO VPU JPU ABB LCD Camera APBB SuperHyway (SYS) INTC DMAC BSC SYS MFI CPG AP HP Bus (SYS) (SYS) S2S SuperHyway (RT) SBSC DMAC 3DG (RT) HP Bus (RT) INTC RT MFI 8 4

5 erbscsiaeriacommunication Architecture - G1 keeps the communication paths (MFI and Serials) used in the previous system for software reuse SH-MobileG1 (1 LSI with 3 s) Baseband APBB AP-SYS S2S AP-RT Baseband LSI lbbscbsc AP-RT LSISAP-SYS LSI lprevious System with 3 LSIs Serial Serial MFI Memory MFI MFI 9 Communication Architecture (Cont d) - AP-SYS and AP-RT share SD and memory map - AP and BB have different SD and memory map - APBB bridge supports access window scheme to access the resource in the other memory map Flash BB SD AP Access Window Using AP-BB bridge BB Periphral Regs BB Address Map Map any region of AP address by register settings Map any region of BB address by register settings Flash SYS Periphral Regs AP SD BB Access Window Using AP-BB bridge RT Periphral Regs AP Address Map 10 5

6 Interrupt Control - Each has its INT controller - MFI can generate inter-domain interruptions - Some external pins generate interrupts for each Baseband AP-SYS AP-RT INTC (BB) INTC (SYS) INTC (RT) (BB) MFI (SYS) MFI (RT) 11 System Control Baseband Reset Clock AP-SYS Reset Clock Reset Clock AP-RT S:Semaphore Register P:Power Down Register W:Wake-up Register B: Boot Control Register Boot Address CPGBB CPGAP S P W B S P W B S P W B Reset Reset SYSCBB Control SYSCSYS Control SYSCRT Power Control SYSC (Common) PLLs Semaphore Free:00 RT:01 SYS:10 BB:11 Boot Address PLLs Boot Control (Master, Boot Address for each ) Boot Address Boot Mode RESET WakeUp 12 6

7 Power Domain (Cont d) 20 hierarchical domains for partial power-off Chip Floorplan Power Domains CPG DDR Sound W-CDMA AP-Misc AP-SYS BB- Misc 3D G MPEG JPEG Camera BB- LCDCMedia APL-RT GSM S BC AC BW2 A2 BA2 C4 BA4 BA3 A1R BG1 BG3 BG2 BW3 BW1 A4U2 C5 A4 A1A A4U1 A3 13 Leakage Current in Usage Scenes (1) Video telephony BW2 BW3 BC AC A2 BA2 C4 BA4 C5 A4 A1A Baseband part Control W-CDMA GSM / OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 part System-domain Realtime-domain Power on Measured Leakage Current (@ Room Temp, 1.2V) 849 μa 14 7

8 Leakage Current in Usage Scenes (2)Telephony (W-CDMA) BW2 BW3 BC AC A2 BA2 C4 BA4 C5 A4 A1A Baseband part Control W-CDMA GSM / OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 part System-domain Realtime-domain OFF Power on Measured Leakage Current (@ Room Temp, 1.2V) 407 μa 15 Leakage Current in Usage Scenes (3)Waiting for Calling BW2 BW3 BC AC A2 BA2 C4 BA4 C5 A4 A1A Baseband part Control W-CDMA GSM OFF * OFF BW1 BG1 BA3 BG2BG3 A1R A4U2 A4U1 A3 part System-domain Realtime-domain OFF OFF Power on Measured Leakage Current (@ Room Temp, 1.2V) *: Intermittent Operation 299 μa 16 8

9 SH-X3: SuperH SH-4A Quad-Core ref: T. Kamei, SH-X3 An Enhanced SuperH Core for Low power MP system. Fall Microprocessor Forum, Oct 2006 Y. Yoshida, et. al., A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption., ISSCC Tech. Dig. pp , Feb Design Concept of SH-X3 Efficient for both SMP and AMP Cache coherency for SMP Local Memories of each block for AMP Data transfer function for local memories Hybrid model support Flexible interrupt architecture Interrupt distribution Inter Processor Interrupt (IPI) Power management Minimizing the power of each for workload variation Easy implementation in standard SoC design flow Fully synthesizable 18 9

10 Block Diagram Clock Controller Interrupt Controller Debug block 0 FPU/ MMU I$ D$ IL DL U block 1 FPU/ MMU I$ D$ U SH-X3 IL DL Snoop Controller block 2 FPU/ MMU I$ D$ IL DL U block 3 FPU/ MMU I$ D$ IL DL U SuperHyway (main on-chip interconnect) 19 SuperHyway = SuperHyway Bus on-chip interconnect Memory subsystem architecture Combination of coherent cache and local memories to support variety of programming models Coherent cache Implicit allocation (programmer doesn t have to care) Mandatory for SMP operating systems Required for multi-threaded programs (e.g. with pthread library) Address-mapped local memories Explicit allocation (deterministic behavior) Add further concurrency of computation and data transfer to ordinal DMA transfer Efficient block transfer (larger than cache line size) Two-level local memories Small but no-wait memory (I/D separate: up to 128KB) Large but a few wait memory (unified: up to 1MB) 20 10

11 Data Transfer Unit () Concurrent data transfer with computation Programmability by transfer commands on local memories MMU support: micro-tlb Max. throughput: 800 MB/s 300MHz SuperHyway 0 UTLB 1 Local Mem. commands src. μtlb Put SuperHyway Automatic Parallelizing Compiler (OSCAR compiler by Waseda Univ.) Parallelization of sequential programs Extraction of data transfer and generation of commands Almost same performance as hand parallelized (MPEG2 enc.) C source main () {... } compile SH inst. 0 inst. add add R0, R0, R1 R1 mult mult R1, R1, R2 R Local Mem. commands + dst. UTLB μtlb 0 cmd. cmd. chk chk 0xFF11.. 0xFF11.. get get 0x x set set 0xFF12 0xFF12 21 Interrupt architecture Two distribution modes Static mode bound to specified (configurable binding) Dynamic mode (used in some SMP OSs) broadcasted to all s serviced by ACK'ed first Inter Processor Interrupt To communicate with other s from peripheral modules Interrupt Controller Interrupt requests from external pins 22 11

12 Power Management Fine power management for workload variation Independent clock slowing down for each Four low power states state Light Sleep Sleep Resume-Standby Ultra-Standby Clock stop Clock stop cache Active Clock stop local mem. Active Active Clock stop 0 Local Mem. Sleep 1 Local Mem. Get 2 Local Mem. Put 3 Local Mem. Sleep 0: job done 1: on-going 2: on-going 3: waiting for data SuperHyway 23 RP1: Chip Overview Core #0 Core #2 SNC Core #1 Core #3 Die size Process Supply voltage Frequency I/D Cache IL DL User Performance FPU Performance Power 9.88mm x 9.88mm 90nm G 8-layer CMOS dual-vth 1.0V(internal), 1.8/3.3V(I/O) 600MHz 32KB 4way(each ) 8KB (each ) 16KB (each ) 128KB (each ) 4320MIPS (Dhrystone2.1) 16.8 GFLOPS 0.6mW/MHz/Core 24 12

13 EXREAL Platform TM EXcellent Reliability Efficiency Agility Link Platform 25 EXREAL Platform TM Software Interconnect Promote reuse of software assets through Wrapper and standardized layer API Control operating frequency and power on/off through the performance scheduler Mobile Phone Wrapper Base band middleware Wrapper Function distributing multi-os Real-time OS Wrapper 2D Graphic middleware Wrapper 3D Graphic middleware Wrapper Wrapper Load distributing multi-os Versatile OS Versatile OS Inter-task / Inter-OS communication Multicore Standard Logical Standard multicore Performance driver Multi-core multicore library Physical library library scheduler driver library HW-IP - Middleware Middleware-OS OS-Driver Hide number with the distributed object framework Layer API Layer API Layer API 26 13

14 Software Does Not Need to Worry about Hardware Flexible replacement of hardware IP and software IP IP changes in the lower layer do not affect the upper layer Possible to select different implementation that possess the identical API Software Customer's area of application development Level API library, OS Low end Popular Mid-level High end Same interface Middleware Level API Middleware library Device Level API Hardware engine Media processor or or Multi-core Algorithm library Accelerator Hardware 27 EXREAL Platform TM : Hardware Interconnect Implement the optimum method for the target processing Software processing = Heterogeneous multi-core Versatile SMP Reconfigurable SIMD D Versatile On-chip bus Moving image Still image Processing processing Voice processing accelerator accelerator accelerator External memory I/F Communication IP Cipher IP Acceleration that is fit for specific algorithm processing Realize processing through hardware 28 14

15 Summary There is many approaches for embedded MPSoC. Heterogeneous AMP : Integration of subsystems Homogeneous AMP : Hetero-OS / Homo-OS Homogeneous SMP : SMP OS Automatic parallelizing compiler System design which implement optimal parallelism with reasonable software design/debug cost is key. Renesas is ready to implement MPSoC for the application specific requirements by various approaches with SH-MobileG1 methodology and SH-X3. Renesas is proposing EXREAL Platform TM for embedded system design with MPSoC