MRF Timing System Status Update. Timing Workshop ICALEPCS Jukka Pietarinen Micro-Research Finland Oy

Transcription

1 MRF Timing System Status Update Timing Workshop ICALEPCS 2017 Jukka Pietarinen Micro-Research Finland Oy

2 Delay Compensation (DC) Typical System Layout Event link protocol carries: 8 bit event event rate max. 142 MHz 8 bit distributed data ½ event rate Data buffer transfers up to 2 kbyte Segmented data buffers up to 128 x 16 bytes Max. data transfer rate 71 Mbytes/s

3 Topology of Simple System without EVG and Delay Compensation

4 Delay Compensation Capable Hardware Currently available hardware VME-EVM-300 (Event Generator + Fan-Out/Concentrator + EVRs) VME-EVR-300 PCIe-EVR-300DC mtca-evr-300i mtca-evr-300u Planned hardware mtca-evm-300 (Event Generator + Fan-Out/Concentrator + EVRs)

5 Hardware without Delay Compensation Capability Still active products VME-EVG-230 VME-EVR-230 VME-EVR-230RF VME-FOUT-12 cpci-evg-230 cpci-evr-230 cpci-evg-300 cpci-evr-300 cpci-fout-12 PMC-EVR-300 End of life products cpci-evrtg-300 cpci-fct-8 PXIe-EVG-300 PXIe-EVR-300

6 VME-EVM-300 Event Generator (EVG) 2 sequencers with maskable events Max events/sequence 32 bit timestamp 8 multiplexed counters data buffer up to 2k bytes segmented data buffer 127 segments, 16 bytes each 8-Way Fan-Out/Concentrator Two Event Receivers (EVR) 8 internal pulse outputs one sequencer Event rate conversion (with some data buffer related limitations) Front panel input phase monitoring/select features Distributed bus phase selection RF input monitoring

7 Delay Compensation EVR (VME-EVR-300, mtca-evr-300, PCIe-EVR-300DC) Stand-alone operation without EVG running on internal reference clock One Sequencer similar to EVG sequencer Can be triggered from pulse generator output (event) / distributed bus bit or prescaler output Software events Can be used in both DC and non-dc mode

8 MTCA.4 Event Receiver mtca-evr-300u Two Universal I/O slots in front panel Due to offset of front panel the distance between PCB has to be reduced using 8 mm spacer instead of a earlier used 10 mm spacer Usable but fit is not perfect, also filler panel mounting suffers from a reduced front panel thickness

9 New Universal I/O TTL Input Module UNIV-TTLIN/IL Replaces both UNIV-TTLIN and UNIV-TTLIN-IL Configurable termination by jumper 50 ohm to ground 240 ohm to +5 V

10 I/O Breakout Issues IFB-300 mechanics becoming obsolete Molex cable discontinued VHDCI/microSCSI connector is fragile and you have to fix the cable mechanically, cannot rely on screwing in connector Alternative ways to get I/O from small front panels? Asked HW-talk mailing list for advice no replies :(

11 MTCA.4 Event Master in Development Almost same as VME-EVM-300 with small changes Different number of SFPs Missing ethernet interface (locate on rear I/O TBD) Event Generator Fan-Out Concentrator 8 Front panel SFP optical ports 4 Backplane point-to-point ports Limited front panel size RF input TTL input

12 MTCA.4 Event Master Possibility to use backplane point-to-point links (port 12-15) for additional fanout ports?

13 EVM configured as System Master

14 EVM configured as Fan-Out

15 EVM Front Panel TTL Inputs with Phase Select and Phase Monitoring Allows using externally generated subharmonics of the event clock for e.g. triggering sequencers Due to data transfers the distributed bus in running at half rate (event clock/2), logic has been added to be able to match the distributed bus phase with the rising edge of an external signal Use case SwissFEL: superperiod generated externally

16 EVR Simplified Block Diagram

17 VME-EVM-300 Configured as Delay Compensation Master

18 VME-EVM-300 Configured as Delay Compensation Fan-Out

19 Delay Compensation Event Receiver

20 Delay Compensation Capable Event Receiver in non-dc mode

21 Compatibility with the Earlier Protocol Delay Compensation extends the protocol by: Using event code 0x7E as beacon event Adds the segmented data buffer that uses a different transfer start comma character than the data buffer Both protocol changes are ignored by pre-dc event hardware Timing is similarly deterministic as with a pre-dc distribution network Delay Compensation EVRs can be used with the earlier protocol in non-dc mode The Delay Compensation FIFO can be used to fine tune the EVR output delays as a group with very high resolution EVMs require the top node to be configured as the Delay Compensation Master EVMs can be used in Delay Compensation Mode only

22 MRF Event System Protocol Based on 8B10B encoding using data characters D00.0 through D31.7 and K-characters K28.0, K28.1, K28.2 and K28.5 Each event clock cycle two characters are transmitted One event code character One data character Event code slot D00.0 null event D01.0 through D31.7 event codes 0x01 through 0xFF K28.5 comma character for synchronization, both 8B10B encoding and event protocol, sent out every 4th event slot instead of character D00.0 Data slot Multiplexed between 8 bit distributed data bus and data transfers Distributed data bus transfers parallel to K28.5 event slots

23 MRF Event System Protocol Data transfers Configurable size data buffer K28.0 start of data packet Dxx.x, Dxx.x, Dxx.x, packet data K28.1 end of data packet Dxx.x, Dxx.x checksum 0xFFFF sum of data bytes Segmented data buffer (16 byte segments) K28.2 start of segmented data packet Dxx.x start segment number 0x00 to 0x7F (last segment reserved for delay compensation) Dxx.x, Dxx.x, Dxx.x, segment data K28.1 end of transfer Dxx.x, Dxx.x checksum 0xFFFF segment address sum of data bytes

24 Towards Open Source Event Receiver Hardware to be used for development Avnet PicoZed AES-Z7PZ-7Z030-SOM-G Avnet PicoZed FMC carrier AES-PZCC-FMC-V2-G Zync 7Z030 incorporates Kintex-based FPGA core Four GTX transceivers Dual-core ARM Cortex-A9 This kit has everything from the hardware point of view to be used as an event receiver

25 Open Source EVR Project Help needed New to Zync Bus interface on IP core? Setting up repository How to deal with closed source IP cores? sharing configuration files in a repository? How to efficiently rebuild a project and IP cores from repository Vivado tcl scripts? Establish working group? Setting up mailing list?