System Design Choices
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1 System esign hoices Programmable Logic PL e.g. Lattice ispgl22v10, tmel TF1502 PL Field Programmable Gate rray (FPG) e.g. ltera yclone III, Xilinx rtix-7/zync-7000 Semi-ustom esign Mask Programmable Gate rray e.g. ES MOS Gate rray ltera Hardopy II structured SIs Standard ell esign e.g. lcatel Mietec MT µm cell library Full ustom esign 8001
2 System esign hoices Programmable Logic STRT HERE est possible design turnaround time heapest for prototyping est time to market Minimum skill required Semi-ustom esign Full ustom esign heapest for mass production Fastest Lowest Power Highest ensity 1 Most skill required 1 optimization limited by speed/power/area trade off 8002
3 Programmable Logic IT PEEL22V10 Source: IT One time use - Fuse programmable. Reprogrammable - UV/Electrically Erasable. 8003
4 Field Programmable Gate rray Xilinx X4000 I/O uffers Programmable Interconnection Point L L I/O uffers L L Vertical Routing hannel I/O uffers L Switching Matrix Horizontal Routing hannel I/O uffers onfigurable Logic locks (Ls) & I/O locks 2 Programmable Interconnect 2 Xilinx X4013 has 576 (24 24) Ls and up to 192 (4 48) user I/O pins. 8004
5 Field Programmable Product Obsolete Gate rray or Under Xilinx Obsolescence X4000 L X4000E and X4000X Series Field Programmable Gate rrays R H 1 IN /H 2 /H0 E G 4 S/R ONTROL ypass G 3 G 2 LOGI FUNTION OF G1-G4 G' IN F' G' H' S Y G 1 LOGI FUNTION OF H' F', G', N H1 G' H' 1 E R Y F 4 F 3 F 2 LOGI FUNTION OF F1-F4 F' IN F' G' H' S/R ONTROL S ypass X F 1 K (LO) H' F' 1 E R X Multiplexer ontrolled by onfiguration Program X6692 Figure 1: Simplified lock iagram of X4000 Series L (RM and arry Logic functions not shown) Flip-Flops The L can pass the combinatorial output(s) to the interconnect network, but can also store the combinatorial results or other incoming data in one or two flip-flops, and connect their outputs to the interconnect network as well lock Enable Source: Xilinx The clock enable signal (E) is active High. The E pin is shared by both storage elements. If left unconnected for either, the clock enable for that storage element defaults to the active state. E is not invertible within the L.
6 X-Ref Target - Figure 2-3 Slice escription OUT HI LO Reset Type Sync/sync FF/LT X 6:1 I I2 6:1 I1 WEN M31 HI LO X FF/LT INIT1 HI LO MUX X 6:1 I I2 6:1 I1 WEN M31 HI LO INIT1 X FF/LT HI LO MUX X 6:1 I I2 6:1 I1 WEN M31 HI LO INIT1 X FF/LT HI LO MUX X 6:1 I LK WE I2 6:1 I1 WEN M31 0/1 WEN IN X FF/LT HI LO MUX UG474_c2_02_ rtix-7 SLIM L Figure 2-3: iagram of SLIM Source: Xilinx Series FPGs L User Guide 19 UG474 (v1.7) November 17, 2014
7 6:1 I X Xilinx rtix-7 SLIM L 3 I2 6:1 I 6:1 I1 WEN M31 6:1 I1 WEN M31 HI LO INIT1 HI LO INIT1 X X FF/LT HI LO FF/LT HI LO MUX X 6:1 I LK WE I2 6:1 I1 WEN M31 0/1 WEN IN X FF/LT HI LO MUX UG474_c2_02_ Figure 2-3: iagram of SLIM 4x 6-input Look-Up Tables (LUTs) for combinational logic 7Series FPGs L User Guide 19 UG474 (v1.7) November 17, 2014 arry chain supporting fast carry lookahead 8x storage elements LUTs can be alternatively configured as 256 bits RM 32-bit shift register Source: Xilinx 3 Xilinx X7200T has 16,825 Ls (each containing 2 slices) and up to 500 user I/O pins. 8007
8 FPG - System On hip Modern FPGs are big enough for: One or more soft-core processors Program memory ata memory + specialist hardware The new trend is for FPGs with hard processors built in: Xilinx Zync-7000 includes dual-core RM 9 ltera rria V includes dual-core RM 9 ypress PSo 4 includes RM ortex-m0 and programmable digital 4 and analog blocks 4 here the digital block is PL rather than FPG 8008
9 Mask Programmable Gate rray 9 Output Pads V Pad 68 Gate Sites arranged as 4 columns of 17 sites each. 8 Input Pads 8 Input Pads GN Pad 9 Output Pads 8009
10 Mask Programmable Gate rray GN Vdd GN Vdd X X X X O O O O Vdd O GN ustomize Metal and ontact Window masks only. 8010
11 Standard ell esign Logic Functions uto Generated Macro locks PL ROM RM System Level locks Microprocessor core 5 5 Will support System On hip applications. 8011
12 Full ustom ll design styles need full custom designers to design the base programmable logic chips to design building blocks for semi-custom Where large SIs use full custom techniques they are likely to be used alongside semi-custom techniques. e.g. Hand-held computer game chip Full custom bitslice datapath hand crafted for optimum area efficiency and low power consumption Standard cell controller Macro block RM, ROM 8012
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