PowerPC Instruction Set Extension Guide
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1 PowerPC Instruction Set Extension Guide ISA Support for the PowerPC APU Controller in Virtex-4 EDK 6.3 November 4, 004 R
2 PowerPC Instruction Set Extension Guide EDK 6.3 November 4,
3 "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC064, XC3090, XC4005, and XC50 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alliance Series, AllianceCORE, Bencher, ChipScope, Configurable Logic Cell, CORE Generator, CoreLINX, Dual Block, EZTag, Fast CLK, Fast CONNECT, Fast FLASH, FastMap, Fast Zero Power, Foundation, Gigabit Speeds...and Beyond!, HardWire, HDL Bencher, IRL, J Drive, JBits, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor, MicroBlaze, MicroVia, MultiLINX, NanoBlaze, PicoBlaze, PLUSASM, PowerGuide, PowerMaze, QPro, Real-PCI, Rocket I/O, SelectI/O, SelectRAM, SelectRAM+, Silicon Xpresso, Smartguide, Smart-IP, SmartSearch, SMARTswitch, System ACE, Testbench In A Minute, TrueMap, UIM, VectorMaze, VersaBlock, VersaRing, Virtex-II Pro, Virtex-II EasyPath, Wave Table, WebFITTER, WebPACK, WebPOWERED, XABEL, XACT- Floorplanner, XACT-Performance, XACTstep Advanced, XACTstep Foundry, XAM, XAPP, X-BLOX +, XC designated products, XChecker, XDM, XEPLD, Xilinx Foundation Series, Xilinx XDTV, Xinfo, XSI, XtremeDSP and ZERO+ are trademarks of Xilinx, Inc. The Programmable Logic Company is a service mark of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others. Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products. Xilinx provides any design, code, or information shown or described herein "as is." By providing the design, code, or information as one possible implementation of a feature, application, or standard, Xilinx makes no representation that such implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation, including but not limited to any warranties or representations that the implementation is free from claims of infringement, as well as any implied warranties of merchantability or fitness for a particular purpose. Xilinx, Inc. devices and products are protected under U.S. Patents. Other U.S. and foreign patents pending. Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user. Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited. The contents of this manual are owned and copyrighted by Xilinx. Copyright Xilinx, Inc. All Rights Reserved. Except as stated herein, none of the material may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of any material contained in this manual may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. EDK 6.3 November 4, PowerPC Instruction Set Extension Guide
4 PowerPC Instruction Set Extension Guide EDK 6.3 November 4, 004 The following table shows the revision history for this document. Version /4/04.0 Initial release. Revision PowerPC Instruction Set Extension Guide EDK 6.3 November 4,
5 Table of Contents About This Document Document Conventions... 7 General Conventions... 7 Chapter : APU Instruction Set Extension Alphabetical Instruction Listing... 9 PowerPC Processor Reference Guide 5 EDK 6. September,
6 6 PowerPC Processor Reference Guide EDK 6. September, 003
7 Preface About This Document This document is an addendum to the Instruction Set Architecture (ISA) chapter in the PowerPC Processor Reference Guide [UG0]. The description herein is focused on the Embedded Development Kit (EDK) extension of the ISA through the Auxiliary Processor Unit (APU) of the PowerPC 405 in Virtex-4. The PowerPC relies on custom processing logic implemented in the FPGAS fabric, called Fabric Co-processing Modules (FCM) to execute these instructions. An FCM can be either a user IP or a Xilinx IP. Please refer to the following documents for more information on the use and design of co-processors for the PowerPC APU interface: PowerPC Block Reference Guide [UG08] PPC405_Virtex4 [DS306] Fabric Co-processor Bus [DS308] FCBFSL_Bridge [DS309] Document Conventions General Conventions This document follows the same standards as the PowerPC Processor Reference Guide. PowerPC Processor Reference Guide 7 EDK 6. September,
8 Preface: 8 PowerPC Processor Reference Guide EDK 6. September, 003
9 Chapter APU Instruction Set Extension Alphabetical Instruction Listing The following pages list the Auxiliary Processor Unit instruction set extension supported by the PPC405 in alphabetical order. PowerPC Processor Reference Guide 9 EDK 6. September,
10 get Get from FSL co-processor via APU controller Chapter : get rd, FSLx get data from FSL x (blocking) nget rd, FSLx get data from FSL x (non-blocking) ncget rd, FSLx get control from FSL x (blocking) ncget rd, FSLx get control from FSL x (non-blocking) X Instruction Form 4 rd FSL 8 n c Description This is a privileged instruction. The processor will read from the FSLx interface and place the result in register rd. The get instruction has four variants. The blocking versions (n=0) will stall processor until data is available. The non-blocking versions will return even if data is not available. XER[CA] is set to 0 if the data is valid and to if the data was invalid. In case of an invalid access the destination register contents is undefined. The get and nget instructions expect the control bit from the FSL interface to be 0. If this is not the case, the instruction will set XER[OV] to. The cget and ncget instructions expect the control bit from the FSL interface to be. If this is not the case, the instruction will set XER[OV] to. Pseudocode (rd) APU(FSL).data if (n = ) then XER[CA] not APU(FSL).exists if (APU(FSL).control == c) then XER[OV] 0 else XER[OV] Registers Altered rd. XER[OV]. XER[CA] if n=. Exceptions None. Compatibility This instruction is defined by Xilinx as a User Defined Instruction (UDI) that uses the PowerPC Auxiliary Processor Unit (APU) controller. 0 PowerPC Processor Reference Guide EDK 6. September, 003
11 put Put to FSL co-processor via APU controller put ra, FSLx put data to FSL x (blocking) nput ra, FSLx put data to FSL x (non-blocking) cput ra, FSLx put control to FSL x (blocking) ncput ra, FSLx put control to FSL x (non-blocking) X Instruction Form ra FSL 5 n c Description This is a privileged instruction. The processor will write the contents of register ra to the FSLx interface. The put instruction has four variants. The blocking versions (n=0) will stall the processor until there is space available on the FSL interface. The non-blocking versions will return even if there is no space. XER[CA] is set to 0 if space was available and to if no space was available. The put and nput instructions will set the control bit to the FSL interface to 0. The cput and ncput instruction will set the control bit to. Pseudocode APU(FSL).data (ra) APU(FSL).control c if (n = ) then XER[CA] APU(FSL).full Registers Altered XER[CA]. Exceptions None. Compatibility This instruction is defined by Xilinx as a User Defined Instruction (UDI) that uses the PowerPC Auxiliary Processor Unit (APU) controller. PowerPC Processor Reference Guide EDK 6. September,
12 Chapter : PowerPC Processor Reference Guide EDK 6. September, 003
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KC705 Si570 Programming March 2012 Copyright 2012 Xilinx XTP186 Revision History Date Version Description 03/02/12 13.4 Initial version. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx
Virtex-5 GTP Aurora v2.8
0 DS538 October 10, 2007 0 0 Introduction The Virtex -5 GTP Aurora core implements the Aurora protocol using the high-speed serial GTP transceivers in Virtex-5 LXT and SXT devices. The core can use up
ML605 GTX IBERT Design Creation
ML605 GTX IBERT Design Creation December 2010 Copyright 2010 Xilinx XTP046 Revision History Date Version Description 12/21/10 12.4 Recompiled under 12.4. 10/05/10 12.3 Recompiled under 12.3. AR36576 fixed.
Intel Cluster Ready Allowed Hardware Variances
Intel Cluster Ready Allowed Hardware Variances Solution designs are certified as Intel Cluster Ready with an exact bill of materials for the hardware and the software stack. When instances of the certified
AC701 Ethernet Design Creation October 2014
AC701 Ethernet Design Creation October 2014 XTP223 Revision History Date Version Description 10/08/14 9.0 Regenerated for 2014.3. 06/09/14 8.0 Regenerated for 2014.2. 04/16/14 6.0 Regenerated for 2014.1.
AC701 Ethernet Design Creation June 2014
AC701 Ethernet Design Creation June 2014 XTP223 Revision History Date Version Description 06/09/14 8.0 Regenerated for 2014.2. 04/16/14 6.0 Regenerated for 2014.1. 12/18/13 5.0 Regenerated for 2013.4.
Virtex-4 PowerPC Example Design. UG434 (v1.2) January 17, 2008
Virtex-4 PowerPC Example Design R R 2007-2008 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks
Enhanced Serial Peripheral Interface (espi) ECN
Enhanced Serial Peripheral Interface (espi) ECN Engineering Change Notice TITLE Clarify OOB packet payload DATE 10 January 2014 AFFECTED DOCUMENT espi Base Specification Rev 0.75 DISCLOSURE RESTRICTIONS
SP605 GTP IBERT Design Creation
SP605 GTP IBERT Design Creation October 2010 Copyright 2010 Xilinx XTP066 Revision History Date Version Description 10/05/10 12.3 Recompiled under 12.3. ARs Present in Spartan-6 IBERT Design: AR36775 Delay
PCI Express Link/Transaction Test Methodology
PCI Express Link/Transaction Test Methodology September 29, 2006 Revision 1.1 This page is intentionally left blank. 2 PCI Express Link/Transaction Test Methodology, Rev 1.1 Revision History Document
KC705 GTX IBERT Design Creation October 2012
KC705 GTX IBERT Design Creation October 2012 XTP103 Revision History Date Version Description 10/23/12 4.0 Regenerated for 14.3. 07/25/12 3.0 Regenerated for 14.2. Added AR50886. 05/30/12 2.1 Minor updates.
Terms of Use. Changes. General Use.
Terms of Use THESE TERMS AND CONDITIONS (THE TERMS ) ARE A LEGAL CONTRACT BETWEEN YOU AND SPIN TRANSFER TECHNOLOGIES ( SPIN TRANSFER TECHNOLOGIES, STT, WE OR US ). THE TERMS EXPLAIN HOW YOU ARE PERMITTED
CALSTRS ONLINE AGREEMENT TERMS AND CONDITIONS
CALSTRS ONLINE AGREEMENT TERMS AND CONDITIONS INTRODUCTION: Before the California State Teachers Retirement System (hereinafter "CalSTRS," "We," or "Us") will provide services found at mycalstrs.com (the
LogiCORE IP Soft Error Mitigation Controller v1.1
LogiCORE IP Soft Error Mitigation Controller v1.1 DS796 September 21, 2010 Introduction The LogiCORE IP Soft Error Mitigation (SEM) Controller is an automatically configured, pre-verified solution to detect
KC705 PCIe Design Creation with Vivado August 2012
KC705 PCIe Design Creation with Vivado August 2012 XTP197 Revision History Date Version Description 08/20/12 1.0 Initial version. Added AR50886. Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX,
ML605 Built-In Self Test Flash Application
ML605 Built-In Self Test Flash Application October 2010 Copyright 2010 Xilinx XTP056 Revision History Date Version Description 10/05/10 12.3 Up-rev 12.2 BIST Design to 12.3. Added AR38127 Added AR38209
Discontinued IP. Verification
0 3GPP2 Turbo Decoder v2.1 DS275 February 15, 2007 0 0 Features Drop-in module for Spartan -3, Spartan-3E, Spartan-3A/3AN, Virtex -II, Virtex-II Pro, Virtex-4, and Virtex-5 FPGAs Implements the CDMA2000/3GPP2
7 Series FPGAs Memory Interface Solutions (v1.9)
7 Series FPGAs Memory Interface Solutions (v1.9) DS176 March 20, 2013 Introduction The Xilinx 7 series FPGAs memory interface solutions cores provide high-performance connections to DDR3 and DDR2 SDRAMs,
Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting Authors: Bill Wilkie and Beth Cowie
Application Note: All Virtex and Spartan FPGA Families XAPP551 (1.0) February 14, 2005 R Viterbi Decoder Block Decoding - Trellis Termination and Tail Biting Authors: Bill Wilkie and Beth Cowie Summary
DCR Interrupt Controller (v2.00a)
DS429 April 24, 2009 Introduction A DCR (Device Control Register Bus v29) Interrupt Controller (INTC) core is composed of a bus-centric wrapper containing the INTC core and a DCR interface. The INTC core