SP605 GTP IBERT Design Creation

Transcription

1 SP605 GTP IBERT Design Creation October 2010 Copyright 2010 Xilinx XTP066

2 Revision History Date Version Description 10/05/ Recompiled under ARs Present in Spartan-6 IBERT Design: AR36775 Delay in ChipScope recognizing Core Units on Spartan-6 GTP Designs 07/23/ Recompiled under Added AR36775 Delay in ChipScope recognizing Core Units on Spartan-6 GTP Designs Copyright 2010 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This Presentation applies to the SP605 SP605 IBERT Overview Xilinx SP605 Board Software Requirements Setup for the SP605 IBERT Designs Running the SP605 IBERT Design SP605 IBERT Design Creation Create IBERT CORE Generator Project Create IBERT Design Create IBERT ACE File References

4 Note: Presentation applies to the SP605 SP605 IBERT Overview Description The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a pattern generation and verification design to exercise the Spartan-6 GTP transceivers. A graphical user interface is provided through the IBERT console window of the ChipScope Pro Analyzer Reference Design IP LogiCORE IBERT Example Designs PCIe (1), SMA (1), SFP (1), FMC_LPC (1) ChipScope Pro Analyzer ChipScope Pro Software and Cores User Guide (UG029)

5 Xilinx SP605 Board Note: Presentation applies to the SP605

6 Note: Presentation applies to the SP605 Software Requirements Xilinx ISE 12.3 software

7 Note: Presentation applies to the SP605 ChipScope Pro Software Requirement Xilinx ChipScope Pro 12.3 software

8 Setup for the SP605 IBERT Designs

9 Note: Presentation applies to the SP605 Setup for the SP605 IBERT Designs Unzip the rdf0036.zip file to your C:\ drive Available through

10 Setup for the SP605 IBERT Designs Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the SP605 board Connect this cable to your PC

11 Note: Presentation applies to the SP605 Setup for the SP605 IBERT Designs SMA Cable P/N: ASPI-024-ASPI-S402

12 Setup for the SP605 IBERT Designs Using the SMA cables: Connect J32 to J34 Note: Presentation applies to the SP605

13 Setup for the SP605 IBERT Designs Using the SMA cables: Connect J33 to J35 Note: Presentation applies to the SP605

14 Note: Presentation applies to the SP605 Setup for the SP605 IBERT Designs Connect Optical Loopback Adapter SFP Loopback Adapter, 3.5 db Attenuation Part # Alternatively, use an SFP transceiver with a fiber optic cable Insert into the SFP Connector on the SP605 board Connect the SP605 Power and turn the SP605 on

15 Running the SP605 IBERT Design

16 Note: Presentation applies to the SP605 Running the SP605 IBERT Design Open ChipScope Pro and click on the Open Cable Button (1) Click OK (2) 1 2

17 Note: Presentation applies to the SP605 Running the SP605 IBERT Design Select Device DEV:1 MyDevice1 (XC6SLX45T) Configure Select <Design Path>\ready_for_download\sp605_ibert_top.bit

18 Note: Presentation applies to the SP605 Running the SP605 IBERT Design Select File Open Project Select <Design Path>\ready_for_download\sp605_ibert.cpj

19 Note: Presentation applies to the SP605 Running the SP605 IBERT Design Click Yes on this Dialog

20 Note: Left to right: PCIe, SMA, SFP, FMC_LPC Running the SP605 IBERT Design The line rate is 2.5 Gbps for all four GTPs (1) Near-End PMA is selected for the PCIe and FMC GTPs (2) 1 2 2

21 Note: Presentation applies to the SP605 Running the SP605 IBERT Design TX Diff Output Swing = 695 mv (0100) TX Pre-emphasis = 1.7 db (010)

22 Note: Presentation applies to the SP605 Running the SP605 IBERT Design TX/RX Data Patterns are set to PRBS 7-bit (1) Click BERT Reset buttons (2) 1 2

23 Note: Presentation applies to the SP605 Running the SP605 IBERT Design View the RX Bit Error Count (1) 1

24 SP605 IBERT Design Creation

25 Note: Presentation applies to the SP605 Create IBERT CORE Generator Project Open the CORE Generator Start All Programs Xilinx ISE Design Suite 12.3 ISE Accessories CORE Generator Create a new project; select File New Project

26 Note: Presentation applies to the SP601 Generate MIG Example Design Create a project directory: sp605_ibert

27 Note: Presentation applies to the SP601 Generate MIG Example Design Name the project: sp605_ibert.cgp

28 Note: Presentation applies to the SP605 Create IBERT CORE Generator Project The Project options will appear Set the Part (as seen here): Family: Spartan6 Device: xc6slx45t Package: fgg484 Speed Grade: -3 Select Generation

29 Note: Presentation applies to the SP605 Create IBERT CORE Generator Project Under Generation Set the Design Entry to Verilog Click OK

30 Note: Presentation applies to the SP605 Create IBERT Design Right click on the IBERT Spartan6 GTP (ChipScope Pro - IBERT, Version 2.01a Select Customize and Generate

31 Create IBERT Design Make the following settings: Component name: sp605_ibert Set the number of Line Rates: 1 Set the line rate to Max Rate: 2.5 Gbps Set the RefClk frequency to: 125 MHz Click Next

32 Create IBERT Design Select both GTPs: GTPA_DUAL_X1_Y0 GTPA_DUAL_X0_Y0 Connect both Refclks to: REFCLK0 X1Y0 This connects both GTPs to the 125 MHz SFP Clock Click Next

33 Create IBERT Design Leave this screen as is Click Next

34 Create IBERT Design Select the following settings: Use External Clock source Frequency (MHz): 200 Location: K21 Input Standard: LVDS 25 Click Next

35 Create IBERT Design Deselect Implement Design Click Generate

36 Note: Presentation applies to the SP605 Create IBERT Design After the IBERT core finishes generating, click Close on the Datasheet window

37 Note: Presentation applies to the SP605 Compile IBERT Design Type these commands in a windows command shell: cd C:\sp605_ibert\sp605_ibert\implement implement.bat > implement.log 2>&1

38 Note: See AR36775 for details on using ChipScope with the IBERT ACE file Create IBERT ACE File (Optional) Type these commands in a windows command shell: cd C:\sp605_ibert\ready_for_download make_ace.bat

39 References

40 References ChipScope Pro ChipScope Pro Software and Cores User Guide xilinx12_3/chipscope_pro_sw_cores_ug029.pdf

41 Documentation

42 Documentation Spartan-6 Spartan-6 FPGA Family SP605 Documentation Spartan-6 FPGA SP605 Evaluation Kit SP605 Getting Started Guide SP605 Hardware User Guide SP605 Reference Design User Guide