KC705 Si5324 Design October 2012

Transcription

1 KC705 Si5324 Design October 2012 XTP188

2 Revision History Date Version Description 10/23/ Recompiled for /25/ Recompiled for Added AR /08/ Recompiled for /14/ Initial version for Copyright 2012 Xilinx, Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.

3 Note: This presentation applies to the KC705 Overview Xilinx KC705 Board Software Requirements KC705 Setup Reducing Jitter with the Si5324 Compile KC705 Si5324 Design References

4 Note: Presentation applies to the KC705 KC705 Si5324 Design Description Description The Si5324 application uses an EDK MicroBlaze system to change the settings for the Si5324 chip on the KC705 board via IIC Note: This design illustrates the relative differences of a Jitter Attenuator device in Bypass mode or in PLL mode. Neither the Evaluation board nor the design are for characterization purposes. Please see the Silicon Labs web site for Jitter Attenuator device data. Reference Design Source rdf0177.zip Available through

5 Xilinx KC705 Board

6 Note: Presentation applies to the KC705 ISE Software Requirement Xilinx ISE 14.3 software

7 Note: Presentation applies to the KC705 EDK Software Requirement Xilinx EDK 14.3 software

8 Note: Presentation applies to the KC705 EDK Software Requirement Xilinx SDK 14.3 software

9 KC705 Setup Connect a USB Type-A to Micro-B cable to the USB JTAG (Digilent) connector on the KC705 board Connect this cable to your PC Power on the KC705 board

10 Note: Presentation applies to the KC705 KC705 Si5324 Setup Unzip the KC705 Si5324 Design Files (14.3 C) Available through

11 Reducing Jitter with the Si5324

12 Note: Presentation applies to the KC705 Reducing Jitter with the Si5324 A means of measuring jitter is required for this section A LeCroy 816Zi-A Scope was used (stock photo shown)

13 Reducing Jitter with the Si5324 Connect SMA cables to J13 and J14, USER_GPIO_P/N Connect these cable to your oscilloscope

14 Note: Presentation applies to the KC705 Reducing Jitter with the Si5324 Open ChipScope Pro and select JTAG Chain Digilent USB Cable (1) Verify 30 MHz operation and click OK (2) 1 2

15 Note: Presentation applies to the KC705 Reducing Jitter with the Si5324 Click OK (1) 1

16 Note: Presentation applies to the KC705 Reducing Jitter with the Si5324 Select Device DEV:0 MyDevice0 (XC7K325T) Configure Select <Design Path>\ready_for_download\si5324_bypass.bit

17 Reducing Jitter with the Si5324 LeCroy Oscilloscope setup Press the Default Setup followed by the Auto Setup twice

18 Reducing Jitter with the Si5324 Adjust the Horizontal knob until you have 5 μs/div

19 Reducing Jitter with the Si5324 From the LeCroy scope menu, select Analysis Serial Data

20 Reducing Jitter with the Si5324 Select Quick View

21 Reducing Jitter with the Si5324 Set the inputs to Input1-Input2 and the Data to match your setup and click OK

22 Reducing Jitter with the Si5324 Click the Close button

23 Reducing Jitter with the Si5324 Note that the DCD (Duty Cycle Distortion) is 61.7 ps See LeCroy presentation on Jitter for explanation of values

24 Note: Presentation applies to the KC705 Reducing Jitter with the Si5324 Select Device DEV:0 MyDevice0 (XC7K325T) Configure Cycle power on the KC705 to clear out any previous settings in the Si5324 Select <Design Path>\ready_for_download\si5324_enabled.bit

25 Reducing Jitter with the Si5324 Note that the DCD (Duty Cycle Distortion) is 13.7 ps Including the Si5324 Jitter Attenuator PLL in the clock path, reduces DCD

26 Compile KC705 Si5324 Design

27 Compile KC705 Si5324 Design If desired, FPGA compile can be skipped by opening SDK directly: Start All Programs Xilinx Design Tools ISE Design Suite 14.3 EDK Xilinx Software Development Kit Select the workspace: <design files>\sw\sdk Go to SDK Software Compile

28 Note: Presentation applies to the KC705 Compile KC705 Si5324 Design Open XPS project <project directory>\ system.xmp Create the hardware design, system.bit, located in <project directory> /implementation Click the Generate Bitstream button (1) Or from the menu, select Hardware Generate Bitstream 1

29 Note: Presentation applies to the KC705 Launch KC705 Design in SDK Open SDK Click the Export Design button (1) Click Export & Launch SDK (2) 1 2

30 Compile KC705 Software in SDK SDK Software Compile - Build ELF files in SDK Select Project Build All (1) Note: If by-passing the FPGA compile, the ELF files are already built; if desired, the ELF files can be re-built by selecting Clean followed by Build All 1

31 Program KC705 with Si5324 Design

32 Program KC705 with Si5324 Design Init memory with the Si5324 Application ELF Update the bitstream (download.bit) with the Si5324 Application ELF Cycle power on the KC705 to clear out any previous settings in the Si5324 Select Xilinx Tools Program FPGA (1) 1

33 Note: Presentation applies to the KC705 Program KC705 with Si5324 Design Init memory with the Si5324 Application ELF Select hello_iic_5324.elf (1) Click Program 1

34 Program KC705 with Si5324 Design Note that the DCD (Duty Cycle Distortion) has a low value now

35 Note: Presentation applies to the KC705 Program KC705 with Si5324 Design To set the Si5324 for Bypass mode edit the hello_iic_si5324.c Locate the line: // Change to 1 to set Si5324 into Bypass PLL mode Change the #if 0 to #if 1

36 Note: Presentation applies to the KC705 Program KC705 with Si5324 Design To set the Si5324 for Bypass mode edit the hello_iic_si5324.c Scroll down and locate the line: // Change to 1 to set Si5324 Loop Bandwidth (BWSEL) Change the #if 1 to #if 0

37 Program KC705 with Si5324 Design Recompiled the ELF file Select Project Build All (1) 1

38 Program KC705 with Si5324 Design Init memory with the Si5324 Application ELF Update the bitstream (download.bit) with the Si5324 Application ELF Cycle power on the KC705 to clear out any previous settings in the Si5324 Select Xilinx Tools Program FPGA (1) 1

39 Note: Presentation applies to the KC705 Program KC705 with Si5324 Design Init memory with the Si5324 Application ELF Select hello_iic_5324.elf (1) Click Program 1

40 Program KC705 with Si5324 Design Note that the DCD (Duty Cycle Distortion) is now higher

41 References

42 References Silicon Labs SI5324 Data Sheet LeCroy Presentation Jitter and Jitter Breakdown Analysis ChipScope Pro ChipScope Pro Software and Cores User Guide xilinx14_3/chipscope_pro_sw_cores_ug029.pdf

43 Documentation

44 Documentation Kintex-7 Kintex-7 FPGA Family KC705 Documentation Kintex-7 FPGA KC705 Evaluation Kit KC705 Getting Started Guide ug883_k7_kc705_eval_kit.pdf KC705 User Guide ug810_kc705_eval_bd.pdf KC705 Reference Design User Guide ug845_ref_design.pdf