Laboratory 2(b): Configuring an ADC with MicroBlaze. Authors: Trung N. Tran (National Instruments) Jeff C. Jensen (National Instruments)

Transcription

1 Laboratory 2(b): Configuring an ADC with MicroBlaze Authors: Trung N. Tran (National Instruments) Jeff C. Jensen (National Instruments) Instructors: Edward A. Lee Sanjit A. Seshia University of California, Berkeley EECS 149 February 2, 2011

2 1 Introduction 1.1 Goals In part (a) of this lab, you interfaced a Nintendo WiiMote with a desktop computer. The embedded processor inside the WiiMote measured analog voltage from an accelerometer and transmitted the binary value of the measurement via Bluetooth. In this lab, you learn how to directly interface a processor with an analog-todigital converter (ADC). In this lab, you will: 1. Program and debug bare iron C code (code that executes in the absence of an operating system). 2. Learn about the MicroBlaze 32-bit microprocessor. 3. Configure an analog-to-digital converter (ADC) to interface an accelerometer. This lab should take 2 hours to complete. 1.2 Required Reading Read the following material in advance of your laboratory session: 1. Lee & Seshia [1] (a) Interrupts and Exceptions, pp (b) The Analog/Digital Interface, pp MicroBlaze Interrupts and the EDK [2] 3. MicroBlaze Processor Reference Guide [3] (a) Ch. 1, MicroBlaze Architecture Introduction, pp. 14. (b) Ch. 1, MicroBlaze Architecture Interrupt, pp Embedded System Tools Reference Guide [4] (a) Ch. 8, GNU Compiler Tools, Interrupt Handlers, pp OS and Libraries Document Collection [5] (a) LibXil Standard C Libraries, pp (b) MicroBlaze Processor API, pp LogiCORE IP XPS Interrupt Controller [6] (a) Interrupt Controller Core, pp. 4. (b) Proramming Model, pp LogiCORE IP XPS Timer/Counter [7] (a) Functional Description, pp (b) Register Descriptions, pp ADXL322: Small and Thin 2g Accelerometer [8] (a) Introduction, pp. 1. (b) Theory of Operation, pp

3 1.3 Equipment 1. PC computer running Windows XP. 2. National Instruments single-board RIO (sbrio) NI National Instruments NI PS-15 power supply. 4. Analog Devices ADXL-322 analog accelerometer. 5. Xilinx SDK 11.5 software. 6. Xilinx Platform Cable USB II (JTAG). The NI-9632 controller [9] is an embedded platform consisting of a PowerPC processor and a Xilinx FPGA. The PowerPC executes a real-time operating system that you will use later in the course; here, we wish to demonstrate low-level programming of an embedded processor, without the use of an operating system. This type of programming is referred to as bare-bones. We have programmed the FPGA on your sbrio with a soft-core processor; that is, the processor architecture has been written to the FPGA. The soft-core processor we use is the Xilinx MicroBlaze. This lab uses Xilinx development tools that target MicroBlaze. This includes a gdb debugger, and you are encouraged to use it. 2 Equipment Introduction 2.1 MicroBlaze Memory-Mapped Registers Memory-mapped registers are implemented with special hardware in MicroBlaze, since they directly control peripheral devices. Such registers may have bitfields that are read-only, write-only, or read/write. These fields are associated with special asynchronous hardware specific to reading or writing; take caution not to violate read/write specifications, as this may produce undefined results. In general, reading from a write-only bitfield will return zero. Timing is crucial when accessing memory-mapped registers. Avoid using operations that sequentially read and write to these registers; while these operations are synchronous with regard to memory, there is a propagation delay of three cycles to the peripheral bus. This is known as a read after write (RAW) hazard. Put simply, if you need to sequentially write to and then read from a memory-mapped register in MicroBlaze, you must wait three cycles in between. Use the assembly nop command: REGA = 0x0001; // Enable GPIO edge triggering asm("nop"); asm("nop"); // Wait for peripheral update asm("nop"); while(!(rega & 0x0002)); // Wait for trigger event 2.2 MicroBlaze Interrupts As is true for any interrupt controller, interrupt service routines should contain a minimum number of instructions. To illustrate why, consider a timer interrupt that is configured to periodically fire every 10 microseconds, but whose interrupt service routine takes 11 microseconds to execute. What should the behavior be? Also avoid using shared hardware resources, such as standard output, error streams, files, or hardware peripherals. This means you should not use print() statements inside interrupts. 2

4 PLB bus 1 Interrupt line TIMER BRAMs MicroBlaze Core ADC subsystem MicroBlaze Debug Module (MDM) Interrupt controller Figure 1: High-level block diagram of MicroBlaze / ADC interface. 3

5 MUX PLB bus ADC core ADC_CTRL_STAT register ADC_INT register ADC interrupt Figure 2: MicroBlaze inteface to the ADC on sbrio. 4

6 2.3 ADC Interface We have interfaced a MicroBlaze processor with the ADCs on sbrio (Fig. 1). Memory-mapped registers for GPIO on MicroBlaze have been directly connected to the ADCs on sbrio via FPGA fabric (Fig. 2); that is to say, memory-mapped registers in MicroBlaze are physically mapped to ADC control, status, and value lines. This feature is specific to sbrio and is not a standard component of MicroBlaze, however the implementation is equivalent to the use of standard GPIO memory-mapped registers on MicroBlaze. 2.4 ADC Configuration The ADC multiplexes up to seven channels, meaning only one channel may be sampled at a time. A conversion for a single channel samples and quantizes the input voltage range of [ 3V, 3V] into 16 bits. Each conversion takes 24µs to complete. The ADC control status register ADC CTRL STAT triggers conversions, signals a conversion is complete, and holds the result of a conversion (Fig. 3). 31 conversion result (16 bits) channel (8 bits) 16 unused (6 bits) 0 Figure 3: ADC Status and Control Register, ADC CTRL STAT. Bits 31-16: (read-only) ADC conversion result. Value is undefined while a conversion is in progress. Bits 15-8: (read/write) Channel selector; only values between 0-7 are valid for this ADC. Bits 2-7: (unused) Bit 1: (read only) Conversion complete bit. Indicates the ADC conversion result is stable. Bit 0: (write only) Trigger conversion. When 1 is written to ADC CTRL STAT Bit 0, an ADC conversion will begin. Bit 1 is automatically set to 0 in the same cycle that Bit 0 is written, indicating the ADC conversion result is unstable. 2.5 ADC Interrupts The ADC module can generate an interrupt when a conversion is complete on a single channel. interrupts are configured by the following three registers: ADC 1. ADCINT GIE Global Interrupt Enable register. (ADC GIE) 2. ADCINT IER Interrupt Programmable Interrupt Enable register (ADC IP IER). 3. ADCINT ISR Interrupt Programmable Interrupt Status register (ADC IP ISR). The ADC IER register enables the ADC peripheral to generate any interrupts, and the ADC GIE enables ADC interrupts to signal the MicroBlaze Master Interrupt Controller. Interrupt status is held in ADC ISR ADC Global Interrupt Enable Register (ADC GIE) The ADC Global Interrupt Enable register (ADC GIE) is the master gate for enabling/disabling interrupt signals to the MicroBlaze Master Interrupt Controller. The enable bit (Fig. 4) in this register must be set for ADC interrupts to be sent to the MicroBlaze interrupt controller. 5

7 2.5.2 ADC IP Interrupt Enable (ADC IP IER) The ADC IP Interrupt Enable register (ADC IP IER) enables ADC conversion complete interrupts. The enable bit (Fig. 5) must be set to generate conversion complete interrupts ADC IP Interrupt Status Register (ADC IP ISR) The ADC IP Interrupt Status Register (ADC IP ISR) indicates whether an interrupt has occurred. The Channel 1 Interrupt Status indicates a conversion complete interrupt has occured. Note: Channel 1 indicates the type of interrupt (conversion complete) and not the specific ADC channel that was sampled. The ADC Status register indicates which channel was read. 6

8 Figure 4: ADC Global Interrupt Enable Register (ADC GIE) Figure 5: ADC IP Interrupt Enable Register (ADC IP IER) and ADC IP Interrupt Status Register (ADC IP ISR). 7

9 3 3.1 Procedure Configure Equipment Connect the molex connector on the power supply to your sbrio, and plug the supply into the wall. The power LED on the sbrio will illuminate; a few seconds later, the FPGA user LED will begin to flash, indicating the FPGA has been programmed and is running MicroBlaze. Your JTAG device is used to download programs to MicroBlaze, and establishes communication between sbrio and your computer to enable debugging. Connect the JTAG device to your PC with a USB cable. The platform connector on the device is split into seven cables, six of which connect to an I/O connector on sbrio (one cable is unused). Your device should already be correctly configured, and we provide a wiring diagram as a reference in Fig. 6 and Table 1. When the JTAG device is correctly connected, and the sbrio is powered, the Status light on the device should illuminate green. Figure 6: Correct JTAG wiring. JTAG Wire GND TDO TDI TCK TMS VCC sbrio Pin Position Function ground Port0/DIO0 Port0/DIO1 Port0/DIO2 Port0/DIO3 +5V Table 1: JTAG wiring pin map. 8

10 3.2 Load the Template Project Download the archive lab02bfiles.zip from the course website to your computer, and extract it to the folder U:\EECS149. Avoid extracting to a location that has spaces in the path. From your desktop, launch the Xilinx SDK 11.5 development environment. This is an Eclipse-based environment that collects hardware targets, libraries, and source files into a single workspace, configures and scripts compilation tools, downloads compiled binaries to hardware targets, and establishes interactive debugging sessions. Upon launching, you will be asked to open a workspace. Navigate to the folder to which you extracted the template project, and select the subdirectory SDK Workspace; following the steps in this guide, the complete path will be U:\EECS149\Lab2b\SDK Workspace. If you did not save to the correct location, the SDK will be unable to locate a hardware specification file. You must manually point to this file, which it expects to find in U:\EECS149\Lab2b\SDK Export\hw \system.xml. 3.3 Review and Download the Template Code From your workspace, open the file ADC.c, which contains all of the source code that will be compiled for MicroBlaze. This is where you will write code to complete this lab. The template code will compile and download to the target without modification, but its functionality is incomplete. The template code is set up to use a timer interrupt to periodically poll one channel of the ADC, but the interrupt will not trigger until the primary interrupt service routine is registered, and the timer interrupt is configured. In the first objective, the timer interrupt service routine needs to be modified to read to and write from memory-mapped registers for the ADC to trigger a conversion, block until a conversion is complete, and save the conversion result to a global variable. First test that you can compile and download. Select the project (aptly called Project) from the navigation pane, and from the Project menu, select Build All to compile the project. Your code is compiled by a gcc compiler, and compilation output is printed to the output window in your workspace. After successful compilation, run your program on the target by opening the Run menu and selecting Run Last Launched. Debug messages are sent from the target to your computer over the JTAG device. The device creates a terminal session over TCP/IP, where print() messages are displayed in XMD Console pane of your workspace. To enable the terminal session, type the following command into the XMD% prompt at the bottom of the XMD Console pane: terminal which opens a terminal session between your computer and the MicroBlaze target. The this terminal is the standard output for print() statements on MicroBlaze. In some cases, the XMD% prompt is blank, and the message unknown command is printed when attempting to start a terminal session. This is a bug with the SDK and is resolved by simply restarting the application. The terminal session within the XMD Console is somewhat buggy and can cause the SDK to crash. Once you have initiated the terminal session, open the Windows HyperTerminal (Start Programs Accessories Communications), and open a TCP/IP session on localhost port The session will move from your XMD Console to the HyperTerminal window. The terminal can be left running without any side-effects, and is reset when you download new MicroBlaze code. Do not close the terminal, as a bug in the development environment sometimes causes the SDK to crash. You will need to reference the required reading to determine which function calls are necessary to complete these objectives. Comments in the source indicate suggested modifications; however, you are free to modify any part of the code. 9

11 4 Acknowledgment We thank the University of California, Berkeley, Department of EECS Instructional Support Group (ISG) and Electronics Support Group (ESG) for their continued efforts in supporting this lab. References [1] E.A. Lee and S.A. Seshia, Introduction to Embedded Systems - A Cyber-Physical Systems Approach, digital version Berkeley, California, Available: DigitalV1_03.pdf. [Accessed January 25 th, 2011]. [2] T. Hickok, MicroBlaze Interrupts and the EDK. Available: cpe-329/edk_resources/th_ublaze_interrupts.pdf. [Accessed January 27 th, 2011]. [3] Xilinx, MicroBlaze Processor Reference Guide version Available: support/documentation/sw_manuals/xilinx11/mb_ref_guide.pdf. [Accessed January 26 th, [4] Xilinx, Embedded System Tools Reference Guide version Available: support/documentation/sw_manuals/xilinx11/est_rm.pdf. [Accessed January 27 th, 2011]. [5] Xilinx, OS and Libraries Document Collection December 2 nd, 2009 edition. Available: xilinx.com/support/documentation/sw_manuals/xilinx11/oslib_rm.pdf. [Accessed January 27 th, 2011]. [6] Xilinx, LogiCORE IP XPS Interrupt Controller version 2.01a. Available: support/documentation/ip_documentation/xps_intc.pdf. [Accessed January 27 th, 2011]. [7] Xilinx, LogiCORE IP XPS Timer/Counter version 1.02a. Available: support/documentation/ip_documentation/xps_timer.pdf. [Accessed January 28 th, 2011]. [8] Analog Devices, ADXL322: Small and Thin 2g Accelerometer datasheet revision 0. Available: [Accessed January 30 th, 2011]. [9] National Instruments, NI sbrio-961x/963x/964x and NI sbrio-9621xt/9632xt/9642xt User Guide June 10 th, 2010 edition, National Instruments. Available: pdf. [Accessed January 27 th, 2011]. 10

12 5 Laboratory 2(b): Configuring an ADC with MicroBlaze Objectives and Checkout Name: Date: Lab Section: This portion of the lab is complete when you complete the following objectives: 1. ( / 50) Periodically poll one axis. (a) ( / 10) Register primaryisr() as an interrupt service routine. (b) ( / 20) Configure the timer to generate periodic interrupts, and verify the interrupts are being handled correctly. (c) ( / 20) Within timerisr(), poll a single ADC channel. Store the conversion result so that the main program loop will print() messages containing the conversion result. We leave polling both channels as a challenge exercise, because it requires avoiding read after write (RAW) hazards. 2. ( / 50) Use ADC interrupts instead of blocking to measure two channels. (a) ( / 10) Change the timer interrupt service routine to return immediately after triggering a conversion, and to multiplex between both analog channels. (b) ( / 20) Configure an interrupt service routine to handle the ADC conversion complete interrupt, and verify interrupts are being handled correctly. (c) ( / 20) Program the ADC interrupt service routine to store the conversion result in a global variable so that the main program loop will print() messages containing the conversion result. 3. ( / 0) BONUS (up to +5): Configure your timer interrupt service routine to sequentially poll both channels every time the interrupt fires. 6 Lab Writeup Prompts In your lab writeup, please address the following questions: 1. When is it better to poll an ADC, and when is it better to use interrupts? 2. Why do you need to insert assembly nop instructions between sequential read after write operations on some memory-mapped registers? 3. How do you read the current timer value for timer 0? 4. Why would you use a timer interrupt to poll the ADC instead of polling within the main() program loop? 11

13 7 Laboratory 2(b): Configuring an ADC with MicroBlaze Prelab Exercises Name: Date: Lab Section: 1. What is the effect of the C type modifier volatile? When should it be used? 2. Where is the MicroBlaze processor on sbrio? What type of processor is it? 3. How is an ADC conversion triggered on MicroBlaze? What indicates a conversion is complete? 4. After an ADC conversion is triggered, what value is in the ADC Data Value region of ADC CTRL STAT before conversion complete is signaled? 12

14 5. Table 2 shows an example memory-map for an embedded microcontroller. Consider the following C code: Device Address Range Size RAM FFF 32 KiB General-Purpose IO FF 256 B Sound Controller FF 256 B Video Controller A000 - A7FF 2 KiB ROM C000 - FFFF 16 KiB Table 2: Sample memory map for an embedded controller. 1 #d e f i n e GPIO BASE 0 x8000 ; 2 #d e f i n e GPIOA OFFSET 0 x0010 ; 3 #d e f i n e GPIOA ( ( ( v o l a t i l e i n t ) (GPIO BASE + GPIOA OFFSET) ) ) 4 v o l a t i l e i n t gpioavalue = ( v o l a t i l e i n t ) (GPIO BASE + GPIOA OFFSET) ; (a) Where in memory does the variable gpioavalue reside? (b) Where in memory does the variable gpioavalue point? (c) What is the effect of the statement GPIOA = (1 << 12);? (d) What is the effect of the statement gpioavalue = (1 << 12);? 13